#
max10
Here are 2 public repositories matching this topic...
Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
fpga
adc
systemverilog
pwm
decimation
dac
max10
sigma-delta-modulation
comb-filter
quarkus
sigma-delta
-
Updated
Apr 11, 2022 - SystemVerilog
Improve this page
Add a description, image, and links to the max10 topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the max10 topic, visit your repo's landing page and select "manage topics."