gds

Here are 3 public repositories matching this topic...

Khalique13 / dvsd_pe_sky130

This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.

rtl gds openlane

Updated Oct 16, 2021
Verilog

mattvenn / wrapped_rgb_mixer

Star

Demo project for the Zero to ASIC Course.

asic gds hdl

Updated Jan 4, 2023
Verilog

arhamhashmi01 / openlane-verification

Star

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

opensource verification synthesis gds cts netlist placement klayout floorplan openlane openlane-flow openlane-github- netlist-simulation-

Updated Mar 8, 2024
Verilog

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gds