cyclone-v
Here are 41 public repositories matching this topic...
VHDL programming about basic N-bit binary calculator ( + - x / ) for altera fpga cyclone v board
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Nov 27, 2022 - VHDL
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
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Jul 30, 2022 - SystemVerilog
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
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Aug 3, 2022 - SystemVerilog
A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇
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Apr 21, 2024 - Verilog
OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board
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May 6, 2019 - C++
An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.
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Feb 8, 2021 - VHDL
Verilog based HDMI for Cyclone V or Altera series
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Oct 4, 2022 - Verilog
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
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Jul 30, 2022 - SystemVerilog
A little sound mixer on Cyclone V FPGA board.
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Feb 3, 2020 - Verilog
Driver - Library for C applications using Altera's UART Core through Avalon Bus on Cyclone V.
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Jul 30, 2017 - C
Various lessons learned while designing an OV5640 camera display in VHDL/Embedded Linux on a Cyclone V SOC board
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Feb 22, 2022 - VHDL
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