cyclone-v
Here are 41 public repositories matching this topic...
OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board
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May 6, 2019 - C++
VHDL programming about basic N-bit binary calculator ( + - x / ) for altera fpga cyclone v board
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Nov 27, 2022 - VHDL
An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.
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Feb 8, 2021 - VHDL
Verilog based HDMI for Cyclone V or Altera series
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Oct 4, 2022 - Verilog
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
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Jul 30, 2022 - SystemVerilog
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
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Aug 3, 2022 - SystemVerilog
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
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Jul 30, 2022 - SystemVerilog
EV21 RISC Processor Design
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Jul 8, 2021 - Verilog
A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇
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Apr 21, 2024 - Verilog
A little sound mixer on Cyclone V FPGA board.
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Feb 3, 2020 - Verilog
Division Algorithms in FPGAs
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Nov 24, 2019 - VHDL
Implement HDMI output using only SystemVerilog and an Analog Devices ADV7513
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Feb 20, 2022 - SystemVerilog
C++ examples for accessing FPGA Soft-IP and Hard-IP with embedded Linux for Intel (ALTERA) SoC-FPGAs (Cyclone V)
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Jun 27, 2021 - C
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