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2,262 public repositories
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Updated
Jan 25, 2023
Verilog
A very rudimentary and haphazard CPU created in Verilog.
Updated
Dec 15, 2022
Verilog
Yet another simple MUNIN plugins
Updated
Apr 21, 2023
Shell
A simple implementation of a RISC-V core (RV32I) written in TL Verilog.
Updated
Jun 16, 2022
Verilog
Updated
Dec 30, 2022
SystemVerilog
An experimental RISC-V CPU designed in VHDL for the Digilent Arty A7.
RISC-V RV32I CPU core in SystemVerilog
Updated
Mar 15, 2023
SystemVerilog
Created my very own CPU and assembler!
Updated
Dec 22, 2022
Python
The implementation of a Five-Stage Pipelining RISC-V Microprocessor in Verilog HDL
Updated
Nov 14, 2022
VHDL
experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent
Updated
May 29, 2023
Verilog
experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent
Updated
Sep 10, 2023
Verilog
simple python cpu and gpu temp monitor with drag function for windows using pyqt
Updated
Jul 12, 2023
Python
experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent
Updated
Oct 24, 2023
Verilog
A processor built using VHDL that can execute assembly/machine codes.
z80ex library with my modifications
Designing Pipelined RISC Processor
Updated
Feb 6, 2019
Verilog
Projekt z Architektury Systemów Komputerowych - projekt mikroprocesora.
Bash script tools and utilities
Updated
Jun 19, 2020
Shell
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