{"payload":{"header_redesign_enabled":false,"results":[{"id":"362879751","archived":false,"color":"#b2b7f8","followers":22,"has_funding_file":false,"hl_name":"sumukhathrey/Verilog_ASIC_Design","hl_trunc_description":"Verilog for ASIC Design","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":362879751,"name":"Verilog_ASIC_Design","owner_id":60277422,"owner_login":"sumukhathrey","updated_at":"2021-09-13T02:43:56.712Z","has_issues":true}},"sponsorable":false,"topics":["counter","hardware","rtl","verilog","adder","testbench","gates","sequence-detector","hardware-modelling"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":85,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Asumukhathrey%252FVerilog_ASIC_Design%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/sumukhathrey/Verilog_ASIC_Design/star":{"post":"79GOEJJSaDvlSw5zbXLwNKQWjKd7FxtyNmPlx_i8IOAHlwYoEM4McZeqPDiwgONYtJH--1SYVVfdKgZkyjWYqg"},"/sumukhathrey/Verilog_ASIC_Design/unstar":{"post":"oMu0AyhkKZ8ZMDWOV4UgT4kZgqKjuH2Ygh4Prwj7rTqdzkFkEo2RPPuqXSe1zj63k42BZH6UG5IvNEaqRXmMIA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"XhOH-dvvCnTT0MHJWXk_pyx0NXeUcw59uTqFptwUT2Yx3C0-jAOy1K5xpLjw8fI-0_mhVHGQ3MPdI8cIj0kfqw"}}},"title":"Repository search results"}