# -------------------------------------------------------------------------- #
#
# Copyright (C) 2022  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
# Date created = 12:12:36  December 06, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		MaximatorZXSpectrum_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08DAF256C8G
set_global_assignment -name TOP_LEVEL_ENTITY MaximatorZXSpectrum
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:12:36  DECEMBER 06, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_E15 -to AUDIO_IN
set_location_assignment PIN_E16 -to AUDIO_OUT
set_location_assignment PIN_L3 -to CLOCK_10
set_location_assignment PIN_R15 -to KEY_RESET
set_location_assignment PIN_R16 -to LEDGTOP[3]
set_location_assignment PIN_P16 -to LEDGTOP[2]
set_location_assignment PIN_N16 -to LEDGTOP[1]
set_location_assignment PIN_M16 -to LEDGTOP[0]
set_location_assignment PIN_G15 -to PS2_CLK
set_location_assignment PIN_J15 -to PS2_DAT
set_location_assignment PIN_M1 -to VGA_B
set_location_assignment PIN_N1 -to VGA_G
set_location_assignment PIN_L1 -to VGA_HS
set_location_assignment PIN_R1 -to VGA_R
set_location_assignment PIN_J1 -to VGA_VS
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
set_location_assignment PIN_C15 -to INT_EN
set_location_assignment PIN_L16 -to KEY_NMI
set_location_assignment PIN_C16 -to TAPE_SOUND_EN
set_location_assignment PIN_D15 -to CPU_TURBO_EN
set_location_assignment PIN_D16 -to ULA_TURBO_EN
set_instance_assignment -name IO_STANDARD "2.5 V" -to VGA_VS
set_instance_assignment -name IO_STANDARD "2.5 V" -to VGA_R
set_instance_assignment -name IO_STANDARD "2.5 V" -to VGA_HS
set_instance_assignment -name IO_STANDARD "2.5 V" -to VGA_G
set_instance_assignment -name IO_STANDARD "2.5 V" -to VGA_B
set_instance_assignment -name IO_STANDARD "2.5 V" -to TAPE_SOUND_EN
set_instance_assignment -name IO_STANDARD "2.5 V" -to PS2_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDGTOP[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY_NMI
set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY_RESET
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDGTOP[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDGTOP[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDGTOP[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to PS2_DAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUDIO_IN
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUDIO_OUT
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_10
set_instance_assignment -name IO_STANDARD "2.5 V" -to INT_EN
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPU_TURBO_EN
set_instance_assignment -name IO_STANDARD "2.5 V" -to ULA_TURBO_EN
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_CLK_p
set_location_assignment PIN_T3 -to HDMI_CLK_n
set_location_assignment PIN_T2 -to HDMI_CLK_p
set_location_assignment PIN_T8 -to HDMI_HPD
set_location_assignment PIN_T7 -to HDMI_SCL
set_location_assignment PIN_T6 -to HDMI_SDA
set_location_assignment PIN_R6 -to HDMI_TX_n[2]
set_location_assignment PIN_R3 -to HDMI_TX_n[1]
set_location_assignment PIN_T5 -to HDMI_TX_n[0]
set_location_assignment PIN_R5 -to HDMI_TX_p[2]
set_location_assignment PIN_R2 -to HDMI_TX_p[1]
set_location_assignment PIN_T4 -to HDMI_TX_p[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_HPD
set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to HDMI_SDA
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_TX_p[2]
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_TX_p[1]
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_TX_p[0]
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_TX_n[2]
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_TX_n[1]
set_instance_assignment -name IO_STANDARD LVDS_E_3R -to HDMI_TX_n[0]
set_global_assignment -name SYSTEMVERILOG_FILE ula/vga_video.sv
set_global_assignment -name SYSTEMVERILOG_FILE ula/hdmi_video.sv
set_global_assignment -name SYSTEMVERILOG_FILE utils/DifferentialSignal.sv
set_global_assignment -name QIP_FILE ram16/ram16.qip
set_global_assignment -name QIP_FILE ula_pll/ula_pll.qip
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/tmds_channel.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/source_product_description_info_frame.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/serializer.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/packet_picker.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/packet_assembler.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/hdmi.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/auxiliary_video_information_info_frame.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/audio_sample_packet.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/audio_info_frame.sv
set_global_assignment -name SYSTEMVERILOG_FILE hdmi/audio_clock_regeneration_packet.sv
set_global_assignment -name SYSTEMVERILOG_FILE MaximatorZXSpectrum.sv
set_global_assignment -name SYSTEMVERILOG_FILE ula/zx_kbd.sv
set_global_assignment -name SYSTEMVERILOG_FILE ula/ula.sv
set_global_assignment -name SYSTEMVERILOG_FILE ula/ps2_kbd.sv
set_global_assignment -name VHDL_FILE ula/i2s_intf.vhd
set_global_assignment -name VHDL_FILE ula/i2c_loader.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ula/clocks.sv
set_global_assignment -name VERILOG_FILE cpu/z80_top_direct_n.v
set_global_assignment -name VERILOG_FILE cpu/sequencer.v
set_global_assignment -name VERILOG_FILE cpu/resets.v
set_global_assignment -name VERILOG_FILE cpu/reg_latch.v
set_global_assignment -name VERILOG_FILE cpu/reg_file.v
set_global_assignment -name VERILOG_FILE cpu/reg_control.v
set_global_assignment -name VERILOG_FILE cpu/pla_decode.v
set_global_assignment -name VERILOG_FILE cpu/pin_control.v
set_global_assignment -name VERILOG_FILE cpu/memory_ifc.v
set_global_assignment -name VERILOG_FILE cpu/ir.v
set_global_assignment -name VERILOG_FILE cpu/interrupts.v
set_global_assignment -name VERILOG_FILE cpu/inc_dec_2bit.v
set_global_assignment -name VERILOG_FILE cpu/inc_dec.v
set_global_assignment -name VERILOG_FILE cpu/execute.v
set_global_assignment -name VERILOG_FILE cpu/decode_state.v
set_global_assignment -name VERILOG_FILE cpu/data_switch_mask.v
set_global_assignment -name VERILOG_FILE cpu/data_switch.v
set_global_assignment -name VERILOG_FILE cpu/data_pins.v
set_global_assignment -name VERILOG_FILE cpu/control_pins_n.v
set_global_assignment -name VERILOG_FILE cpu/clk_delay.v
set_global_assignment -name VERILOG_FILE cpu/bus_switch.v
set_global_assignment -name VERILOG_FILE cpu/bus_control.v
set_global_assignment -name VERILOG_FILE cpu/alu_slice.v
set_global_assignment -name VERILOG_FILE cpu/alu_shifter_core.v
set_global_assignment -name VERILOG_FILE cpu/alu_select.v
set_global_assignment -name VERILOG_FILE cpu/alu_prep_daa.v
set_global_assignment -name VERILOG_FILE cpu/alu_mux_8.v
set_global_assignment -name VERILOG_FILE cpu/alu_mux_4.v
set_global_assignment -name VERILOG_FILE cpu/alu_mux_3z.v
set_global_assignment -name VERILOG_FILE cpu/alu_mux_2z.v
set_global_assignment -name VERILOG_FILE cpu/alu_mux_2.v
set_global_assignment -name VERILOG_FILE cpu/alu_flags.v
set_global_assignment -name VERILOG_FILE cpu/alu_core.v
set_global_assignment -name VERILOG_FILE cpu/alu_control.v
set_global_assignment -name VERILOG_FILE cpu/alu_bit_select.v
set_global_assignment -name VERILOG_FILE cpu/alu.v
set_global_assignment -name VERILOG_FILE cpu/address_pins.v
set_global_assignment -name VERILOG_FILE cpu/address_mux.v
set_global_assignment -name VERILOG_FILE cpu/address_latch.v
set_global_assignment -name QIP_FILE rom16/rom16.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top