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Commits on May 13, 2017

• controller: Fix precharge bit

  stffrdhrn

  committed
  cd6c4c5

• controller: fix rd_ready bit

  stffrdhrn

  committed
  2500c15

Commits on Apr 26, 2017

• controller: Fix whitespace

  stffrdhrn

  committed
  931cbc0

Commits on Feb 3, 2017

• Remove last sdram file

  stffrdhrn

  committed
  abf41c4

• Remove unused files

  stffrdhrn

  committed
  44931f2

• Add the generated project files from fusesoc

  stffrdhrn

  committed
  dde0db0

Commits on Sep 13, 2016

• fusesoc: convert to filesets and make top and tb stuff private

  stffrdhrn

  committed
  8d3b20f

Commits on Aug 26, 2016

• fifo/ctrl: Add fixes from digi recorder project

  stffrdhrn

  committed
  f0f8cbd

• readme: add some details on the build

  stffrdhrn

  committed
  37dd0d6

• testcases: get test cases working

  stffrdhrn

  committed
  9d2356c

• toplevel: finish toplevel wiring

  stffrdhrn

  committed
  74e5999

Commits on Aug 25, 2016

• Merge branch 'master' of github.com:stffrdhrn/sdram-controller

  stffrdhrn

  committed
  3e4ff4b

• fusesoc: adding fusesoc build for sdram

  stffrdhrn

  committed
  443f9d8

Commits on Jun 22, 2015

• Update diagram to match current implementation

  stffrdhrn

  committed
  e881013

Commits on Jun 18, 2015

• fix schematic

  stffrdhrn

  committed
  512f1da

• update image

  stffrdhrn

  committed
  b93bb43

• add an image of the top schematic

  stffrdhrn

  committed
  160081a

• status is stable again

  stffrdhrn

  committed
  a4d58b2

• fix some wiring

  stffrdhrn

  committed
  dd3f724

• make sure we define the widths

  stffrdhrn

  committed
  32d94cd

• fix a few isues with toplevel

  stffrdhrn

  committed
  c6dfb3d

• wire everything together

  stffrdhrn

  committed
  607f8d0

• working on cdc

  stffrdhrn

  committed
  e4e6f00

Commits on Jun 15, 2015

• Add small test to confirm fifo works

  stffrdhrn

  committed
  7564961

Commits on Jun 14, 2015

• forgot to use syncrhonized signal

  stffrdhrn

  committed
  df23d83

• working on fifo and moving interface to 1Mhz low freq clock

  stffrdhrn

  committed
  bd9a758

Commits on Jun 9, 2015

• Merge branch 'master' of github.com:stffrdhrn/sdram-controller

  stffrdhrn

  committed
  7b9864c

• make the controller all register on the posedge (more simple pipelining to sdram)

  stffrdhrn

  committed
  f4a07e3

Commits on Jun 6, 2015

• forgot one

  stffrdhrn

  committed
  51dc07e

• change non-blocking combinational logic to block (cliff cummings)

  stffrdhrn

  committed
  eeda475

Commits on Jun 4, 2015

• fix some typos

  stffrdhrn

  committed
  ba85b1b

Commits on Jun 3, 2015

• update readme

  stffrdhrn

  committed
  0dd063c

• update readme

  stffrdhrn

  committed
  102a9a5

• update readme

  stffrdhrn

  committed
  ebab587

Commits on Jun 2, 2015

• add block diagram

  stffrdhrn

  committed
  864bfc1

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