OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

CUGR, VLSI Global Routing Tool Developed by CUHK

CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)

Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization

Deep learning toolkit-enabled VLSI placement

Pin-Accessible Legalization for Mixed-Cell-Height Circuits

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

Python iterface for Cadence LEF/DEF parser.

An open-source static random access memory (SRAM) compiler.

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the s…

DREAMPlaceFPGA for MLCAD23 contest

reference block design for the ASAP7nm library in Cadence Innovus

liberty parser (For parsing IC timing lib file)

Mirror of Synopsys's Liberty parser library

GPU-accelerated RePlAce