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Intel Quartus Prime demo FPGA project
File Name FPGA supported Board name Description Documentation
"D10STDNANO_DDR3.qprs "
Cyclone V every Cyclone V BoardSystem DDR3 memory configuration script
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"DE0NANOrsyocto.qar "
Cyclone V Terasic DE10-Nano Quartus prime archive file of the default FPGA configuration
Info Papers
"DE0NANOrsyocto.v "
Cyclone V Terasic DE10-Nano The top-level Verilog file
Info Papers
"DE10STDrsyocto.qar "
Cyclone V Terasic DE10-Standard Quartus prime archive file of the default FPGA configuration
Info Papers
"DE10STDrsyocto.v "
Cyclone V Terasic DE10-Nano The top-level Verilog file
Info Papers
"DE0NANOrsyocto.qar "
Cyclone V Terasic DE0-Nano SoC Quartus prime archive file of the default FPGA configuration
Info Papers
"DE0NANOrsyocto.v "
Cyclone V Terasic DE0-Nano SoC The top-level Verilog file
Info Papers
"DE10NANO_NIOS.qar "
Cyclone V Terasic DE10-Nano Quartus prime archive file with a NIOS II processor accessing HPS Hard-IP
Guide
"DE10STD_NIOS.qar "
Cyclone V Terasic DE10-Standard Quartus prime archive file with a NIOS II processor accessing HPS Hard-IP
Guide
"DE0NANO_NIOS.qar "
Cyclone V Terasic DE10-Nano SoC Quartus prime archive file with a NIOS II processor accessing HPS Hard-IP
Guide
For the Terasic DE10 Standard Board
Unzip the project with Intel Quartus Prime
Copy the folder "ip" (sub folder: fpga/DE10STD_IP/ ) into the main Quartus Prime Project directory (Folder: DE10STDrsyocto )
Build the project (the IP should now be found)
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