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azure-pipelines.yml
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azure-pipelines.yml
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Azure Pipelines CI build configuration
# Documentation at https://aka.ms/yaml
variables:
- template: ci/vars.yml
trigger:
batch: true
branches:
include:
- '*'
tags:
include:
- '*'
pr:
branches:
include:
- '*'
# Note: All tests run as part of one job to avoid copying intermediate build
# artifacts around (e.g. Verilator and toolchain builds). Once more builds/tests
# are added, we need to re-evaluate this decision to parallelize jobs and
# improve end-to-end CI times.
jobs:
- job: lint_dv
displayName: Run quality checks (Lint and DV)
pool:
vmImage: "ubuntu-16.04"
steps:
- bash: |
ci/install-build-deps.sh
displayName: Install build dependencies
- bash: |
echo $PATH
python3 --version
echo -n "fusesoc "
fusesoc --version
verilator --version
riscv32-unknown-elf-gcc --version
verible-verilog-lint --version
displayName: Display environment
# Verible format is experimental so only run on default config for now,
# will eventually become part of the per-config CI
- bash: |
fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core_tracing
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
echo "This flow is currently experimental and failures can be ignored."
fi
# Show diff of what verilog_format would have changed, and then revert.
git diff
git reset --hard HEAD
continueOnError: true
displayName: Format all source code with Verible format (experimental)
- bash: |
fork_origin=$(git merge-base --fork-point origin/master)
changed_files=$(git diff --name-only $fork_origin | grep -v '^vendor' | grep -E '\.(cpp|cc|c|h)$')
test -z "$changed_files" || git diff -U0 $fork_origin $changed_files | clang-format-diff -p1 | tee clang-format-output
if [ -s clang-format-output ]; then
echo -n "##vso[task.logissue type=error]"
echo "C/C++ lint failed. Use 'git clang-format' with appropriate options to reformat the changed code."
exit 1
fi
# This check is not idempotent, but checks changes to a base branch.
# Run it only on pull requests.
condition: eq(variables['Build.Reason'], 'PullRequest')
displayName: 'Use clang-format to check C/C++ coding style'
- bash: |
# Build and run CSR testbench, chosen Ibex configuration does not effect
# this so doesn't need to be part of per-config CI
fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:ibex:tb_cs_registers
displayName: Build and run CSR testbench with Verilator
- bash: |
cd build
git clone https://github.com/riscv/riscv-compliance.git
cd riscv-compliance
git checkout "$RISCV_COMPLIANCE_GIT_VERSION"
displayName: Get RISC-V Compliance test suite
# Run Ibex RTL CI per supported configuration
- template : ci/ibex-rtl-ci-steps.yml
parameters:
ibex_configs:
# Note: Try to keep the list of configurations in sync with the one used
# in Private CI.
- small
- experimental-maxperf-pmp
- experimental-maxperf-pmp-bmfull
- experimental-maxperf-pmp-bmfull-icache
- experimental-branch-predictor
# Run lint on simple system
- bash: |
fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog lint with Verilator failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system' to check and fix all errors."
exit 1
fi
displayName: Run Verilator lint on simple system
- bash: |
fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system' to check and fix all errors."
exit 1
fi
displayName: Run Verible lint on simple system