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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
VexRiscv-SMP integration test with LiteX.
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
MiSTer SD card installer (Windows 64bit)
IC design and development should be faster,simpler and more reliable
有趣的Python爬虫和Python数据分析小项目(Some interesting Python crawlers and data analysis projects)