personal practice

Linux kernel source tree

SoC based on VexRiscv and ICE40 UP5K

Arduino compatible Risc-V Based SOC

Linux on LiteX-VexRiscv

Build your hardware, easily!

32-bit Superscalar RISC-V CPU

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

RISC-V CPU Core (RV32IM)

VexRiscv-SMP integration test with LiteX.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

Daughter boards

MiSTer SD card installer (Windows 64bit)

Main MiSTer binary and Wiki

IC design and development should be faster，simpler and more reliable

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

HDL libraries and projects

有趣的Python爬虫和Python数据分析小项目(Some interesting Python crawlers and data analysis projects)