- Madrid, Spain - Dubai, UAE
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19:50
(UTC +04:00) - https://piranna.github.io
- https://orcid.org/0009-0008-5916-4620
- @el_piranna
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Language: Verilog
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Must-have verilog systemverilog modules
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Repository for basic (and not so basic) Verilog blocks with high re-use potential
synthesiseable ieee 754 floating point library in verilog
An open source SPI flash emulator and monitor
🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
A simple, basic, formally verified UART controller
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
Minimax: a Compressed-First, Microcoded RISC-V CPU
🌱 ❄️ Collection of open-source peripherals in Verilog
IceChips is a library of all common discrete logic devices in Verilog
Regression test suite for Icarus Verilog. (OBSOLETE)
Public examples of ICE40 HX8K examples using Icestorm