- Madrid, Spain - Dubai, UAE
-
11:17
(UTC +04:00) - https://piranna.github.io
- https://orcid.org/0009-0008-5916-4620
- @el_piranna
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10
stars
written in SystemVerilog
Clear filter
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A Verilog synthesis flow for Minecraft redstone circuits
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A Linux-capable RISC-V multicore for and by the world
The root repo for lowRISC project and FPGA demos.
BaseJump STL: A Standard Template Library for SystemVerilog
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Simple hash table on Verilog (SystemVerilog)