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sse2rvv.h
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sse2rvv.h
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#ifndef SSE2RVV_H
#define SSE2RVV_H
// This header file provides a simple API translation layer
// between SSE intrinsics to their corresponding RVV versions
/*
* sse2rvv is freely redistributable under the MIT License.
*
* Copyright (c) 2023-2024 SSE2RVV Contributors.
*
* Contributors to this work are:
* Yang Hau <[email protected]>
* Cheng-Hao <[email protected]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* compiler specific definitions */
#if defined(__GNUC__) || defined(__clang__)
#pragma push_macro("FORCE_INLINE")
#pragma push_macro("ALIGN_STRUCT")
#define FORCE_INLINE static inline __attribute__((always_inline))
#define ALIGN_STRUCT(x) __attribute__((aligned(x)))
#define _sse2rvv_likely(x) __builtin_expect(!!(x), 1)
#define _sse2rvv_unlikely(x) __builtin_expect(!!(x), 0)
#else
#pragma message("Macro name collisions may happen with unsupported compilers.")
#endif
/* C language does not allow initializing a variable with a function call. */
#ifdef __cplusplus
#define _sse2rvv_const static const
#else
#define _sse2rvv_const const
#endif
#include <math.h>
#include <riscv_vector.h>
#include <stdint.h>
#include <stdlib.h>
/* A few intrinsics accept traditional data types like ints or floats, but
* most operate on data types that are specific to SSE.
* If a vector type ends in d, it contains doubles, and if it does not have
* a suffix, it contains floats. An integer vector type can contain any type
* of integer, from chars to shorts to unsigned long longs.
*/
typedef vint32m1_t __m64; /* 64-bit vector containing integers */
typedef vfloat32m1_t __m128; /* 128-bit vector containing 4 floats */
typedef vfloat64m1_t __m128d; /* 128-bit vector containing 2 doubles */
typedef vint32m1_t __m128i; /* 128-bit vector containing integers */
// A struct is defined in this header file called 'SIMDVec' which can be used
// by applications which attempt to access the contents of an __m128 struct
// directly. It is important to note that accessing the __m128 struct directly
// is bad coding practice by Microsoft: @see:
// https://learn.microsoft.com/en-us/cpp/cpp/m128
//
// However, some legacy source code may try to access the contents of an __m128
// struct directly so the developer can use the SIMDVec as an alias for it. Any
// casting must be done manually by the developer, as you cannot cast or
// otherwise alias the base NEON data type for intrinsic operations.
//
// union intended to allow direct access to an __m128 variable using the names
// that the MSVC compiler provides. This union should really only be used when
// trying to access the members of the vector as integer values. GCC/clang
// allow native access to the float members through a simple array access
// operator (in C since 4.6, in C++ since 4.8).
//
// Ideally direct accesses to SIMD vectors should not be used since it can cause
// a performance hit. If it really is needed however, the original __m128
// variable can be aliased with a pointer to this union and used to access
// individual components. The use of this union should be hidden behind a macro
// that is used throughout the codebase to access the members instead of always
// declaring this type of variable.
typedef union ALIGN_STRUCT(16) SIMDVec {
float m128_f32[4]; // as floats - DON'T USE. Added for convenience.
int8_t m128_i8[16]; // as signed 8-bit integers.
int16_t m128_i16[8]; // as signed 16-bit integers.
int32_t m128_i32[4]; // as signed 32-bit integers.
int64_t m128_i64[2]; // as signed 64-bit integers.
uint8_t m128_u8[16]; // as unsigned 8-bit integers.
uint16_t m128_u16[8]; // as unsigned 16-bit integers.
uint32_t m128_u32[4]; // as unsigned 32-bit integers.
uint64_t m128_u64[2]; // as unsigned 64-bit integers.
} SIMDVec;
#define vreinterpretq_m128_u8(x) \
__riscv_vreinterpret_v_u32m1_u8m1(__riscv_vreinterpret_v_f32m1_u32m1(x))
#define vreinterpretq_m128_u16(x) \
__riscv_vreinterpret_v_u32m1_u16m1(__riscv_vreinterpret_v_f32m1_u32m1(x))
#define vreinterpretq_m128_u32(x) __riscv_vreinterpret_v_f32m1_u32m1(x)
#define vreinterpretq_m128_u64(x) \
__riscv_vreinterpret_v_u32m1_u64m1(__riscv_vreinterpret_v_f32m1_u32m1(x))
#define vreinterpretq_m128_i8(x) \
__riscv_vreinterpret_v_i32m1_i8m1(__riscv_vreinterpret_v_f32m1_i32m1(x))
#define vreinterpretq_m128_i16(x) \
__riscv_vreinterpret_v_i32m1_i16m1(__riscv_vreinterpret_v_f32m1_i32m1(x))
#define vreinterpretq_m128_i32(x) __riscv_vreinterpret_v_f32m1_i32m1(x)
#define vreinterpretq_m128_i64(x) \
__riscv_vreinterpret_v_i32m1_i64m1(__riscv_vreinterpret_v_f32m1_i32m1(x))
#define vreinterpretq_m128_f32(x) (x)
#define vreinterpretq_m128_f64(x) \
__riscv_vreinterpret_v_u64m1_f64m1(__riscv_vreinterpret_v_u32m1_u64m1( \
__riscv_vreinterpret_v_f32m1_u32m1(x)))
#define vreinterpretq_u8_m128(x) \
__riscv_vreinterpret_v_u32m1_f32m1(__riscv_vreinterpret_v_u8m1_u32m1(x))
#define vreinterpretq_u16_m128(x) \
__riscv_vreinterpret_v_u32m1_f32m1(__riscv_vreinterpret_v_u16m1_u32m1(x))
#define vreinterpretq_u32_m128(x) __riscv_vreinterpret_v_u32m1_f32m1(x)
#define vreinterpretq_u64_m128(x) \
__riscv_vreinterpret_v_u32m1_f32m1(__riscv_vreinterpret_v_u64m1_u32m1(x))
#define vreinterpretq_i8_m128(x) \
__riscv_vreinterpret_v_i32m1_f32m1(__riscv_vreinterpret_v_i8m1_i32m1(x))
#define vreinterpretq_i16_m128(x) \
__riscv_vreinterpret_v_i32m1_f32m1(__riscv_vreinterpret_v_i16m1_i32m1(x))
#define vreinterpretq_i32_m128(x) __riscv_vreinterpret_v_i32m1_f32m1(x)
#define vreinterpretq_i64_m128(x) \
__riscv_vreinterpret_v_i32m1_f32m1(__riscv_vreinterpret_v_i64m1_i32m1(x))
#define vreinterpretq_f32_m128(x) (x)
#define vreinterpretq_f64_m128(x) \
__riscv_vreinterpret_v_u32m1_f32m1(__riscv_vreinterpret_v_u64m1_u32m1( \
__riscv_vreinterpret_v_f64m1_u64m1(x)))
#define vreinterpretq_m128d_u8(x) \
__riscv_vreinterpret_v_u64m1_u8m1(__riscv_vreinterpret_v_f64m1_u64m1(x))
#define vreinterpretq_m128d_u16(x) \
__riscv_vreinterpret_v_u64m1_u16m1(__riscv_vreinterpret_v_f64m1_u64m1(x))
#define vreinterpretq_m128d_u32(x) \
__riscv_vreinterpret_v_u64m1_u32m1(__riscv_vreinterpret_v_f64m1_u64m1(x))
#define vreinterpretq_m128d_u64(x) __riscv_vreinterpret_v_f64m1_u64m1(x)
#define vreinterpretq_m128d_i8(x) \
__riscv_vreinterpret_v_i64m1_i8m1(__riscv_vreinterpret_v_f64m1_i64m1(x))
#define vreinterpretq_m128d_i16(x) \
__riscv_vreinterpret_v_i64m1_i16m1(__riscv_vreinterpret_v_f64m1_i64m1(x))
#define vreinterpretq_m128d_i32(x) \
__riscv_vreinterpret_v_i64m1_i32m1(__riscv_vreinterpret_v_f64m1_i64m1(x))
#define vreinterpretq_m128d_i64(x) __riscv_vreinterpret_v_f64m1_i64m1(x)
#define vreinterpretq_m128d_f32(x) \
__riscv_vreinterpret_v_i32m1_f32m1(__riscv_vreinterpret_v_i64m1_i32m1( \
__riscv_vreinterpret_v_f64m1_i64m1(x)))
#define vreinterpretq_m128d_f64(x) (x)
#define vreinterpretq_u8_m128d(x) \
__riscv_vreinterpret_v_u64m1_f64m1(__riscv_vreinterpret_v_u8m1_u64m1(x))
#define vreinterpretq_u16_m128d(x) \
__riscv_vreinterpret_v_u64m1_f64m1(__riscv_vreinterpret_v_u16m1_u64m1(x))
#define vreinterpretq_u32_m128d(x) \
__riscv_vreinterpret_v_u64m1_f64m1(__riscv_vreinterpret_v_u32m1_u64m1(x))
#define vreinterpretq_u64_m128d(x) __riscv_vreinterpret_v_u64m1_f64m1(x)
#define vreinterpretq_i8_m128d(x) \
__riscv_vreinterpret_v_i64m1_f64m1(__riscv_vreinterpret_v_i8m1_i64m1(x))
#define vreinterpretq_i16_m128d(x) \
__riscv_vreinterpret_v_i64m1_f64m1(__riscv_vreinterpret_v_i16m1_i64m1(x))
#define vreinterpretq_i32_m128d(x) \
__riscv_vreinterpret_v_i64m1_f64m1(__riscv_vreinterpret_v_i32m1_i64m1(x))
#define vreinterpretq_i64_m128d(x) __riscv_vreinterpret_v_i64m1_f64m1(x)
#define vreinterpretq_f32_m128d(x) \
__riscv_vreinterpret_v_i64m1_f64m1(__riscv_vreinterpret_v_i32m1_i64m1( \
__riscv_vreinterpret_v_f32m1_i32m1(x)))
#define vreinterpretq_f64_m128d(x) (x)
#define vreinterpretq_m128i_u8(x) \
__riscv_vreinterpret_v_u32m1_u8m1(__riscv_vreinterpret_v_i32m1_u32m1(x))
#define vreinterpretq_m128i_u16(x) \
__riscv_vreinterpret_v_u32m1_u16m1(__riscv_vreinterpret_v_i32m1_u32m1(x))
#define vreinterpretq_m128i_u32(x) __riscv_vreinterpret_v_i32m1_u32m1(x)
#define vreinterpretq_m128i_u64(x) \
__riscv_vreinterpret_v_u32m1_u64m1(__riscv_vreinterpret_v_i32m1_u32m1(x))
#define vreinterpretq_m128i_i8(x) __riscv_vreinterpret_v_i32m1_i8m1(x)
#define vreinterpretq_m128i_i16(x) __riscv_vreinterpret_v_i32m1_i16m1(x)
#define vreinterpretq_m128i_i32(x) (x)
#define vreinterpretq_m128i_i64(x) __riscv_vreinterpret_v_i32m1_i64m1(x)
#define vreinterpretq_m128i_f32(x) __riscv_vreinterpret_v_i32m1_f32m1(x)
#define vreinterpretq_m128i_f64(x) \
__riscv_vreinterpret_v_f32m1_f64m1(__riscv_vreinterpret_v_i32m1_f32m1(x))
#define vreinterpretq_u8_m128i(x) \
__riscv_vreinterpret_v_u32m1_i32m1(__riscv_vreinterpret_v_u8m1_u32m1(x))
#define vreinterpretq_u16_m128i(x) \
__riscv_vreinterpret_v_u32m1_i32m1(__riscv_vreinterpret_v_u16m1_u32m1(x))
#define vreinterpretq_u32_m128i(x) __riscv_vreinterpret_v_u32m1_i32m1(x)
#define vreinterpretq_u64_m128i(x) \
__riscv_vreinterpret_v_u32m1_i32m1(__riscv_vreinterpret_v_u64m1_u32m1(x))
#define vreinterpretq_i8_m128i(x) __riscv_vreinterpret_v_i8m1_i32m1(x)
#define vreinterpretq_i16_m128i(x) __riscv_vreinterpret_v_i16m1_i32m1(x)
#define vreinterpretq_i32_m128i(x) (x)
#define vreinterpretq_i64_m128i(x) __riscv_vreinterpret_v_i64m1_i32m1(x)
#define vreinterpretq_f32_m128i(x) __riscv_vreinterpret_v_f32m1_i32m1(x)
#define vreinterpretq_f64_m128i(x) \
__riscv_vreinterpret_v_i64m1_i32m1(__riscv_vreinterpret_v_f64m1_i64m1(x))
#define vreinterpretq_m64_u8(x) \
__riscv_vreinterpret_v_u32m1_u8m1(__riscv_vreinterpret_v_i32m1_u32m1(x))
#define vreinterpretq_m64_u16(x) \
__riscv_vreinterpret_v_u32m1_u16m1(__riscv_vreinterpret_v_i32m1_u32m1(x))
#define vreinterpretq_m64_u32(x) __riscv_vreinterpret_v_i32m1_u32m1(x)
#define vreinterpretq_m64_u64(x) \
__riscv_vreinterpret_v_f64m1_u64m1(__riscv_vreinterpret_v_f32m1_f64m1(x))
#define vreinterpretq_m64_i8(x) __riscv_vreinterpret_v_i32m1_i8m1(x)
#define vreinterpretq_m64_i16(x) __riscv_vreinterpret_v_i32m1_i16m1(x)
#define vreinterpretq_m64_i32(x) (x)
#define vreinterpretq_m64_i64(x) __riscv_vreinterpret_v_i32m1_i64m1(x)
#define vreinterpretq_m64_f32(x) __riscv_vreinterpret_v_i32m1_f32m1(x)
#define vreinterpretq_m64_f64(x) \
__riscv_vreinterpret_v_i64m1_f64m1(__riscv_vreinterpret_v_i32m1_i64m1(x))
#define vreinterpretq_u8_m64(x) \
__riscv_vreinterpret_v_u32m1_i32m1(__riscv_vreinterpret_v_u8m1_u32m1(x))
#define vreinterpretq_u16_m64(x) \
__riscv_vreinterpret_v_u32m1_i32m1(__riscv_vreinterpret_v_u16m1_u32m1(x))
#define vreinterpretq_u32_m64(x) __riscv_vreinterpret_v_u32m1_f32m1(x)
#define vreinterpretq_u64_m64(x) \
__riscv_vreinterpret_v_u32m1_i32m1(__riscv_vreinterpret_v_u64m1_u32m1(x))
#define vreinterpretq_i8_m64(x) __riscv_vreinterpret_v_i8m1_i32m1(x)
#define vreinterpretq_i16_m64(x) __riscv_vreinterpret_v_i16m1_i32m1(x)
#define vreinterpretq_i32_m64(x) (x)
#define vreinterpretq_i64_m64(x) __riscv_vreinterpret_v_i64m1_i32m1(x)
#define vreinterpretq_f32_m64(x) __riscv_vreinterpret_v_f32m1_i32m1(x)
#define vreinterpretq_f64_m64(x) \
__riscv_vreinterpret_v_i64m1_i32m1(__riscv_vreinterpret_v_f64m1_i64m1(x))
// __int64 is defined in the Intrinsics Guide which maps to different datatype
// in different data model
#if !(defined(_WIN32) || defined(_WIN64) || defined(__int64))
#if (defined(__x86_64__) || defined(__i386__))
#define __int64 long long
#else
#define __int64 int64_t
#endif
#endif
// forward declaration
FORCE_INLINE int _mm_extract_pi16(__m64 a, int imm8);
FORCE_INLINE __m64 _mm_sad_pu8(__m64 a, __m64 b);
FORCE_INLINE __m64 _mm_shuffle_pi16(__m64 a, int imm8);
/* SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 */
FORCE_INLINE __m128i _mm_abs_epi16(__m128i a) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t mask = __riscv_vsra_vx_i16m1(_a, 15, 8);
vint16m1_t a_xor = __riscv_vxor_vv_i16m1(_a, mask, 8);
return vreinterpretq_i16_m128i(__riscv_vsub_vv_i16m1(a_xor, mask, 8));
}
FORCE_INLINE __m128i _mm_abs_epi32(__m128i a) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t mask = __riscv_vsra_vx_i32m1(_a, 31, 4);
vint32m1_t a_xor = __riscv_vxor_vv_i32m1(_a, mask, 4);
return vreinterpretq_i32_m128i(__riscv_vsub_vv_i32m1(a_xor, mask, 4));
}
FORCE_INLINE __m128i _mm_abs_epi8(__m128i a) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t mask = __riscv_vsra_vx_i8m1(_a, 7, 16);
vint8m1_t a_xor = __riscv_vxor_vv_i8m1(_a, mask, 16);
return vreinterpretq_i8_m128i(__riscv_vsub_vv_i8m1(a_xor, mask, 16));
}
FORCE_INLINE __m64 _mm_abs_pi16(__m64 a) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t mask = __riscv_vsra_vx_i16m1(_a, 15, 4);
vint16m1_t a_xor = __riscv_vxor_vv_i16m1(_a, mask, 4);
return vreinterpretq_i16_m128i(__riscv_vsub_vv_i16m1(a_xor, mask, 4));
}
FORCE_INLINE __m64 _mm_abs_pi32(__m64 a) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t mask = __riscv_vsra_vx_i32m1(_a, 31, 2);
vint32m1_t a_xor = __riscv_vxor_vv_i32m1(_a, mask, 2);
return vreinterpretq_i32_m128i(__riscv_vsub_vv_i32m1(a_xor, mask, 2));
}
FORCE_INLINE __m64 _mm_abs_pi8(__m64 a) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t mask = __riscv_vsra_vx_i8m1(_a, 7, 8);
vint8m1_t a_xor = __riscv_vxor_vv_i8m1(_a, mask, 8);
return vreinterpretq_i8_m128i(__riscv_vsub_vv_i8m1(a_xor, mask, 8));
}
FORCE_INLINE __m128i _mm_add_epi16(__m128i a, __m128i b) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t _b = vreinterpretq_m128i_i16(b);
return vreinterpretq_i16_m128i(__riscv_vadd_vv_i16m1(_a, _b, 8));
}
FORCE_INLINE __m128i _mm_add_epi32(__m128i a, __m128i b) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t _b = vreinterpretq_m128i_i32(b);
return __riscv_vadd_vv_i32m1(_a, _b, 4);
}
FORCE_INLINE __m128i _mm_add_epi64(__m128i a, __m128i b) {
vint64m1_t _a = vreinterpretq_m128i_i64(a);
vint64m1_t _b = vreinterpretq_m128i_i64(b);
return vreinterpretq_i64_m128i(__riscv_vadd_vv_i64m1(_a, _b, 2));
}
FORCE_INLINE __m128i _mm_add_epi8(__m128i a, __m128i b) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t _b = vreinterpretq_m128i_i8(b);
return vreinterpretq_i8_m128i(__riscv_vadd_vv_i8m1(_a, _b, 16));
}
FORCE_INLINE __m128d _mm_add_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
return vreinterpretq_f64_m128d(__riscv_vfadd_vv_f64m1(_a, _b, 2));
}
FORCE_INLINE __m128 _mm_add_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
return vreinterpretq_f32_m128(__riscv_vfadd_vv_f32m1(_a, _b, 4));
}
FORCE_INLINE __m128d _mm_add_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vfloat64m1_t add = __riscv_vfadd_vv_f64m1(_a, _b, 2);
return vreinterpretq_f64_m128d(__riscv_vslideup_vx_f64m1_tu(_a, add, 0, 1));
}
FORCE_INLINE __m64 _mm_add_si64(__m64 a, __m64 b) {
vint64m1_t _a = vreinterpretq_m64_i64(a);
vint64m1_t _b = vreinterpretq_m64_i64(b);
return vreinterpretq_i64_m64(__riscv_vadd_vv_i64m1(_a, _b, 1));
}
FORCE_INLINE __m128 _mm_add_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vfloat32m1_t add = __riscv_vfadd_vv_f32m1(_a, _b, 4);
return vreinterpretq_f32_m128(__riscv_vslideup_vx_f32m1_tu(_a, add, 0, 1));
}
FORCE_INLINE __m128i _mm_adds_epi16(__m128i a, __m128i b) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t _b = vreinterpretq_m128i_i16(b);
return vreinterpretq_i16_m128i(__riscv_vsadd_vv_i16m1(_a, _b, 8));
}
FORCE_INLINE __m128i _mm_adds_epi8(__m128i a, __m128i b) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t _b = vreinterpretq_m128i_i8(b);
return vreinterpretq_i8_m128i(__riscv_vsadd_vv_i8m1(_a, _b, 16));
}
FORCE_INLINE __m128i _mm_adds_epu16(__m128i a, __m128i b) {
vuint16m1_t _a = vreinterpretq_m128i_u16(a);
vuint16m1_t _b = vreinterpretq_m128i_u16(b);
return vreinterpretq_u16_m128i(__riscv_vsaddu_vv_u16m1(_a, _b, 8));
}
FORCE_INLINE __m128i _mm_adds_epu8(__m128i a, __m128i b) {
vuint8m1_t _a = vreinterpretq_m128i_u8(a);
vuint8m1_t _b = vreinterpretq_m128i_u8(b);
return vreinterpretq_u8_m128i(__riscv_vsaddu_vv_u8m1(_a, _b, 16));
}
FORCE_INLINE __m128d _mm_addsub_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vfloat64m1_t add = __riscv_vfadd_vv_f64m1(_a, _b, 2);
vfloat64m1_t sub = __riscv_vfsub_vv_f64m1(_a, _b, 2);
return vreinterpretq_f64_m128d(__riscv_vslideup_vx_f64m1_tu(add, sub, 0, 1));
}
FORCE_INLINE __m128 _mm_addsub_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vfloat32m1_t add = __riscv_vfadd_vv_f32m1(_a, _b, 4);
vfloat32m1_t sub = __riscv_vfsub_vv_f32m1(_a, _b, 4);
vbool32_t mask =
__riscv_vreinterpret_v_i32m1_b32(__riscv_vmv_s_x_i32m1(0xa, 4));
return vreinterpretq_f32_m128(__riscv_vmerge_vvm_f32m1(sub, add, mask, 4));
}
FORCE_INLINE __m128i _mm_alignr_epi8(__m128i a, __m128i b, int imm8) {
vuint8m2_t _a = __riscv_vlmul_ext_v_u8m1_u8m2(vreinterpretq_m128i_u8(a));
vuint8m2_t _b = __riscv_vlmul_ext_v_u8m1_u8m2(vreinterpretq_m128i_u8(b));
vuint8m2_t ab = __riscv_vslideup_vx_u8m2_tu(_b, _a, 16, 32);
return vreinterpretq_u8_m128i(__riscv_vlmul_trunc_v_u8m2_u8m1(
__riscv_vslidedown_vx_u8m2(ab, imm8, 32)));
}
FORCE_INLINE __m64 _mm_alignr_pi8(__m64 a, __m64 b, int imm8) {
vuint8m1_t _a = vreinterpretq_m64_u8(a);
vuint8m1_t _b = vreinterpretq_m64_u8(b);
vuint8m1_t ab = __riscv_vslideup_vx_u8m1_tu(_b, _a, 8, 16);
return vreinterpretq_u8_m64(__riscv_vslidedown_vx_u8m1(ab, imm8, 16));
}
FORCE_INLINE __m128d _mm_and_pd(__m128d a, __m128d b) {
vint64m1_t _a = vreinterpretq_m128d_i64(a);
vint64m1_t _b = vreinterpretq_m128d_i64(b);
return vreinterpretq_i64_m128d(__riscv_vand_vv_i64m1(_a, _b, 2));
}
FORCE_INLINE __m128 _mm_and_ps(__m128 a, __m128 b) {
vint32m1_t _a = vreinterpretq_m128_i32(a);
vint32m1_t _b = vreinterpretq_m128_i32(b);
return vreinterpretq_i32_m128(__riscv_vand_vv_i32m1(_a, _b, 4));
}
FORCE_INLINE __m128i _mm_and_si128(__m128i a, __m128i b) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t _b = vreinterpretq_m128i_i32(b);
return vreinterpretq_i32_m128i(__riscv_vand_vv_i32m1(_a, _b, 4));
}
FORCE_INLINE __m128d _mm_andnot_pd(__m128d a, __m128d b) {
vint64m1_t _a = vreinterpretq_m128d_i64(a);
vint64m1_t _b = vreinterpretq_m128d_i64(b);
return vreinterpretq_i64_m128d(
__riscv_vand_vv_i64m1(__riscv_vnot_v_i64m1(_a, 2), _b, 2));
}
FORCE_INLINE __m128 _mm_andnot_ps(__m128 a, __m128 b) {
vint32m1_t _a = vreinterpretq_m128_i32(a);
vint32m1_t _b = vreinterpretq_m128_i32(b);
return vreinterpretq_i32_m128(
__riscv_vand_vv_i32m1(__riscv_vnot_v_i32m1(_a, 4), _b, 4));
}
FORCE_INLINE __m128i _mm_andnot_si128(__m128i a, __m128i b) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t _b = vreinterpretq_m128i_i32(b);
return vreinterpretq_i32_m128i(
__riscv_vand_vv_i32m1(__riscv_vnot_v_i32m1(_a, 4), _b, 4));
}
FORCE_INLINE __m128i _mm_avg_epu16(__m128i a, __m128i b) {
vuint16m1_t _a = vreinterpretq_m128i_u16(a);
vuint16m1_t _b = vreinterpretq_m128i_u16(b);
return vreinterpretq_u16_m128i(
__riscv_vaaddu_vv_u16m1(_a, _b, __RISCV_VXRM_RNU, 8));
}
FORCE_INLINE __m128i _mm_avg_epu8(__m128i a, __m128i b) {
vuint8m1_t _a = vreinterpretq_m128i_u8(a);
vuint8m1_t _b = vreinterpretq_m128i_u8(b);
return vreinterpretq_u8_m128i(
__riscv_vaaddu_vv_u8m1(_a, _b, __RISCV_VXRM_RNU, 16));
}
FORCE_INLINE __m64 _mm_avg_pu16(__m64 a, __m64 b) {
// FIXME vreinterpretq_m64_u16 would trigger memory error
vint16m1_t __a = __riscv_vreinterpret_v_i32m1_i16m1(a);
vuint16m1_t _a = __riscv_vreinterpret_v_i16m1_u16m1(__a);
vint16m1_t __b = __riscv_vreinterpret_v_i32m1_i16m1(b);
vuint16m1_t _b = __riscv_vreinterpret_v_i16m1_u16m1(__b);
return vreinterpretq_u16_m64(
__riscv_vaaddu_vv_u16m1(_a, _b, __RISCV_VXRM_RNU, 4));
}
FORCE_INLINE __m64 _mm_avg_pu8(__m64 a, __m64 b) {
vuint8m1_t _a = vreinterpretq_m64_u8(a);
vuint8m1_t _b = vreinterpretq_m64_u8(b);
return vreinterpretq_u8_m64(
__riscv_vaaddu_vv_u8m1(_a, _b, __RISCV_VXRM_RNU, 8));
}
FORCE_INLINE __m128i _mm_blend_epi16(__m128i a, __m128i b, const int imm8) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t _b = vreinterpretq_m128i_i16(b);
vbool16_t _imm8 =
__riscv_vreinterpret_v_i8m1_b16(__riscv_vmv_s_x_i8m1(imm8, 8));
return vreinterpretq_i16_m128i(__riscv_vmerge_vvm_i16m1(_a, _b, _imm8, 8));
}
FORCE_INLINE __m128d _mm_blend_pd(__m128d a, __m128d b, const int imm8) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t _imm8 =
__riscv_vreinterpret_v_i8m1_b64(__riscv_vmv_s_x_i8m1(imm8, 2));
return vreinterpretq_f64_m128d(__riscv_vmerge_vvm_f64m1(_a, _b, _imm8, 2));
}
FORCE_INLINE __m128 _mm_blend_ps(__m128 a, __m128 b, const int imm8) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t _imm8 =
__riscv_vreinterpret_v_i8m1_b32(__riscv_vmv_s_x_i8m1(imm8, 4));
return vreinterpretq_f32_m128(__riscv_vmerge_vvm_f32m1(_a, _b, _imm8, 4));
}
FORCE_INLINE __m128i _mm_blendv_epi8(__m128i a, __m128i b, __m128i mask) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t _b = vreinterpretq_m128i_i8(b);
vint8m1_t _mask = vreinterpretq_m128i_i8(mask);
vint8m1_t mask_sra = __riscv_vsra_vx_i8m1(_mask, 7, 16);
vbool8_t mask_b8 = __riscv_vmsne_vx_i8m1_b8(mask_sra, 0, 16);
return vreinterpretq_i8_m128i(__riscv_vmerge_vvm_i8m1(_a, _b, mask_b8, 16));
}
FORCE_INLINE __m128d _mm_blendv_pd(__m128d a, __m128d b, __m128d mask) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vint64m1_t _mask = vreinterpretq_m128d_i64(mask);
vint64m1_t mask_sra = __riscv_vsra_vx_i64m1(_mask, 63, 2);
vbool64_t mask_b64 = __riscv_vmsne_vx_i64m1_b64(mask_sra, 0, 2);
return vreinterpretq_f64_m128d(__riscv_vmerge_vvm_f64m1(_a, _b, mask_b64, 2));
}
FORCE_INLINE __m128 _mm_blendv_ps(__m128 a, __m128 b, __m128 mask) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vint32m1_t _mask = vreinterpretq_m128_i32(mask);
vint32m1_t mask_sra = __riscv_vsra_vx_i32m1(_mask, 31, 4);
vbool32_t mask_b32 = __riscv_vmsne_vx_i32m1_b32(mask_sra, 0, 4);
return vreinterpretq_f32_m128(__riscv_vmerge_vvm_f32m1(_a, _b, mask_b32, 4));
}
FORCE_INLINE __m128i _mm_bslli_si128(__m128i a, int imm8) {
vuint8m1_t _a = vreinterpretq_m128i_u8(a);
vuint8m1_t zeros = __riscv_vmv_v_x_u8m1(0, 16);
return vreinterpretq_u8_m128i(
__riscv_vslideup_vx_u8m1_tu(zeros, _a, imm8 & 0xff, 16));
}
FORCE_INLINE __m128i _mm_bsrli_si128(__m128i a, int imm8) {
vuint8m1_t _a = vreinterpretq_m128i_u8(a);
return vreinterpretq_u8_m128i(
__riscv_vslidedown_vx_u8m1(_a, imm8 & 0xff, 16));
}
FORCE_INLINE __m128 _mm_castpd_ps(__m128d a) {
return __riscv_vreinterpret_v_u32m1_f32m1(__riscv_vreinterpret_v_u64m1_u32m1(
__riscv_vreinterpret_v_f64m1_u64m1(a)));
}
FORCE_INLINE __m128i _mm_castpd_si128(__m128d a) {
return __riscv_vreinterpret_v_i64m1_i32m1(
__riscv_vreinterpret_v_f64m1_i64m1(a));
}
FORCE_INLINE __m128d _mm_castps_pd(__m128 a) {
return __riscv_vreinterpret_v_i64m1_f64m1(__riscv_vreinterpret_v_i32m1_i64m1(
__riscv_vreinterpret_v_f32m1_i32m1(a)));
}
FORCE_INLINE __m128i _mm_castps_si128(__m128 a) {
return __riscv_vreinterpret_v_f32m1_i32m1(a);
}
FORCE_INLINE __m128d _mm_castsi128_pd(__m128i a) {
return __riscv_vreinterpret_v_i64m1_f64m1(
__riscv_vreinterpret_v_i32m1_i64m1(a));
}
FORCE_INLINE __m128 _mm_castsi128_ps(__m128i a) {
return __riscv_vreinterpret_v_i32m1_f32m1(a);
}
FORCE_INLINE __m128d _mm_ceil_pd(__m128d a) {
// FIXME riscv round doesn't work
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
double arr[2];
const int len = 2;
__riscv_vse64_v_f64m1(arr, _a, len);
for (int i = 0; i < len; i++) {
arr[i] = ceil(arr[i]);
}
return vreinterpretq_f64_m128d(__riscv_vle64_v_f64m1(arr, len));
}
FORCE_INLINE __m128 _mm_ceil_ps(__m128 a) {
// FIXME riscv round doesn't work
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
float arr[4];
const int len = 4;
__riscv_vse32_v_f32m1(arr, _a, len);
for (int i = 0; i < len; i++) {
arr[i] = ceil(arr[i]);
}
return vreinterpretq_f32_m128(__riscv_vle32_v_f32m1(arr, len));
}
FORCE_INLINE __m128d _mm_ceil_sd(__m128d a, __m128d b) {
// FIXME riscv round doesn't work
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
double arr[2];
const int len = 2;
__riscv_vse64_v_f64m1(arr, _b, len);
arr[0] = ceil(arr[0]);
vfloat64m1_t _arr = __riscv_vle64_v_f64m1(arr, 1);
return vreinterpretq_f64_m128d(__riscv_vslideup_vx_f64m1_tu(_a, _arr, 0, 1));
}
FORCE_INLINE __m128 _mm_ceil_ss(__m128 a, __m128 b) {
// FIXME riscv round doesn't work
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
float arr[4];
const int len = 4;
__riscv_vse32_v_f32m1(arr, _b, len);
arr[0] = ceil(arr[0]);
vfloat32m1_t _arr = __riscv_vle32_v_f32m1(arr, 1);
return vreinterpretq_f32_m128(__riscv_vslideup_vx_f32m1_tu(_a, _arr, 0, 1));
}
// FORCE_INLINE void _mm_clflush (void const* p) {}
FORCE_INLINE __m128i _mm_cmpeq_epi16(__m128i a, __m128i b) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t _b = vreinterpretq_m128i_i16(b);
vbool16_t cmp_res = __riscv_vmseq_vv_i16m1_b16(_a, _b, 8);
return vreinterpretq_i16_m128i(
__riscv_vmerge_vxm_i16m1(__riscv_vmv_v_x_i16m1(0x0, 8), -1, cmp_res, 8));
}
FORCE_INLINE __m128i _mm_cmpeq_epi32(__m128i a, __m128i b) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t _b = vreinterpretq_m128i_i32(b);
vbool32_t cmp_res = __riscv_vmseq_vv_i32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128i(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128i _mm_cmpeq_epi64(__m128i a, __m128i b) {
vint64m1_t _a = vreinterpretq_m128i_i64(a);
vint64m1_t _b = vreinterpretq_m128i_i64(b);
vbool64_t cmp_res = __riscv_vmseq_vv_i64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128i(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128i _mm_cmpeq_epi8(__m128i a, __m128i b) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t _b = vreinterpretq_m128i_i8(b);
vbool8_t cmp_res = __riscv_vmseq_vv_i8m1_b8(_a, _b, 16);
return vreinterpretq_i8_m128i(
__riscv_vmerge_vxm_i8m1(__riscv_vmv_v_x_i8m1(0x0, 16), -1, cmp_res, 16));
}
FORCE_INLINE __m128d _mm_cmpeq_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfeq_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmpeq_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfeq_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmpeq_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfeq_vv_f64m1_b64(_a, _b, 2);
vint64m1_t cmp_res_i64 =
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1_tu(
__riscv_vreinterpret_v_f64m1_i64m1(_a), cmp_res_i64, 0, 1));
}
FORCE_INLINE __m128 _mm_cmpeq_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfeq_vv_f32m1_b32(_a, _b, 4);
vint32m1_t cmp_res_i32 =
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1_tu(
__riscv_vreinterpret_v_f32m1_i32m1(_a), cmp_res_i32, 0, 1));
}
// FORCE_INLINE int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const
// int imm8) {}
// FORCE_INLINE int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const
// int imm8) {}
// FORCE_INLINE int _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const
// int imm8) {}
// FORCE_INLINE __m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb,
// const int imm8) {}
// FORCE_INLINE int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const
// int imm8) {}
// FORCE_INLINE int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const
// int imm8) {}
// FORCE_INLINE int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const
// int imm8) {}
FORCE_INLINE __m128d _mm_cmpge_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfge_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmpge_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfge_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmpge_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfge_vv_f64m1_b64(_a, _b, 2);
vint64m1_t cmp_res_i64 =
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1_tu(
__riscv_vreinterpret_v_f64m1_i64m1(_a), cmp_res_i64, 0, 1));
}
FORCE_INLINE __m128 _mm_cmpge_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfge_vv_f32m1_b32(_a, _b, 4);
vint32m1_t cmp_res_i32 =
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1_tu(
__riscv_vreinterpret_v_f32m1_i32m1(_a), cmp_res_i32, 0, 1));
}
FORCE_INLINE __m128i _mm_cmpgt_epi16(__m128i a, __m128i b) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t _b = vreinterpretq_m128i_i16(b);
vbool16_t cmp_res = __riscv_vmsgt_vv_i16m1_b16(_a, _b, 8);
return vreinterpretq_i16_m128i(
__riscv_vmerge_vxm_i16m1(__riscv_vmv_v_x_i16m1(0x0, 8), -1, cmp_res, 8));
}
FORCE_INLINE __m128i _mm_cmpgt_epi32(__m128i a, __m128i b) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t _b = vreinterpretq_m128i_i32(b);
vbool32_t cmp_res = __riscv_vmsgt_vv_i32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128i(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128i _mm_cmpgt_epi64(__m128i a, __m128i b) {
vint64m1_t _a = vreinterpretq_m128i_i64(a);
vint64m1_t _b = vreinterpretq_m128i_i64(b);
vbool64_t cmp_res = __riscv_vmsgt_vv_i64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128i(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128i _mm_cmpgt_epi8(__m128i a, __m128i b) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t _b = vreinterpretq_m128i_i8(b);
vbool8_t cmp_res = __riscv_vmsgt_vv_i8m1_b8(_a, _b, 16);
return vreinterpretq_i8_m128i(
__riscv_vmerge_vxm_i8m1(__riscv_vmv_v_x_i8m1(0x0, 16), -1, cmp_res, 16));
}
FORCE_INLINE __m128d _mm_cmpgt_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfgt_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmpgt_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfgt_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmpgt_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfgt_vv_f64m1_b64(_a, _b, 2);
vint64m1_t cmp_res_i64 =
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1_tu(
__riscv_vreinterpret_v_f64m1_i64m1(_a), cmp_res_i64, 0, 1));
}
FORCE_INLINE __m128 _mm_cmpgt_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfgt_vv_f32m1_b32(_a, _b, 4);
vint32m1_t cmp_res_i32 =
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1_tu(
__riscv_vreinterpret_v_f32m1_i32m1(_a), cmp_res_i32, 0, 1));
}
// FORCE_INLINE int _mm_cmpistra (__m128i a, __m128i b, const int imm8) {}
// FORCE_INLINE int _mm_cmpistrc (__m128i a, __m128i b, const int imm8) {}
// FORCE_INLINE int _mm_cmpistri (__m128i a, __m128i b, const int imm8) {}
// FORCE_INLINE __m128i _mm_cmpistrm (__m128i a, __m128i b, const int imm8) {}
// FORCE_INLINE int _mm_cmpistro (__m128i a, __m128i b, const int imm8) {}
// FORCE_INLINE int _mm_cmpistrs (__m128i a, __m128i b, const int imm8) {}
// FORCE_INLINE int _mm_cmpistrz (__m128i a, __m128i b, const int imm8) {}
FORCE_INLINE __m128d _mm_cmple_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfle_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmple_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfle_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmple_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfle_vv_f64m1_b64(_a, _b, 2);
vint64m1_t cmp_res_i64 =
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1_tu(
__riscv_vreinterpret_v_f64m1_i64m1(_a), cmp_res_i64, 0, 1));
}
FORCE_INLINE __m128 _mm_cmple_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfle_vv_f32m1_b32(_a, _b, 4);
vint32m1_t cmp_res_i32 =
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1_tu(
__riscv_vreinterpret_v_f32m1_i32m1(_a), cmp_res_i32, 0, 1));
}
FORCE_INLINE __m128i _mm_cmplt_epi16(__m128i a, __m128i b) {
vint16m1_t _a = vreinterpretq_m128i_i16(a);
vint16m1_t _b = vreinterpretq_m128i_i16(b);
vbool16_t cmp_res = __riscv_vmslt_vv_i16m1_b16(_a, _b, 8);
return vreinterpretq_i16_m128i(
__riscv_vmerge_vxm_i16m1(__riscv_vmv_v_x_i16m1(0x0, 8), -1, cmp_res, 8));
}
FORCE_INLINE __m128i _mm_cmplt_epi32(__m128i a, __m128i b) {
vint32m1_t _a = vreinterpretq_m128i_i32(a);
vint32m1_t _b = vreinterpretq_m128i_i32(b);
vbool32_t cmp_res = __riscv_vmslt_vv_i32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128i(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128i _mm_cmplt_epi8(__m128i a, __m128i b) {
vint8m1_t _a = vreinterpretq_m128i_i8(a);
vint8m1_t _b = vreinterpretq_m128i_i8(b);
vbool8_t cmp_res = __riscv_vmslt_vv_i8m1_b8(_a, _b, 16);
return vreinterpretq_i8_m128i(
__riscv_vmerge_vxm_i8m1(__riscv_vmv_v_x_i8m1(0x0, 16), -1, cmp_res, 16));
}
FORCE_INLINE __m128d _mm_cmplt_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmflt_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmplt_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmflt_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmplt_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmflt_vv_f64m1_b64(_a, _b, 2);
vint64m1_t cmp_res_i64 =
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1_tu(
__riscv_vreinterpret_v_f64m1_i64m1(_a), cmp_res_i64, 0, 1));
}
FORCE_INLINE __m128 _mm_cmplt_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmflt_vv_f32m1_b32(_a, _b, 4);
vint32m1_t cmp_res_i32 =
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1_tu(
__riscv_vreinterpret_v_f32m1_i32m1(_a), cmp_res_i32, 0, 1));
}
FORCE_INLINE __m128d _mm_cmpneq_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfne_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmpneq_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfne_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmpneq_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfne_vv_f64m1_b64(_a, _b, 2);
vint64m1_t cmp_res_i64 =
__riscv_vmerge_vxm_i64m1(__riscv_vmv_v_x_i64m1(0x0, 2), -1, cmp_res, 2);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1_tu(
__riscv_vreinterpret_v_f64m1_i64m1(_a), cmp_res_i64, 0, 1));
}
FORCE_INLINE __m128 _mm_cmpneq_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfne_vv_f32m1_b32(_a, _b, 4);
vint32m1_t cmp_res_i32 =
__riscv_vmerge_vxm_i32m1(__riscv_vmv_v_x_i32m1(0x0, 4), -1, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1_tu(
__riscv_vreinterpret_v_f32m1_i32m1(_a), cmp_res_i32, 0, 1));
}
FORCE_INLINE __m128d _mm_cmpnge_pd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfge_vv_f64m1_b64(_a, _b, 2);
return vreinterpretq_i64_m128d(__riscv_vmerge_vxm_i64m1(
__riscv_vmv_v_x_i64m1(UINT64_MAX, 2), 0x0, cmp_res, 2));
}
FORCE_INLINE __m128 _mm_cmpnge_ps(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfge_vv_f32m1_b32(_a, _b, 4);
return vreinterpretq_i32_m128(__riscv_vmerge_vxm_i32m1(
__riscv_vmv_v_x_i32m1(UINT32_MAX, 4), 0x0, cmp_res, 4));
}
FORCE_INLINE __m128d _mm_cmpnge_sd(__m128d a, __m128d b) {
vfloat64m1_t _a = vreinterpretq_m128d_f64(a);
vfloat64m1_t _b = vreinterpretq_m128d_f64(b);
vbool64_t cmp_res = __riscv_vmfge_vv_f64m1_b64(_a, _b, 2);
vint64m1_t merge = __riscv_vmerge_vxm_i64m1(
__riscv_vmv_v_x_i64m1(UINT64_MAX, 2), 0x0, cmp_res, 1);
return vreinterpretq_i64_m128d(__riscv_vslideup_vx_i64m1(
__riscv_vreinterpret_v_f64m1_i64m1(_a), merge, 0, 1));
}
FORCE_INLINE __m128 _mm_cmpnge_ss(__m128 a, __m128 b) {
vfloat32m1_t _a = vreinterpretq_m128_f32(a);
vfloat32m1_t _b = vreinterpretq_m128_f32(b);
vbool32_t cmp_res = __riscv_vmfge_vv_f32m1_b32(_a, _b, 4);
vint32m1_t merge = __riscv_vmerge_vxm_i32m1(
__riscv_vmv_v_x_i32m1(UINT32_MAX, 4), 0x0, cmp_res, 4);
return vreinterpretq_i32_m128(__riscv_vslideup_vx_i32m1(
__riscv_vreinterpret_v_f32m1_i32m1(_a), merge, 0, 1));
}
FORCE_INLINE __m128d _mm_cmpngt_pd(__m128d a, __m128d b) {