18 #include "AlarmClock.h"
20 #if defined ARDUINO_ARCH_AVR && !defined Adafruit_SPIDevice_h
21 #include <util/delay.h>
22 typedef uint8_t BitOrder;
25 #ifndef Adafruit_SPIDevice_h
26 #define SPI_BITORDER_MSBFIRST MSBFIRST
27 #define SPI_BITORDER_LSBFIRST LSBFIRST
32 #ifndef USE_OTA_BOOTLOADER
34 #undef USE_OTA_BOOTLOADER_FREQUENCY
40 #define CC1101_IOCFG2 0x00 // (0x29) GDO2 Output Pin Configuration
41 #define CC1101_IOCFG1 0x01 // (0x2E) GDO1 Output Pin Configuration
42 #define CC1101_IOCFG0 0x02 // (0x3F) GDO0 Output Pin Configuration
43 #define CC1101_FIFOTHR 0x03 // (0x07) RX FIFO and TX FIFO Thresholds
44 #define CC1101_SYNC1 0x04 // (0xD3) Sync Word, High Byte
45 #define CC1101_SYNC0 0x05 // (0x91) Sync Word, Low Byte
46 #define CC1101_PKTLEN 0x06 // (0xFF) Packet Length
47 #define CC1101_PKTCTRL1 0x07 // (0x04) Packet Automation Control
48 #define CC1101_PKTCTRL0 0x08 // (0x45) Packet Automation Control
49 #define CC1101_ADDR 0x09 // (0x00) Device Address
50 #define CC1101_CHANNR 0x0A // (0x00) Channel Number
51 #define CC1101_FSCTRL1 0x0B // (0x0F) Frequency Synthesizer Control
52 #define CC1101_FSCTRL0 0x0C // (0x00) Frequency Synthesizer Control
53 #define CC1101_FREQ2 0x0D // (0x1E) Frequency Control Word, High Byte
54 #define CC1101_FREQ1 0x0E // (0xC4) Frequency Control Word, Middle Byte
55 #define CC1101_FREQ0 0x0F // (0xEC) Frequency Control Word, Low Byte
56 #define CC1101_MDMCFG4 0x10 // (0x8C) Modem Configuration
57 #define CC1101_MDMCFG3 0x11 // (0x22) Modem Configuration
58 #define CC1101_MDMCFG2 0x12 // (0x02) Modem Configuration
59 #define CC1101_MDMCFG1 0x13 // (0x22) Modem Configuration
60 #define CC1101_MDMCFG0 0x14 // (0xF8) Modem Configuration
61 #define CC1101_DEVIATN 0x15 // (0x47) Modem Deviation Setting
62 #define CC1101_MCSM2 0x16 // (0x07) Main Radio Control State Machine Configuration
63 #define CC1101_MCSM1 0x17 // (0x30) Main Radio Control State Machine Configuration
64 #define CC1101_MCSM0 0x18 // (0x04) Main Radio Control State Machine Configuration
65 #define CC1101_FOCCFG 0x19 // (0x36) Frequency Offset Compensation Configuration
66 #define CC1101_BSCFG 0x1A // (0x6C) Bit Synchronization Configuration
67 #define CC1101_AGCCTRL2 0x1B // (0x03) AGC Control
68 #define CC1101_AGCCTRL1 0x1C // (0x40) AGC Control
69 #define CC1101_AGCCTRL0 0x1D // (0x91) AGC Control
70 #define CC1101_WOREVT1 0x1E // (0x87) High Byte Event0 Timeout
71 #define CC1101_WOREVT0 0x1F // (0x6B) Low Byte Event0 Timeout
72 #define CC1101_WORCTRL 0x20 // (0xF8) Wake On Radio Control
73 #define CC1101_FREND1 0x21 // (0x56) Front End RX Configuration
74 #define CC1101_FREND0 0x22 // (0x10) Front End RX Configuration
75 #define CC1101_FSCAL3 0x23 // (0xA9) Frequency Synthesizer Calibration
76 #define CC1101_FSCAL2 0x24 // (0x0A) Frequency Synthesizer Calibration
77 #define CC1101_FSCAL1 0x25 // (0x20) Frequency Synthesizer Calibration
78 #define CC1101_FSCAL0 0x26 // (0x0D) Frequency Synthesizer Calibration
79 #define CC1101_RCCTRL1 0x27 // (0x41) RC Oscillator Configuration
80 #define CC1101_RCCTRL2 0x28 // (0x00) RC Oscillator Configuration
81 #define CC1101_FSTEST 0x29 // (0x59) Frequency Synthesizer Calibration Control
82 #define CC1101_PTEST 0x2A // (0x7F) Production Test
83 #define CC1101_AGCTEST 0x2B // (0x3F) AGC Test
84 #define CC1101_TEST2 0x2C // (0x88) Various Test Settings
85 #define CC1101_TEST1 0x2D // (0x31) Various Test Settings
86 #define CC1101_TEST0 0x2E // (0x0B) Various Test Settings
88 #define CC1101_PARTNUM 0x30 // (0x00) Readonly: Chip ID
89 #define CC1101_VERSION 0x31 // (0x04) Readonly: Chip ID
90 #define CC1101_FREQEST 0x32 // (0x00) Readonly: Frequency Offset Estimate from Demodulator
91 #define CC1101_LQI 0x33 // (0x00) Readonly: Demodulator Estimate for Link Quality
92 #define CC1101_RSSI 0x34 // (0x00) Readonly: Received Signal Strength Indication
93 #define CC1101_MARCSTATE 0x35 // (0x00) Readonly: Main Radio Control State Machine State
94 #define CC1101_WORTIME1 0x36 // (0x00) Readonly: High Byte of WOR Time
95 #define CC1101_WORTIME0 0x37 // (0x00) Readonly: Low Byte of WOR Time
96 #define CC1101_PKTSTATUS 0x38 // (0x00) Readonly: Current GDOx Status and Packet Status
97 #define CC1101_VCO_VC_DAC 0x39 // (0x00) Readonly: Current Setting from PLL Calibration Module
98 #define CC1101_TXBYTES 0x3A // (0x00) Readonly: Underflow and Number of Bytes
99 #define CC1101_RXBYTES 0x3B // (0x00) Readonly: Overflow and Number of Bytes
100 #define CC1101_RCCTRL1_STATUS 0x3C // (0x00) Readonly: Last RC Oscillator Calibration Result
101 #define CC1101_RCCTRL0_STATUS 0x3D // (0x00) Readonly: Last RC Oscillator Calibration Result
103 #define CC1101_PATABLE 0x3E // PATABLE address
104 #define CC1101_TXFIFO 0x3F // TX FIFO address
105 #define CC1101_RXFIFO 0x3F // RX FIFO address
107 #define CC1101_PA_TABLE0 0x40 // (0x00) PA table, entry 0
108 #define CC1101_PA_TABLE1 0x41 // (0x00) PA table, entry 1
109 #define CC1101_PA_TABLE2 0x42 // (0x00) PA table, entry 2
110 #define CC1101_PA_TABLE3 0x43 // (0x00) PA table, entry 3
111 #define CC1101_PA_TABLE4 0x44 // (0x00) PA table, entry 4
112 #define CC1101_PA_TABLE5 0x45 // (0x00) PA table, entry 5
113 #define CC1101_PA_TABLE6 0x46 // (0x00) PA table, entry 6
114 #define CC1101_PA_TABLE7 0x47 // (0x00) PA table, entry 7
117 #define READ_SINGLE 0x80 // type of transfers
118 #define READ_BURST 0xC0
119 #define WRITE_BURST 0x40
121 #define CC1101_CONFIG 0x80 // type of register
122 #define CC1101_STATUS 0xC0
124 #define CC1101_SRES 0x30 // reset CC1101 chip
125 #define CC1101_SFSTXON 0x31 // enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). if in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
126 #define CC1101_SXOFF 0x32 // turn off crystal oscillator
127 #define CC1101_SCAL 0x33 // calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
128 #define CC1101_SRX 0x34 // enable RX. perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1
129 #define CC1101_STX 0x35 // in IDLE state: enable TX. perform calibration first if MCSM0.FS_AUTOCAL=1. if in RX state and CCA is enabled: only go to TX if channel is clear
130 #define CC1101_SIDLE 0x36 // exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable
131 #define CC1101_SWOR 0x38 // start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if WORCTRL.RC_PD=0
132 #define CC1101_SPWD 0x39 // enter power down mode when CSn goes high
133 #define CC1101_SFRX 0x3A // flush the RX FIFO buffer. only issue SFRX in IDLE or RXFIFO_OVERFLOW states
134 #define CC1101_SFTX 0x3B // flush the TX FIFO buffer. only issue SFTX in IDLE or TXFIFO_UNDERFLOW states
135 #define CC1101_SWORRST 0x3C // reset real time clock to Event1 value
136 #define CC1101_SNOP 0x3D // no operation. may be used to get access to the chip status byte
138 #define MARCSTATE_SLEEP 0x00
139 #define MARCSTATE_IDLE 0x01
140 #define MARCSTATE_XOFF 0x02
141 #define MARCSTATE_VCOON_MC 0x03
142 #define MARCSTATE_REGON_MC 0x04
143 #define MARCSTATE_MANCAL 0x05
144 #define MARCSTATE_VCOON 0x06
145 #define MARCSTATE_REGON 0x07
146 #define MARCSTATE_STARTCAL 0x08
147 #define MARCSTATE_BWBOOST 0x09
148 #define MARCSTATE_FS_LOCK 0x0A
149 #define MARCSTATE_IFADCON 0x0B
150 #define MARCSTATE_ENDCAL 0x0C
151 #define MARCSTATE_RX 0x0D
152 #define MARCSTATE_RX_END 0x0E
153 #define MARCSTATE_RX_RST 0x0F
154 #define MARCSTATE_TXRX_SWITCH 0x10
155 #define MARCSTATE_RXFIFO_OFLOW 0x11
156 #define MARCSTATE_FSTXON 0x12
157 #define MARCSTATE_TX 0x13
158 #define MARCSTATE_TX_END 0x14
159 #define MARCSTATE_RXTX_SWITCH 0x15
160 #define MARCSTATE_TXFIFO_UFLOW 0x16
162 #define PA_LowPower 0x03 // PATABLE values
163 #define PA_Normal 0x50 // PATABLE values
164 #define PA_MaxPower 0xC0
168 #ifdef ARDUINO_ARCH_AVR
170 template <u
int8_t CS,u
int8_t MOSI,u
int8_t MISO,u
int8_t SCLK,
class PINTYPE=ArduinoPins>
174 uint8_t send (uint8_t data) {
176 while (!(SPSR & _BV(SPIF)));
181 while(PINTYPE::getState(MISO));
185 PINTYPE::setOutput(CS);
186 PINTYPE::setOutput(MOSI);
187 PINTYPE::setInput(MISO);
188 PINTYPE::setOutput(SCLK);
190 SPCR = _BV(SPE) | _BV(MSTR);
191 PINTYPE::setHigh(CS);
193 PINTYPE::setHigh(SCLK);
194 PINTYPE::setLow(MOSI);
202 PINTYPE::setHigh(CS);
211 uint8_t strobe(uint8_t cmd) {
214 uint8_t ret = send(cmd);
219 void readBurst(uint8_t * buf, uint8_t regAddr, uint8_t len) {
222 send(regAddr | READ_BURST);
223 for(uint8_t i=0 ; i<len ; i++) {
230 void writeBurst(uint8_t regAddr, uint8_t* buf, uint8_t len) {
233 send(regAddr | WRITE_BURST);
234 for(uint8_t i=0 ; i<len ; i++)
239 uint8_t readReg(uint8_t regAddr, uint8_t regType) {
242 send(regAddr | regType);
243 uint8_t val = send(0x00);
248 void writeReg(uint8_t regAddr, uint8_t val) {
263 template <u
int8_t CS,u
int32_t CLOCK=2000000, BitOrder BITORDER=SPI_BITORDER_MSBFIRST, u
int8_t MODE=SPI_MODE0>
274 digitalWrite(CS,LOW);
278 digitalWrite(CS,HIGH);
282 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
286 SPI.endTransaction();
290 #ifdef ARDUINO_ARCH_STM32F1
291 while(digitalRead(SPI.misoPin()));
292 #elif defined (PIN_SPI_MISO)
293 while(digitalRead(PIN_SPI_MISO));
299 uint8_t send (uint8_t data) {
300 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
301 uint8_t ret = SPI.transfer(data);
302 SPI.endTransaction();
306 uint8_t strobe(uint8_t cmd) {
307 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
309 uint8_t ret = SPI.transfer(cmd);
311 SPI.endTransaction();
315 void readBurst(uint8_t * buf, uint8_t regAddr, uint8_t len) {
316 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
318 SPI.transfer(regAddr | READ_BURST);
319 for(uint8_t i=0 ; i<len ; i++) {
320 buf[i] = SPI.transfer(0x00);
324 SPI.endTransaction();
327 void writeBurst(uint8_t regAddr, uint8_t* buf, uint8_t len) {
328 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
330 SPI.transfer(regAddr | WRITE_BURST);
331 for(uint8_t i=0 ; i<len ; i++)
332 SPI.transfer(buf[i]);
334 SPI.endTransaction();
337 uint8_t readReg(uint8_t regAddr, uint8_t regType) {
338 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
340 SPI.transfer(regAddr | regType);
341 uint8_t val = SPI.transfer(0x00);
343 SPI.endTransaction();
347 void writeReg(uint8_t regAddr, uint8_t val) {
348 SPI.beginTransaction(SPISettings(CLOCK,BITORDER,MODE));
350 SPI.transfer(regAddr);
353 SPI.endTransaction();
360 extern void* __gb_radio;
366 bool detectBurst () {
return false; }
370 uint8_t getGDO0 () {
return 0; }
371 bool init () {
return true; }
372 bool isIdle () {
return true; }
373 uint8_t read (__attribute__ ((unused))
Message& msg) {
return 0; }
374 uint8_t reset () {
return 0; }
375 uint8_t rssi () {
return 0; }
377 void setSendTimeout (__attribute__ ((unused)) uint16_t timeout=0) {}
378 void waitTimeout (__attribute__ ((unused)) uint16_t timeout) {}
380 void initReg(__attribute__ ((unused)) uint8_t val0, __attribute__ ((unused)) uint8_t val1) {}
381 bool write (__attribute__ ((unused))
const Message& msg, __attribute__ ((unused)) uint8_t burst) {
return false; }
384 template <
class SPIType>
389 #ifdef USE_OTA_BOOTLOADER_FREQUENCY
395 #ifdef USE_OTA_BOOTLOADER_FREQUENCY
403 while(cnt-- && (spi.strobe(CC1101_SIDLE) & 0x70) != 0) {
406 spi.strobe(CC1101_SFRX);
410 spi.writeReg(CC1101_PKTCTRL1, 0x4C);
411 spi.writeReg(CC1101_MCSM2, 0x1c);
413 spi.strobe(CC1101_SWORRST);
414 spi.strobe(CC1101_SWOR);
416 spi.strobe(CC1101_SPWD);
420 void wakeup (
bool flush) {
427 spi.writeReg(CC1101_PKTCTRL1, 0x0C);
428 spi.writeReg(CC1101_MCSM2, 0x07);
430 spi.strobe(CC1101_SRX);
453 uint8_t ret = spi.send(CC1101_SRES);
466 #ifdef USE_OTA_BOOTLOADER_FREQUENCY
468 f1 = spi.readReg(CC1101_FREQ1, CC1101_CONFIG);
469 f0 = spi.readReg(CC1101_FREQ0, CC1101_CONFIG);
470 DPRINT(F(
"Boot Loader Freq: 0x21"));DHEX(f1);DHEXLN(f0);
474 #ifdef SIMPLE_CC1101_INIT
475 static const uint8_t initVal[] PROGMEM = {
531 for (uint8_t i=0; i<
sizeof(initVal); ++i) {
532 bool initres = initReg(i, pgm_read_byte(&initVal[i]));
534 if (initres ==
false) initOK =
false;
538 static const uint8_t initVal[] PROGMEM = {
549 CC1101_FIFOTHR, 0x0D,
553 CC1101_PKTCTRL1, 0x0C,
557 CC1101_FSCTRL1, 0x06,
560 #ifndef USE_OTA_BOOTLOADER_FREQUENCY
567 CC1101_MDMCFG4, 0xC8,
568 CC1101_MDMCFG3, 0x93,
569 CC1101_MDMCFG2, 0x03,
572 CC1101_DEVIATN, 0x34,
582 CC1101_AGCCTRL2, 0x43,
585 CC1101_WOREVT1, 0x2f,
586 CC1101_WOREVT0, 0x65,
587 CC1101_WORCTRL, 0x78,
602 CC1101_PATABLE, 0x03,
606 for (uint8_t i=0; i<
sizeof(initVal); i+=2) {
607 bool initres = initReg(pgm_read_byte(&initVal[i]), pgm_read_byte(&initVal[i+1]));
609 if (initres ==
false) initOK =
false;
614 #ifdef USE_OTA_BOOTLOADER_FREQUENCY
616 initReg(CC1101_FREQ2, 0x21);
617 initReg(CC1101_FREQ1, f1);
618 initReg(CC1101_FREQ0, f0);
622 DPRINT(F(
"CC Version: ")); DHEXLN(spi.readReg(CC1101_VERSION, CC1101_STATUS));
624 spi.strobe(CC1101_SCAL);
628 initReg(CC1101_PATABLE, PA_MaxPower);
630 DPRINTLN(F(
" - ready"));
634 #ifdef SIMPLE_CC1101_INIT
635 bool initReg (uint8_t regAddr, uint8_t val) {
636 spi.writeReg(regAddr, val);
640 bool initReg (uint8_t regAddr, uint8_t val, uint8_t retries=3) {
641 spi.writeReg(regAddr, val);
642 uint8_t val_read = spi.readReg(regAddr, CC1101_CONFIG);
643 bool initResult =
true;
644 if( val_read != val ) {
646 initResult = initReg(regAddr, val, --retries);
650 DPRINT(F(
"Error at ")); DHEX(regAddr);
651 DPRINT(F(
" expected: ")); DHEX(val); DPRINT(F(
" read: ")); DHEXLN(val_read);
659 uint8_t rssi ()
const {
664 spi.strobe(CC1101_SIDLE);
665 spi.strobe(CC1101_SNOP);
666 spi.strobe(CC1101_SFRX);
669 bool detectBurst () {
670 uint8_t state = spi.readReg(CC1101_PKTSTATUS, CC1101_STATUS);
672 return (state & 0x01<<6) == (0x01<<6);
676 calculateRSSI(spi.readReg(CC1101_RSSI, CC1101_STATUS));
681 void calculateRSSI(uint8_t rsshex) {
682 rss = -1 * ((((int16_t)rsshex-((int16_t)rsshex >= 128 ? 256 : 0))/2)-74);
685 uint8_t sndData(uint8_t *buf, uint8_t size, uint8_t burst) {
688 spi.strobe(CC1101_SIDLE);
689 spi.strobe(CC1101_SFTX );
693 spi.strobe(CC1101_STX);
697 spi.strobe(CC1101_SIDLE );
698 spi.strobe(CC1101_SFTX );
699 spi.strobe(CC1101_SNOP );
701 do { spi.strobe(CC1101_SRX);
702 }
while (spi.readReg(CC1101_MARCSTATE, CC1101_STATUS) != MARCSTATE_RX);
706 while(spi.readReg(CC1101_MARCSTATE, CC1101_STATUS) != MARCSTATE_TX);
713 spi.writeReg(CC1101_TXFIFO, size);
714 spi.writeBurst(CC1101_TXFIFO, buf, size);
716 for(uint8_t i = 0; i < 200; i++) {
717 if( spi.readReg(CC1101_MARCSTATE, CC1101_STATUS) == MARCSTATE_RX)
724 uint8_t rcvData(uint8_t *buf, uint8_t size) {
727 uint8_t packetBytes = 0;
729 uint8_t fifoBytes = spi.readReg(CC1101_RXBYTES, CC1101_STATUS);
732 if( fifoBytes > 0 && (fifoBytes & 0x80) != 0x80 ) {
733 packetBytes = spi.readReg(CC1101_RXFIFO, CC1101_CONFIG);
736 if (packetBytes <= size) {
737 spi.readBurst(buf, CC1101_RXFIFO, packetBytes);
738 calculateRSSI(spi.readReg(CC1101_RXFIFO, CC1101_CONFIG));
739 uint8_t val = spi.readReg(CC1101_RXFIFO, CC1101_CONFIG);
741 if( (val & 0x80) == 0x80 ) {
743 rxBytes = packetBytes;
746 DPRINTLN(F(
"CRC Failed"));
750 DPRINT(F(
"Packet too big: "));DDECLN(packetBytes);
755 spi.strobe(CC1101_SFRX);
758 spi.strobe(CC1101_SRX);
766 template <
class SPIType ,u
int8_t GDO0,
int SENDDELAY=100,
class HWRADIO=CC1101<SPIType> >
773 class MinSendTimeout :
public Alarm {
776 MinSendTimeout () :
Alarm(0), wait(
false) { async(
true); }
777 virtual ~MinSendTimeout () {}
778 void waitTimeout () {
780 while( wait==
true ) {
786 set(millis2ticks(SENDDELAY));
794 void setTimeout (uint16_t millis=SENDDELAY) {
796 sysclock.cancel(*
this);
798 set(millis2ticks(millis));
805 virtual void trigger(__attribute__ ((unused))
AlarmClock& clock) {
813 void setSendTimeout(uint16_t millis=SENDDELAY) {
814 timeout.setTimeout(millis);
817 void waitTimeout (uint16_t millis) {
818 timeout.setTimeout(millis);
819 timeout.waitTimeout();
823 volatile uint8_t intread;
824 volatile uint8_t sending;
829 Radio () : intread(0), sending(0), idle(
false) {}
836 DPRINT(F(
"CC init"));
841 bool initOK = HWRADIO::init();
842 if (initOK) HWRADIO::wakeup(
true);
848 if( idle ==
false ) {
854 void wakeup (
bool flush=
true) {
856 HWRADIO::wakeup(flush);
872 bool detectBurst () {
873 if( isIdle() ==
true ) {
878 return HWRADIO::detectBurst();
882 return digitalRead(GDO0);
886 #ifdef EnableInterrupt_h
887 if( digitalPinToInterrupt(GDO0) == NOT_AN_INTERRUPT )
888 enableInterrupt(GDO0,isr,FALLING);
891 attachInterrupt(digitalPinToInterrupt(GDO0),isr,FALLING);
894 #ifdef EnableInterrupt_h
895 if( digitalPinToInterrupt(GDO0) == NOT_AN_INTERRUPT )
896 disableInterrupt(GDO0);
899 detachInterrupt(digitalPinToInterrupt(GDO0));
908 uint8_t len = this->rcvData(buffer.buffer(),buffer.buffersize());
914 memcpy(msg.buffer(),buffer.buffer(),len);
925 uint8_t read (
Message& msg, uint32_t timeout) {
935 while( num == 0 && time < timeout );
940 bool write (
const Message& msg, uint8_t burst) {
941 memcpy(buffer.buffer(),msg.buffer(),msg.length());
942 buffer.length(msg.length());
944 return sndData(buffer.buffer(),buffer.length(),burst);
969 uint8_t sndData(uint8_t *buf, uint8_t size, uint8_t burst) {
970 timeout.waitTimeout();
973 uint8_t result = HWRADIO::sndData(buf,size,burst);