{"payload":{"branches":{"default":{"name":"master","isDefault":true,"mergeQueueEnabled":false,"path":"/pConst/basic_verilog","rulesetsPath":null,"protectedByBranchProtections":false,"author":{"login":"pConst","name":"pConst","avatarUrl":"https://avatars.githubusercontent.com/u/949988?s=32&v=4","path":"/pConst"},"authoredDate":"2024-07-06T07:59:04.000+00:00","deleteable":false,"deleteProtected":false,"isBeingRenamed":false,"renameable":false},"yours":[],"active":[]},"hasMore":{"yours":false,"active":false},"protectThisBranchBanner":{"dismissed":true,"isSecurityAdvisory":false}},"title":"Branches ยท pConst/basic_verilog"}