.travis.yml

# Copyright 2020 ETH Zurich
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http:https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

language: cpp
# run on new infrastructure
dist: xenial
sudo: false
cache:
  apt: true
  directories:
    $RISCV
    $VERILATOR_ROOT
  timeout: 1000

# required packages to install
addons:
  apt:
    sources:
      - ubuntu-toolchain-r-test
    packages:
      - gcc-7
      - g++-7
      - gperf
      - autoconf
      - automake
      - autotools-dev
      - libmpc-dev
      - libmpfr-dev
      - libgmp-dev
      - gawk
      - build-essential
      - bison
      - flex
      - texinfo
      - python-pexpect
      - libusb-1.0-0-dev
      - default-jdk
      - zlib1g-dev
      - valgrind
env:
  global:
    - RISCV="/home/travis/riscv_install"
    - VERILATOR_ROOT="/home/travis/verilator-4.018"


before_install:
  - export CXX=g++-7 CC=gcc-7
  # setup dependent paths
  - export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
  - export LIBRARY_PATH=$RISCV/lib
  - export LD_LIBRARY_PATH=$RISCV/lib
  - export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/share/verilator/include
  - export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/share/verilator/include
  - export PKG_CONFIG_PATH=$VERILATOR_ROOT/share/pkgconfig
  # number of parallel jobs to use for make commands and simulation
  - export NUM_JOBS=4
  - ci/make-tmp.sh
  - git submodule update --init --recursive

stages:
  - download
  - compile1
  - compile2
  - test

jobs:
  include:
    - stage: download
      name: download pulp gcc
      script:
        - ci/download-pulp-gcc.sh

    - stage: compile2
      name: build verilator
      script:
        - ci/install-verilator.sh
    - stage: compile2
      name: build openocd
      script:
        - ci/get-openocd.sh

    - stage: test
      name: run openocd debug module tests
      script:
        - ci/veri-run-openocd-compliance.sh
    - stage: test
      name: run riscv tests
      script:
        - make -C tb/core firmware-veri-run
    - stage: test
      name: run verilator model
      script:
        - make -C tb/verilator-model/ all && ./tb/verilator-model/testbench
    - stage: test
      name: run riscv-compliance suite
      script:
        - export RISCV_PREFIX=riscv32-unknown-elf-
        - export RISCV_DEVICE=rv32imc
        - export RISCV_TARGET=ri5cy
        - export TARGET_SIM=${TRAVIS_BUILD_DIR}/tb/core/testbench_verilator
        - git clone https://github.com/bluewww/riscv-compliance.git -b target-ri5cy
        - make -C tb/core verilate
        - make -C riscv-compliance/ RISCV_ISA=rv32im && make -C riscv-compliance/ RISCV_ISA=rv32imc
#        - make -C riscv-compliance/ RISCV_ISA=rv32i # this is borked

# extra time during long builds
install: travis_wait