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this:\n\nrv32imc_zicsr_xcvhwlp-ilp32--\nrv32imfc_zicsr_xcvhwlp-ilp32--\nrv32imc_zicsr_zfinx_xcvhwlp-ilp32--\nrv32imfc_zicsr_xcvmac_xcvalu_xcvhwlp-ilp32-\n\nBootstrapped on x86_64\n\nbuild 'all-gcc' for x86_64 x sh-elf\n-------------- next part --------------\nAdd support for XCVhwlp extension in CV32E40P\n\n2023-11-18  Joern Rennecke  <joern.rennecke@embecosm.com>\n\ngcc/\n\t* common/config/riscv/riscv-common.cc (riscv_ext_version_table):\n\tAdd xcvhwlp.\n\t(riscv_ext_flag_table): Likewise.\n\t* config.gcc (riscv*): Add corev.o to extra_objs.\n\t* config/riscv/constraints.md (xcvl0s, xcvl0e): New constraints.\n\t(xcvl0c, xcvl1s, xcvl1e, xcvl1c): Likewise.\n\t(CVl0, xcvlb5, xcvlbs, xcvlbe, CV12): Likewise.\n\t* config/riscv/corev.cc: New file.\n\t* config/riscv/corev.md (UNSPEC_CV_LOOPBUG): New constant.\n\t(UNSPECV_CV_LOOPALIGN, UNSPEC_CV_FOLLOWS): Likewise.\n\t(UNSPEC_CV_LP_START_12): Likewise.\n\t(UNSPEC_CV_LP_END_5, UNSPEC_CV_LP_END_12): Likewise.\n\t(doloop_end_i, *cv_start, *cv_end, *cv_count): New insn patterns.\n\t(doloop_align): Likewise.\n\t(doloop_end, doloop_begin): New expanders.\n\t(doloop_begin_i): New define_insn_and_split.\n\t(doloop_begin_i+1): New splitter.\n\t* config/riscv/predicates.md (lpstart_reg_op): New predicate.\n\t(lpend_reg_op, lpcount_reg_op): Likewise.\n\t(label_register_operand, move_dest_operand): Likewise.\n\t* config/riscv/riscv-passes.def (pass_riscv_doloop_begin): Add.\n\t(pass_riscv_doloop_ranges):\n\tInsert before and after register allocation.\n\t* config/riscv/riscv-protos.h (make_pass_riscv_doloop_begin): Declare.\n\t(make_pass_riscv_doloop_ranges): Likewise.\n\t(riscv_can_use_doloop_p, riscv_invalid_within_doloop): Likewise.\n\t(hwloop_setupi_p, add_label_op_ref, corev_label_align): Likewise.\n\t* config/riscv/riscv.cc (riscv_regno_to_class): Add classes for\n\thardware loop start, end and counter registers.\n\t(riscv_strip_unspec_address): Also strip UNSPEC_CV_LP_START_12,\n\tUNSPEC_CV_LP_END_5 and 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for Issue #77\n\nSince the constraint `m` should assume non-xcvmem specific operands,\nwe redefined TARGET_MEM_CONSTRAINT and defined 'm' to exclude XCVmem\nspecific operands.\nConstraint `CVmp` defines addresses for post modify operands.\nConstraint `CVmr` defines addresses for reg + reg operands.\n\nFiles Changed:\n\n   * gcc/config/riscv/predicates.md (mem_post_inc): Prevent DI and\n     DF mode mem.\n     (mem_plus_reg): Likewise.\n   * gcc/config/riscv/constraints.md: Add new constraints `m`,\n     `CVmp` and `CVmr`.\n   * gcc/config/riscv/riscv.md: Remove constraint `am`.\n   * gcc/config/riscv/riscv.h: Redefine TARGET_MEM_CONSTRAINT to\n     `w`.\n   * gcc/testsuite/gcc.target/riscv/cv-mem-compile-1.c: New test.\n   * gcc/testsuite/gcc.target/riscv/cv-mem-compile-2.c: Likewise.\n   * gcc/testsuite/gcc.target/riscv/cv-mem-compile-3.c: Likewise.","shortMessageHtmlLink":"Fix for Issue <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"1956480255\" data-permission-text=\"Title is private\" data-url=\"https://github.com/openhwgroup/corev-gcc/issues/77\" data-hovercard-type=\"issue\" data-hovercard-url=\"/openhwgroup/corev-gcc/issues/77/hovercard\" href=\"https://github.com/openhwgroup/corev-gcc/issues/77\">#77</a>"}},{"before":"5c51b2667e0a5ce5f1c4d7c719e5e66e7bb76c65","after":"4a6bad0f495f038f948a00a40464e3d28761b0e4","ref":"refs/heads/development","pushedAt":"2023-11-02T14:30:20.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Exclude CORE-V memory tests for compressed code generation.\n\n\tThe generation of CORE-V memory instructions in these tests only\n\toccurs for performance optimization levels (01, 02, 03), but not\n\tfor unoptimized code (00, 0g) or for compressed optimization (0s,\n\tOz).\n\ngcc/testsuite/\n\n\t* gcc.target/riscv/cv-mem-lb-compile-1.c: Exclude running at -O0,\n\t-Os, -Og as well as -O0.\n\t* gcc.target/riscv/cv-mem-lb-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lbu-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lbu-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lh-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lh-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lhu-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lhu-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lw-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-lw-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-sb-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-sb-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-sh-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-sh-compile-2.c: Likewise.\n\t* gcc.target/riscv/cv-mem-sw-compile-1.c: Likewise.\n\t* gcc.target/riscv/cv-mem-sw-compile-2.c: Likewise.\n\nSigned-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com>","shortMessageHtmlLink":"Exclude CORE-V memory tests for compressed code generation."}},{"before":"38b1b3fdf856ba7e5768901303958716e331b4b8","after":"5c51b2667e0a5ce5f1c4d7c719e5e66e7bb76c65","ref":"refs/heads/development","pushedAt":"2023-10-30T12:20:22.000Z","pushType":"pr_merge","commitsCount":6,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Change test for cv.setupi to cv.setup\n\n    * gcc/testsuite/gcc.target/riscv/cv-hwlp-shiftsub.c: Updated test.","shortMessageHtmlLink":"Change test for cv.setupi to cv.setup"}},{"before":"a730fd987c880a7d4c3cd3c9b90c7adffdf780d2","after":"38b1b3fdf856ba7e5768901303958716e331b4b8","ref":"refs/heads/development","pushedAt":"2023-10-26T14:41:13.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"backport CORE-V HW loop.\n\ngcc/\n        * common/config/riscv/riscv-common.cc (riscv_ext_version_table):\n        Add xcv and xcvhwlp.\n        (riscv_ext_flag_table): Likewise.\n        * config.gcc (riscv*): Add corev.o to extra_objs.\n        * config/riscv/constraints.md (xcvl0s, xcvl0e): New constraints.\n        (xcvl0c, xcvl1s, xcvl1e, xcvl1c): Likewise.\n        * config/riscv/corev.cc: New file.\n        * config/riscv/corev.md (UNSPEC_CV_LOOPBUG): New constant.\n        (doloop_end_i, *cv_start, *cv_end, *cv_count): New insn patterns.\n        (doloop_end, doloop_begin): New expanders.\n        (doloop_begin_i): New define_insn_and_split.\n        * config/riscv/predicates.md (lpstart_reg_op): New predicate.\n        (lpend_reg_op, lpcount_reg_op): Likewise.\n\t(label_register_operand): Likewise.\n        * config/riscv/riscv-opts.h (MASK_XCVHWLP, TARGET_XCVHWLP): Define.\n        * config/riscv/riscv-passes.def (pass_riscv_doloop_begin): Add.\n        * config/riscv/riscv-protos.h (make_pass_riscv_doloop_begin): Declare.\n        (riscv_can_use_doloop_p, riscv_invalid_within_doloop): Likewise.\n        * hwloop_setupi_p, add_label_op_ref): Likewise.\n        * config/riscv/riscv.cc (riscv_regno_to_class): Add classes for\n        hardware loop start, end and counter registers.\n        (riscv_output_move): Add support to read loop counter registers.\n        (TARGET_CAN_USE_DOLOOP_P, TARGET_INVALID_WITHIN_DOLOOP): Override.\n        * config/riscv/riscv.h (enum reg_class): Add items for hardware\n        loop start, end and counter registers.\n        (REG_CLASS_NAMES): Likewise.\n        (REG_CLASS_CONTENTS): Likewise.\n        (REG_ALLOC_ORDER): Likewise.\n        (REGISTER_NAMES): Likewise.\n        * config/riscv/riscv.md (LPSTART0_REGNUM): New constant.\n        (LPEND0_REGNUM, LPCOUNT0_REGNUM): Likewise.\n        (LPSTART1_REGNUM, LPEND1_REGNUM, LPCOUNT1_REGNUM): Likewise.\n        (attr ext): New value xcvhwlp.\n        (attr enabled): Handle xcvhwlp.\n        (movsi_internal): Add alternatives to read loop counters.\n        * config/riscv/t-riscv (corev.o): New rule.\n        * doc/md.texi (doloop_end): Document oprional operand 2.\n        * loop-doloop.cc (doloop_optimize): Provide 3rd operand to\n        gen_doloop_end.\n        * target-insns.def (doloop_end): Add optional 3rd operand.\ngcc/testsuite/\n        * gcc.target/riscv/cv-hwlp-shiftsub.c: New test.","shortMessageHtmlLink":"backport CORE-V HW loop."}},{"before":"fe2bd9135b75e00070163b2ac7a2b5d163a7153b","after":"a730fd987c880a7d4c3cd3c9b90c7adffdf780d2","ref":"refs/heads/development","pushedAt":"2023-10-13T15:21:32.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Fix mem_plus_reg predicate\n\nFiles Changed:\n\n    * constraints.md: Add \"am\" which prevents (mem (plus reg reg).\n    * riscv.md: Add \"am\" constraint to movesf_hardfloat.\n    * predicates.md: Change mem_plus_reg to check that both operands are\n      registers.\n    * riscv.cc (riscv_legitimate_xcvmem_address_p): Tighten PLUS case.\n    * gcc.target/riscv/cv-mem-sw-fail-1.c: New Test.\n    * gcc.target/riscv/cv-mem-flw-fail.c: Likewise.","shortMessageHtmlLink":"Fix mem_plus_reg predicate"}},{"before":"276b33003b39bce3d17e18b9dd76ffc755366d28","after":"fe2bd9135b75e00070163b2ac7a2b5d163a7153b","ref":"refs/heads/development","pushedAt":"2023-10-13T08:31:54.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Merge pull request #75 from MaryBennett/mb-predicate\n\nFix mem_plus_reg predicate","shortMessageHtmlLink":"Merge pull request <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"1928730576\" data-permission-text=\"Title is private\" data-url=\"https://github.com/openhwgroup/corev-gcc/issues/75\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/openhwgroup/corev-gcc/pull/75/hovercard\" href=\"https://github.com/openhwgroup/corev-gcc/pull/75\">#75</a> from MaryBennett/mb-predicate"}},{"before":"e4cc5d4b14cd91d23a54a3e496fca491199a40d9","after":"276b33003b39bce3d17e18b9dd76ffc755366d28","ref":"refs/heads/development","pushedAt":"2023-10-05T13:11:08.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Fix cv.shuffle.b.sci immediate operand\n\nIssue [#68](https://github.com/openhwgroup/corev-gcc/issues/68)\n\nThe built-in for `cv.shuffle.b.sci` takes an 8-bit immediate operand.\nThe top two bits decides which `cv.shufflei*` instruction is used.\nThe other six bits are printed.\n\nFiles Changed:\n\n  * config/riscv/constraints.md: Added new constraints to check\n    the top two bits.\n  * config/riscv/corev.md: Likewise.\n  * config/riscv/riscv.cc: Added new operand type for printing the\n    bottom six bits.\n  * testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: Updated test.\n  * testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: Likewise.\n  * testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: Likewise.\n  * testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: Likewise.\n  * testsuite/gcc.target/riscv/cv-xcvsimd-march-compile-1.c: Likewise.","shortMessageHtmlLink":"Fix cv.shuffle.b.sci immediate operand"}},{"before":null,"after":"e4cc5d4b14cd91d23a54a3e496fca491199a40d9","ref":"refs/heads/development-7ef44579787","pushedAt":"2023-10-05T13:04:18.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Merge pull request #72 from MaryBennett/mb-shuffle\n\nFix cv.shuffle.b.sci immediate operand","shortMessageHtmlLink":"Merge pull request <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"1890432278\" data-permission-text=\"Title is private\" data-url=\"https://github.com/openhwgroup/corev-gcc/issues/72\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/openhwgroup/corev-gcc/pull/72/hovercard\" href=\"https://github.com/openhwgroup/corev-gcc/pull/72\">#72</a> from MaryBennett/mb-shuffle"}},{"before":"9bcb04a94bddbb92eeacb84a2c69e9e0e14769a7","after":"e4cc5d4b14cd91d23a54a3e496fca491199a40d9","ref":"refs/heads/development","pushedAt":"2023-10-05T12:56:50.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"MaryBennett","name":"MaryBennett","path":"/MaryBennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/29869061?s=80&v=4"},"commit":{"message":"Merge pull request #72 from MaryBennett/mb-shuffle\n\nFix cv.shuffle.b.sci immediate operand","shortMessageHtmlLink":"Merge pull request <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"1890432278\" data-permission-text=\"Title is private\" data-url=\"https://github.com/openhwgroup/corev-gcc/issues/72\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/openhwgroup/corev-gcc/pull/72/hovercard\" href=\"https://github.com/openhwgroup/corev-gcc/pull/72\">#72</a> from MaryBennett/mb-shuffle"}},{"before":"54e2f9148ce1f8f1c38f50d157e6db65ccec253a","after":"9bcb04a94bddbb92eeacb84a2c69e9e0e14769a7","ref":"refs/heads/development","pushedAt":"2023-09-07T15:14:43.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"jeremybennett","name":"Jeremy Bennett","path":"/jeremybennett","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1662021?s=80&v=4"},"commit":{"message":"Fixes to xcvbitmanip and xcvsimd\n\nThe immediate operand order in instructions `cv.bclr` and `cv.bset`\nwas wrong. Tests updated to match.\n\nTests for instructions `cv.extract[u].[h,b]` and `cv.insert.[h,b]`\nfixed for unsigned immediate `sel`.\n\nInstructions `cv.s[ll,ra,la].sc.[h,b]` fixed for unsigned immediate\n`j`. Tests updated to match.\n\nFiles Changed:\n\n  * config/riscv/corev.md: Various fixes.\n  * gcc.target/riscv/cv-march-xcvbitmanip-compile-bclr.c: Fixed test.\n  * gcc.target/riscv/cv-march-xcvbitmanip-compile-bset.c: Likewise.\n  * gcc.target/riscv/cv-simd-extract-b-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-extract-h-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-insert-b-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-insert-h-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: Likewise.\n  * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: Likewise.\n\nSigned-off-by: Mary Bennett <mary.bennett@embecosm.com>","shortMessageHtmlLink":"Fixes to xcvbitmanip and xcvsimd"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEg7L06gA","startCursor":null,"endCursor":null}},"title":"Activity · openhwgroup/corev-gcc"}