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serial1.sdc.bak
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serial1.sdc.bak
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## Generated SDC file "serial1.sdc"
## Copyright (C) 2018 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition"
## DATE "Sat May 22 11:51:39 2021"
##
## DEVICE "10M08SAE144C8GES"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clock_ext_osc} -period 1.000 -waveform { 0.000 0.500 } [get_ports {clock_ext_osc}]
create_clock -name {processor:inst|scanclk} -period 1.000 -waveform { 0.000 0.500 } [get_registers {processor:inst|scanclk}]
create_clock -name {usb_clk60} -period 1.000 -waveform { 0.000 0.500 } [get_ports {usb_clk60}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {inst15|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst15|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 5 -master_clock {clock_ext_osc} [get_pins {inst15|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {inst15|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst15|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 5 -divide_by 2 -master_clock {clock_ext_osc} [get_pins {inst15|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {inst15|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {inst15|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 5 -divide_by 2 -phase 180/1 -master_clock {clock_ext_osc} [get_pins {inst15|altpll_component|auto_generated|pll1|clk[4]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {usb_clk60}] -rise_to [get_clocks {usb_clk60}] 0.070
set_clock_uncertainty -rise_from [get_clocks {usb_clk60}] -fall_to [get_clocks {usb_clk60}] 0.070
set_clock_uncertainty -rise_from [get_clocks {usb_clk60}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {usb_clk60}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {usb_clk60}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {usb_clk60}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {usb_clk60}] -rise_to [get_clocks {usb_clk60}] 0.070
set_clock_uncertainty -fall_from [get_clocks {usb_clk60}] -fall_to [get_clocks {usb_clk60}] 0.070
set_clock_uncertainty -fall_from [get_clocks {usb_clk60}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {usb_clk60}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {usb_clk60}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {usb_clk60}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {usb_clk60}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {usb_clk60}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {clock_ext_osc}] 0.130
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {clock_ext_osc}] 0.130
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {processor:inst|scanclk}] -setup 0.120
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {processor:inst|scanclk}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {processor:inst|scanclk}] -setup 0.120
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {processor:inst|scanclk}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.140
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.140
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {usb_clk60}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {usb_clk60}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {clock_ext_osc}] 0.130
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {clock_ext_osc}] 0.130
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {processor:inst|scanclk}] -setup 0.120
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {processor:inst|scanclk}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {processor:inst|scanclk}] -setup 0.120
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {processor:inst|scanclk}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.140
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.140
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {clock_ext_osc}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -rise_from [get_clocks {processor:inst|scanclk}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {processor:inst|scanclk}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.120
set_clock_uncertainty -rise_from [get_clocks {processor:inst|scanclk}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {processor:inst|scanclk}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.120
set_clock_uncertainty -rise_from [get_clocks {processor:inst|scanclk}] -rise_to [get_clocks {processor:inst|scanclk}] 0.070
set_clock_uncertainty -rise_from [get_clocks {processor:inst|scanclk}] -fall_to [get_clocks {processor:inst|scanclk}] 0.070
set_clock_uncertainty -fall_from [get_clocks {processor:inst|scanclk}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {processor:inst|scanclk}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.120
set_clock_uncertainty -fall_from [get_clocks {processor:inst|scanclk}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {processor:inst|scanclk}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.120
set_clock_uncertainty -fall_from [get_clocks {processor:inst|scanclk}] -rise_to [get_clocks {processor:inst|scanclk}] 0.070
set_clock_uncertainty -fall_from [get_clocks {processor:inst|scanclk}] -fall_to [get_clocks {processor:inst|scanclk}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {usb_clk60}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {usb_clk60}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {usb_clk60}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {usb_clk60}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {usb_clk60}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[4]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[1]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] 0.070
set_clock_uncertainty -rise_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {clock_ext_osc}] -setup 0.140
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {clock_ext_osc}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] 0.070
set_clock_uncertainty -fall_from [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst15|altpll_component|auto_generated|pll1|clk[0]}] 0.070
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -from [get_keepers {**}] -to [get_keepers {*phasedone_state*}]
set_false_path -from [get_keepers {**}] -to [get_keepers {*internal_phasestep*}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[0]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[0]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[1]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[1]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[2]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[2]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[3]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[3]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[4]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[4]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[5]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[5]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[6]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[6]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[7]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[7]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[8]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[8]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[9]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[9]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[10]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[10]}]
set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[11]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[11]}]
set_false_path -from [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|chsel[*]}] -to [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|chsel[*]}]
set_false_path -from [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|soc}] -to [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|soc}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
#**************************************************************
# Set Net Delay
#**************************************************************
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|eoc}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|eoc}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|clk_dft}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|clk_dft}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[0]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[1]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[2]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[3]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[4]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[5]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[6]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[7]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[8]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[9]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[10]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[11]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[0]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[1]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[2]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[3]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[4]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[5]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[6]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[7]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[8]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[9]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[10]}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[11]}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|u_control_fsm|chsel[*]|q}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|u_control_fsm|chsel[*]|q}]
set_net_delay -max 5.000 -from [get_pins -compatibility_mode {*|u_control_fsm|soc|q}]
set_net_delay -min 0.000 -from [get_pins -compatibility_mode {*|u_control_fsm|soc|q}]