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  • University of Minneapolis, Twin Cities
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  • Autograder scripts for grading C++ programs on Gradescope, written in Python.

    Python 1 GNU General Public License v3.0 Updated Oct 4, 2024
  • chipyard Public

    Forked from ucb-bar/chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala BSD 3-Clause "New" or "Revised" License Updated Jun 30, 2024
  • EE4301-Labs Public

    Digital Design with Programmable Logic. Labs with Basys3 FPGA.

    Tcl Updated Apr 28, 2024
  • CacheSim Public

    Forked from CMU-SAFARI/Pythia

    A Cache Simulator where replacement policy, pre-fetcher, branch predictor and cache parameters can be customized.

    C++ 1 MIT License Updated Apr 23, 2024
  • Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C++ Other Updated Apr 22, 2024
  • DRIM Public

    Forked from ic-lab-duth/DRIM

    DUTH RISC-V Microprocessor

    SystemVerilog MIT License Updated Feb 13, 2024
  • RTLLM Public

    Forked from hkust-zhiyao/RTLLM

    An open-source benchmark for generating design RTL with natural language

    Verilog Updated Jan 31, 2024
  • riscv-dv Public

    Forked from chipsalliance/riscv-dv

    Random instruction generator for RISC-V processor verification

    Python Apache License 2.0 Updated Jul 15, 2023
  • autoprompt Public

    Forked from ucinlp/autoprompt

    AutoPrompt: Automatic Prompt Construction for Masked Language Models.

    Python Apache License 2.0 Updated Jun 12, 2023
  • ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog Apache License 2.0 Updated May 18, 2023
  • Functional verification project for the CORE-V family of RISC-V cores.

    Assembly Other Updated Apr 17, 2023
  • sbt Public

    Batchfile Apache License 2.0 Updated Mar 12, 2022
  • A complete guide for interfacing SIM808 module with Arduino

    C++ Updated Aug 13, 2021
  • cv32e40p Public

    Forked from openhwgroup/cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog Other Updated May 20, 2021
  • This is a repository reporting how to create GradeScope Autograders for C/C++ using Python.

    Python Updated Dec 31, 2020