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3 stars written in Verilog
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,428 499 Updated Jul 10, 2024

A small, light weight, RISC CPU soft core

Verilog 1,228 152 Updated Jul 1, 2024

🌱 Open source ecosystem for open FPGA boards

Verilog 779 131 Updated Jun 24, 2024