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Stars

12 stars written in Verilog
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nvdla / hw

RTL, Cmodel, and testbench for NVDLA

Verilog 1,708 565 Updated Mar 2, 2022

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,497 525 Updated Sep 5, 2024

Obijuan / open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Verilog 766 194 Updated Apr 15, 2020

efabless / caravel_user_project

https://caravel-user-project.readthedocs.io

Verilog 177 329 Updated Sep 3, 2024

icebreaker-fpga / icebreaker-workshop

iCEBreaker Workshop

Verilog 119 25 Updated Feb 1, 2024

vidor-libraries / VidorFPGA

repository for Vidor FPGA IP blocks and projects

Verilog 90 34 Updated Jul 28, 2018

efabless / clear

Verilog 55 6 Updated Aug 19, 2024

alinxalinx / AX301

AX301

Verilog 26 20 Updated May 31, 2018

TinyTapeout / tt08-verilog-template

Submission template for Tiny Tapeout 8 - Verilog HDL Projects

Verilog 13 75 Updated Jul 12, 2024

SimDaSong / 4-bit-cpu

4 bit CPU (logisim, verilog)

Verilog 7 2 Updated Nov 26, 2021

TinyTapeout / tt05-verilog-demo

Forked from TinyTapeout/tt04-verilog-demo

Verilog Demo, updated for Tiny Tapeout 05

Verilog 7 77 Updated Nov 4, 2023

ZiyangYE / LicheeTang25k_VexRV_micro

Verilog 2 2 Updated Jan 29, 2024