Stars
12
stars
written in Verilog
Clear filter
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
https://caravel-user-project.readthedocs.io
repository for Vidor FPGA IP blocks and projects
Submission template for Tiny Tapeout 8 - Verilog HDL Projects
Verilog Demo, updated for Tiny Tapeout 05