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ms.c
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ms.c
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/* Driver for Realtek RTS51xx USB card reader
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http:https://www.gnu.org/licenses/>.
*
* Author:
* wwang ([email protected])
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
* Maintainer:
* Edwin Rong ([email protected])
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
*/
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include "debug.h"
#include "trace.h"
#include "rts51x.h"
#include "rts51x_transport.h"
#include "rts51x_scsi.h"
#include "rts51x_card.h"
#include "ms.h"
static inline void ms_set_err_code(struct rts51x_chip *chip, u8 err_code)
{
struct ms_info *ms_card = &(chip->ms_card);
ms_card->err_code = err_code;
}
static inline int ms_check_err_code(struct rts51x_chip *chip, u8 err_code)
{
struct ms_info *ms_card = &(chip->ms_card);
return ms_card->err_code == err_code;
}
static int ms_parse_err_code(struct rts51x_chip *chip)
{
TRACE_RET(chip, STATUS_FAIL);
}
static int ms_transfer_tpc(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,
u8 cnt, u8 cfg)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
RTS51X_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
PINGPONG_BUFFER);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
MS_TRANSFER_START | trans_mode);
rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
MS_TRANSFER_END);
rts51x_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, 2, 5000);
if (CHECK_MS_TRANS_FAIL(chip, retval)) {
rts51x_clear_ms_error(chip);
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
if (!(tpc & 0x08)) { /* Read Packet */
/* Check CRC16 & Ready Timeout */
if (chip->rsp_buf[1] & MS_CRC16_ERR) {
ms_set_err_code(chip, MS_CRC16_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
} else { /* Write Packet */
if (CHK_MSPRO(ms_card) && !(chip->rsp_buf[1] & 0x80)) {
if (chip->rsp_buf[1] & (MS_INT_ERR | MS_INT_CMDNK)) {
ms_set_err_code(chip, MS_CMD_NK);
TRACE_RET(chip, ms_parse_err_code(chip));
}
}
}
/* Check Timeout of Ready Signal */
if (chip->rsp_buf[1] & MS_RDY_TIMEOUT) {
rts51x_clear_ms_error(chip);
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
return STATUS_SUCCESS;
}
int ms_transfer_data(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,
u16 sec_cnt, u8 cfg, int mode_2k, int use_sg, void *buf,
int buf_len)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
u8 val, err_code = 0, flag = 0;
enum dma_data_direction dir;
unsigned int pipe;
if (!buf || !buf_len)
TRACE_RET(chip, STATUS_FAIL);
if (trans_mode == MS_TM_AUTO_READ) {
pipe = RCV_BULK_PIPE(chip);
dir = DMA_FROM_DEVICE;
flag = MODE_CDIR;
err_code = MS_FLASH_READ_ERROR;
} else if (trans_mode == MS_TM_AUTO_WRITE) {
pipe = SND_BULK_PIPE(chip);
dir = DMA_TO_DEVICE;
flag = MODE_CDOR;
err_code = MS_FLASH_WRITE_ERROR;
} else {
TRACE_RET(chip, STATUS_FAIL);
}
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF,
(u8) (sec_cnt >> 8));
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
(u8) sec_cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
RING_BUFFER);
if (mode_2k)
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,
MS_2K_SECTOR_MODE);
else
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,
0);
rts51x_trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
MS_TRANSFER_START | trans_mode);
rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
MS_TRANSFER_END);
retval = rts51x_send_cmd(chip, flag | STAGE_MS_STATUS, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval =
rts51x_transfer_data_rcc(chip, pipe, buf, buf_len, use_sg, NULL,
15000, flag);
if (retval != STATUS_SUCCESS) {
ms_set_err_code(chip, err_code);
rts51x_clear_ms_error(chip);
TRACE_RET(chip, retval);
}
retval = rts51x_get_rsp(chip, 3, 15000);
if (CHECK_MS_TRANS_FAIL(chip, retval)) {
ms_set_err_code(chip, err_code);
rts51x_clear_ms_error(chip);
TRACE_RET(chip, STATUS_FAIL);
}
ms_card->last_rw_int = val = chip->rsp_buf[1];
if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
TRACE_RET(chip, STATUS_FAIL);
return STATUS_SUCCESS;
}
int ms_write_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,
int data_len)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
if (!data || (data_len < cnt))
TRACE_RET(chip, STATUS_ERROR);
rts51x_init_cmd(chip);
for (i = 0; i < cnt; i++) {
rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,
data[i]);
}
if (cnt % 2)
rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i,
0xFF, 0xFF);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
PINGPONG_BUFFER);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
MS_TRANSFER_START | MS_TM_WRITE_BYTES);
rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
MS_TRANSFER_END);
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, 1, 5000);
if (CHECK_MS_TRANS_FAIL(chip, retval)) {
u8 val = 0;
rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
rts51x_clear_ms_error(chip);
if (!(tpc & 0x08)) { /* Read Packet */
/* Check CRC16 & Ready Timeout */
if (val & MS_CRC16_ERR) {
ms_set_err_code(chip, MS_CRC16_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
} else { /* Write Packet */
if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
ms_set_err_code(chip, MS_CMD_NK);
TRACE_RET(chip,
ms_parse_err_code(chip));
}
}
}
/* Check Timeout of Ready Signal */
if (val & MS_RDY_TIMEOUT) {
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
return STATUS_SUCCESS;
}
int ms_read_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,
int data_len)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
if (!data)
TRACE_RET(chip, STATUS_ERROR);
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
PINGPONG_BUFFER);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
MS_TRANSFER_START | MS_TM_READ_BYTES);
rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
MS_TRANSFER_END);
for (i = 0; i < data_len - 1; i++)
rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
if (data_len % 2)
rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0,
0);
else
rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
0, 0);
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, data_len + 1, 5000);
if (CHECK_MS_TRANS_FAIL(chip, retval)) {
u8 val = 0;
rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
rts51x_clear_ms_error(chip);
if (!(tpc & 0x08)) { /* Read Packet */
/* Check CRC16 & Ready Timeout */
if (val & MS_CRC16_ERR) {
ms_set_err_code(chip, MS_CRC16_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
} else { /* Write Packet */
if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
ms_set_err_code(chip, MS_CMD_NK);
TRACE_RET(chip,
ms_parse_err_code(chip));
}
}
}
/* Check Timeout of Ready Signal */
if (val & MS_RDY_TIMEOUT) {
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
rts51x_read_rsp_buf(chip, 1, data, data_len);
return STATUS_SUCCESS;
}
int ms_set_rw_reg_addr(struct rts51x_chip *chip,
u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
{
int retval, i;
u8 data[4];
data[0] = read_start;
data[1] = read_cnt;
data[2] = write_start;
data[3] = write_cnt;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_write_bytes(chip, SET_RW_REG_ADRS, 4, NO_WAIT_INT, data,
4);
if (retval == STATUS_SUCCESS)
return STATUS_SUCCESS;
rts51x_clear_ms_error(chip);
}
TRACE_RET(chip, STATUS_FAIL);
}
static int ms_send_cmd(struct rts51x_chip *chip, u8 cmd, u8 cfg)
{
u8 data[2];
data[0] = cmd;
data[1] = 0;
return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
}
static int ms_set_cmd(struct rts51x_chip *chip,
u8 read_start, u8 read_count,
u8 write_start, u8 write_count,
u8 cmd, u8 cfg, u8 *data, int data_len, u8 *int_stat)
{
int retval, i;
u8 val;
if (!data || (data_len <= 0) || (data_len > 128)) {
RTS51X_DEBUGP("ms_set_cmd (data_len = %d)\n", data_len);
TRACE_RET(chip, STATUS_FAIL);
}
retval =
ms_set_rw_reg_addr(chip, read_start, read_count, write_start,
write_count);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_write_bytes(chip, WRITE_REG, write_count, NO_WAIT_INT,
data, data_len);
if (retval == STATUS_SUCCESS)
break;
}
if (i == MS_MAX_RETRY_COUNT)
TRACE_RET(chip, STATUS_FAIL);
ms_set_err_code(chip, MS_NO_ERROR);
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_send_cmd(chip, cmd, WAIT_INT);
if (retval == STATUS_SUCCESS)
break;
}
if (i == MS_MAX_RETRY_COUNT)
TRACE_RET(chip, STATUS_FAIL);
/* GET_INT Register */
ms_set_err_code(chip, MS_NO_ERROR);
retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
if (int_stat)
*int_stat = val;
return STATUS_SUCCESS;
}
#ifdef MS_SPEEDUP
static int ms_auto_set_cmd(struct rts51x_chip *chip,
u8 read_start, u8 read_count,
u8 write_start, u8 write_count,
u8 cmd, u8 cfg, u8 *data, int data_len,
u8 *int_stat)
{
int retval;
int i;
if (!data || (data_len <= 0) || (data_len > 128)) {
RTS51X_DEBUGP("ms_auto_set_cmd (data_len = %d)\n", data_len);
TRACE_RET(chip, STATUS_FAIL);
}
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_START, 0xFF, read_start);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_COUNT, 0xFF, read_count);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_START, 0xFF, write_start);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_COUNT, 0xFF, write_count);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_COMMAND, 0xFF, cmd);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
PINGPONG_BUFFER);
for (i = 0; i < data_len; i++) {
rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,
data[i]);
}
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
MS_TRANSFER_START | MS_TM_SET_CMD);
rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
MS_TRANSFER_END);
retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, 3, 5000);
if (CHECK_MS_TRANS_FAIL(chip, retval)) {
rts51x_clear_ms_error(chip);
TRACE_RET(chip, STATUS_FAIL);
}
if (int_stat)
*int_stat = chip->rsp_buf[2];
return STATUS_SUCCESS;
}
#endif
static int ms_set_init_para(struct rts51x_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
if (CHK_HG8BIT(ms_card)) {
if (chip->asic_code)
ms_card->ms_clock = chip->option.asic_ms_hg_clk;
else
ms_card->ms_clock = chip->option.fpga_ms_hg_clk;
} else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
if (chip->asic_code)
ms_card->ms_clock = chip->option.asic_ms_4bit_clk;
else
ms_card->ms_clock = chip->option.fpga_ms_4bit_clk;
} else {
if (chip->asic_code)
ms_card->ms_clock = 38;
else
ms_card->ms_clock = CLK_40;
}
retval = switch_clock(chip, ms_card->ms_clock);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_select_card(chip, MS_CARD);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return STATUS_SUCCESS;
}
int ms_switch_clock(struct rts51x_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
retval = rts51x_select_card(chip, MS_CARD);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = switch_clock(chip, ms_card->ms_clock);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return STATUS_SUCCESS;
}
static void ms_pull_ctl_disable(struct rts51x_chip *chip)
{
if (CHECK_PKG(chip, LQFP48)) {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
} else {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
}
}
static void ms_pull_ctl_enable(struct rts51x_chip *chip)
{
if (CHECK_PKG(chip, LQFP48)) {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
} else {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
}
}
static int ms_prepare_reset(struct rts51x_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
ms_card->ms_type = 0;
ms_card->check_ms_flow = 0;
ms_card->switch_8bit_fail = 0;
ms_card->delay_write.delay_write_flag = 0;
ms_card->pro_under_formatting = 0;
rts51x_init_cmd(chip);
if (chip->asic_code) {
ms_pull_ctl_enable(chip);
} else {
rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
FPGA_MS_PULL_CTL_BIT | 0x20, 0);
}
/* Tri-state MS output */
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
if (!chip->option.FT2_fast_mode) {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
POWER_OFF);
}
retval = rts51x_send_cmd(chip, MODE_C, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
if (!chip->option.FT2_fast_mode) {
wait_timeout(250);
rts51x_card_power_on(chip, MS_CARD);
wait_timeout(150);
#ifdef SUPPORT_OCP
rts51x_get_card_status(chip, &(chip->card_status));
/* get OCP status */
chip->ocp_stat = (chip->card_status >> 4) & 0x03;
if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
chip->ocp_stat);
TRACE_RET(chip, STATUS_FAIL);
}
#endif
}
rts51x_init_cmd(chip);
/* Enable MS Output */
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN,
MS_OUTPUT_EN);
/* Reset Registers */
if (chip->asic_code)
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,
SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
else
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,
SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
NO_WAIT_INT | NO_AUTO_READ_INT_REG);
retval = rts51x_send_cmd(chip, MODE_C, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return ms_set_init_para(chip);
}
static int ms_identify_media_type(struct rts51x_chip *chip, int switch_8bit_bus)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 val;
retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
/* Get Register form MS-PRO card */
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6,
NO_WAIT_INT);
if (retval == STATUS_SUCCESS)
break;
}
if (i == MS_MAX_RETRY_COUNT)
TRACE_RET(chip, STATUS_FAIL);
RTS51X_READ_REG(chip, PPBUF_BASE2 + 2, &val);
RTS51X_DEBUGP("Type register: 0x%x\n", val);
if (val != 0x01) {
if (val != 0x02)
ms_card->check_ms_flow = 1;
TRACE_RET(chip, STATUS_FAIL);
}
/* Category Register */
RTS51X_READ_REG(chip, PPBUF_BASE2 + 4, &val);
RTS51X_DEBUGP("Category register: 0x%x\n", val);
if (val != 0) {
ms_card->check_ms_flow = 1;
TRACE_RET(chip, STATUS_FAIL);
}
/* Class Register */
RTS51X_READ_REG(chip, PPBUF_BASE2 + 5, &val);
RTS51X_DEBUGP("Class register: 0x%x\n", val);
if (val == 0) {
RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
if (val & WRT_PRTCT)
chip->card_wp |= MS_CARD;
else
chip->card_wp &= ~MS_CARD;
} else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
chip->card_wp |= MS_CARD;
} else {
ms_card->check_ms_flow = 1;
TRACE_RET(chip, STATUS_FAIL);
}
ms_card->ms_type |= TYPE_MSPRO;
/* Check MSPro-HG Card, use IF Mode Register to distinguish */
RTS51X_READ_REG(chip, PPBUF_BASE2 + 3, &val);
RTS51X_DEBUGP("IF Mode register: 0x%x\n", val);
if (val == 0) {
ms_card->ms_type &= 0x0F;
} else if (val == 7) {
if (switch_8bit_bus)
ms_card->ms_type |= MS_HG;
else
ms_card->ms_type &= 0x0F;
} else {
TRACE_RET(chip, STATUS_FAIL);
}
/* end Procedure to identify Media Type */
return STATUS_SUCCESS;
}
static int ms_confirm_cpu_startup(struct rts51x_chip *chip)
{
int retval, i, k;
u8 val;
/* Confirm CPU StartUp */
k = 0;
do {
if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
TRACE_RET(chip, STATUS_FAIL);
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
1);
if (retval == STATUS_SUCCESS)
break;
}
if (i == MS_MAX_RETRY_COUNT)
TRACE_RET(chip, STATUS_FAIL);
if (k > 100)
TRACE_RET(chip, STATUS_FAIL);
k++;
wait_timeout(100);
} while (!(val & INT_REG_CED));
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
if (retval == STATUS_SUCCESS)
break;
}
if (i == MS_MAX_RETRY_COUNT)
TRACE_RET(chip, STATUS_FAIL);
if (val & INT_REG_ERR) {
if (val & INT_REG_CMDNK) { /* CMDNK = 1 */
chip->card_wp |= (MS_CARD);
} else { /* CMDNK = 0 */
TRACE_RET(chip, STATUS_FAIL);
}
}
/*-- end confirm CPU startup */
return STATUS_SUCCESS;
}
static int ms_switch_parallel_bus(struct rts51x_chip *chip)
{
int retval, i;
u8 data[2];
data[0] = PARALLEL_4BIT_IF;
data[1] = 0;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
if (retval == STATUS_SUCCESS)
break;
}
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return STATUS_SUCCESS;
}
static int ms_switch_8bit_bus(struct rts51x_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 data[2];
data[0] = PARALLEL_8BIT_IF;
data[1] = 0;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
if (retval == STATUS_SUCCESS)
break;
}
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, STATUS_FAIL);
RTS51X_WRITE_REG(chip, MS_CFG, 0x98,
MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
ms_card->ms_type |= MS_8BIT;
retval = ms_set_init_para(chip);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
NO_WAIT_INT);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
}
return STATUS_SUCCESS;
}
static int ms_pro_reset_flow(struct rts51x_chip *chip, int switch_8bit_bus)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
for (i = 0; i < 3; i++) {
retval = ms_prepare_reset(chip);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = ms_identify_media_type(chip, switch_8bit_bus);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = ms_confirm_cpu_startup(chip);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = ms_switch_parallel_bus(chip);
if (retval != STATUS_SUCCESS) {
if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
TRACE_RET(chip, STATUS_FAIL);
continue;
} else {
break;
}
}
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
RTS51X_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
RTS51X_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
retval = ms_set_init_para(chip);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
if (CHK_MSHG(ms_card) && switch_8bit_bus) {
retval = ms_switch_8bit_bus(chip);
if (retval != STATUS_SUCCESS) {
ms_card->switch_8bit_fail = 1;
TRACE_RET(chip, retval);
}
}
return STATUS_SUCCESS;
}
#ifdef XC_POWERCLASS
static int msxc_change_power(struct rts51x_chip *chip, u8 mode)
{
int retval;
u8 buf[6];
rts51x_ms_cleanup_work(chip);
/* Set Parameter Register */
retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
buf[0] = 0;
buf[1] = mode;
buf[2] = 0;
buf[3] = 0;
buf[4] = 0;
buf[5] = 0;
retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
RTS51X_READ_REG(chip, MS_TRANS_CFG, buf);
if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
TRACE_RET(chip, STATUS_FAIL);
return STATUS_SUCCESS;
}
#endif
static int ms_read_attribute_info(struct rts51x_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 val, *buf, class_code, device_type, sub_class, data[16];
u16 total_blk = 0, blk_size = 0;
#ifdef SUPPORT_MSXC
u32 xc_total_blk = 0, xc_blk_size = 0;
#endif
u32 sys_info_addr = 0, sys_info_size;
#ifdef SUPPORT_PCGL_1P18
u32 model_name_addr = 0, model_name_size;
int found_sys_info = 0, found_model_name = 0;
#endif
retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
if (CHK_MS8BIT(ms_card))
data[0] = PARALLEL_8BIT_IF;
else
data[0] = PARALLEL_4BIT_IF;
data[1] = 0;
data[2] = 0x40;
data[3] = 0;
data[4] = 0;
data[5] = 0;
/* Start address 0 */
data[6] = 0;
data[7] = 0;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval =
ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data,
8);
if (retval == STATUS_SUCCESS)
break;
}
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
buf = kmalloc(64 * 512, GFP_KERNEL);
if (buf == NULL)
TRACE_RET(chip, STATUS_NOMEM);
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
if (retval != STATUS_SUCCESS)
continue;
retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);
if (retval != STATUS_SUCCESS) {
kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (!(val & MS_INT_BREQ)) {
kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
retval =
ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
0x40, WAIT_INT, 0, 0, buf, 64 * 512);
if (retval == STATUS_SUCCESS)
break;
else
rts51x_clear_ms_error(chip);
}
if (retval != STATUS_SUCCESS) {
kfree(buf);
TRACE_RET(chip, retval);
}
i = 0;
do {
retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);
if (retval != STATUS_SUCCESS) {
kfree(buf);
TRACE_RET(chip, retval);
}
if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
break;
retval =
ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA,
0, WAIT_INT);
if (retval != STATUS_SUCCESS) {
kfree(buf);
TRACE_RET(chip, retval);
}
i++;
} while (i < 1024);