Liu Chaojia liucj97

🎯

Focusing

Achievements

5 stars written in Verilog

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,091 749 Updated Jun 27, 2024

Verilog AXI components for FPGA implementation

Verilog 1,459 439 Updated Dec 7, 2023

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Verilog 229 32 Updated Nov 29, 2018

异步FIFO的内部实现

Verilog 24 10 Updated Aug 26, 2018

parameterized AXIS FIFO design

Verilog 9 8 Updated Jul 18, 2017