-
Notifications
You must be signed in to change notification settings - Fork 652
/
mlx5dv_dr.h
1782 lines (1620 loc) · 54.2 KB
/
mlx5dv_dr.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2019, Mellanox Technologies. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _MLX5_DV_DR_
#define _MLX5_DV_DR_
#include <ccan/list.h>
#include <ccan/minmax.h>
#include <util/bitmap.h>
#include <stdatomic.h>
#include "mlx5dv.h"
#include "mlx5_ifc.h"
#include "mlx5.h"
#define DR_RULE_MAX_STES 20
#define DR_ACTION_MAX_STES 7
#define DR_ACTION_ASO_CROSS_GVMI_STES 2
/* Use up to 14 send rings. This number provided the best performance */
#define DR_MAX_SEND_RINGS 14
#define NUM_OF_LOCKS DR_MAX_SEND_RINGS
#define WIRE_PORT 0xFFFF
#define ECPF_PORT 0xFFFE
#define DR_STE_SVLAN 0x1
#define DR_STE_CVLAN 0x2
#define CVLAN_ETHERTYPE 0x8100
#define SVLAN_ETHERTYPE 0x88a8
#define NUM_OF_FLEX_PARSERS 8
#define DR_STE_MAX_FLEX_0_ID 3
#define DR_STE_MAX_FLEX_1_ID 7
#define DR_VPORTS_BUCKETS 256
#define ACTION_CACHE_LINE_SIZE 64
#define dr_dbg(dmn, arg...) dr_dbg_ctx((dmn)->ctx, ##arg)
#define dr_dbg_ctx(ctx, arg...) \
mlx5_dbg(to_mctx(ctx)->dbg_fp, MLX5_DBG_DR, ##arg);
enum dr_icm_chunk_size {
DR_CHUNK_SIZE_1,
DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */
DR_CHUNK_SIZE_2,
DR_CHUNK_SIZE_4,
DR_CHUNK_SIZE_8,
DR_CHUNK_SIZE_16,
DR_CHUNK_SIZE_32,
DR_CHUNK_SIZE_64,
DR_CHUNK_SIZE_128,
DR_CHUNK_SIZE_256,
DR_CHUNK_SIZE_512,
DR_CHUNK_SIZE_1K,
DR_CHUNK_SIZE_2K,
DR_CHUNK_SIZE_4K,
DR_CHUNK_SIZE_8K,
DR_CHUNK_SIZE_16K,
DR_CHUNK_SIZE_32K,
DR_CHUNK_SIZE_64K,
DR_CHUNK_SIZE_128K,
DR_CHUNK_SIZE_256K,
DR_CHUNK_SIZE_512K,
DR_CHUNK_SIZE_1024K,
DR_CHUNK_SIZE_2048K,
DR_CHUNK_SIZE_4096K,
DR_CHUNK_SIZE_8192K,
DR_CHUNK_SIZE_16384K,
DR_CHUNK_SIZE_MAX,
};
enum dr_icm_type {
DR_ICM_TYPE_STE,
DR_ICM_TYPE_MODIFY_ACTION,
DR_ICM_TYPE_MODIFY_HDR_PTRN,
DR_ICM_TYPE_MAX,
};
static inline enum dr_icm_chunk_size
dr_icm_next_higher_chunk(enum dr_icm_chunk_size chunk)
{
chunk += 2;
if (chunk < DR_CHUNK_SIZE_MAX)
return chunk;
return DR_CHUNK_SIZE_MAX;
}
enum dr_ste_lu_type {
DR_STE_LU_TYPE_DONT_CARE = 0x0f,
};
enum {
DR_STE_SIZE = 64,
DR_STE_SIZE_CTRL = 32,
DR_STE_SIZE_MATCH_TAG = 32,
DR_STE_SIZE_TAG = 16,
DR_STE_SIZE_MASK = 16,
DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
DR_STE_LOG_SIZE = 6,
};
enum dr_ste_ctx_action_cap {
DR_STE_CTX_ACTION_CAP_NONE = 0,
DR_STE_CTX_ACTION_CAP_TX_POP = 1 << 0,
DR_STE_CTX_ACTION_CAP_RX_PUSH = 1 << 1,
DR_STE_CTX_ACTION_CAP_RX_ENCAP = 1 << 3,
DR_STE_CTX_ACTION_CAP_POP_MDFY = 1 << 4,
DR_STE_CTX_ACTION_CAP_MODIFY_HDR_INLINE = 1 << 5,
};
enum {
DR_MODIFY_ACTION_SIZE = 8,
DR_MODIFY_ACTION_LOG_SIZE = 3,
};
enum dr_matcher_criteria {
DR_MATCHER_CRITERIA_EMPTY = 0,
DR_MATCHER_CRITERIA_OUTER = 1 << 0,
DR_MATCHER_CRITERIA_MISC = 1 << 1,
DR_MATCHER_CRITERIA_INNER = 1 << 2,
DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
DR_MATCHER_CRITERIA_MISC4 = 1 << 5,
DR_MATCHER_CRITERIA_MISC5 = 1 << 6,
DR_MATCHER_CRITERIA_MAX = 1 << 7,
};
enum dr_matcher_definer {
DR_MATCHER_DEFINER_0 = 0,
DR_MATCHER_DEFINER_2 = 2,
DR_MATCHER_DEFINER_6 = 6,
DR_MATCHER_DEFINER_16 = 16,
DR_MATCHER_DEFINER_22 = 22,
DR_MATCHER_DEFINER_24 = 24,
DR_MATCHER_DEFINER_25 = 25,
DR_MATCHER_DEFINER_26 = 26,
DR_MATCHER_DEFINER_28 = 28,
DR_MATCHER_DEFINER_33 = 33,
};
enum dr_action_type {
DR_ACTION_TYP_TNL_L2_TO_L2,
DR_ACTION_TYP_L2_TO_TNL_L2,
DR_ACTION_TYP_TNL_L3_TO_L2,
DR_ACTION_TYP_L2_TO_TNL_L3,
DR_ACTION_TYP_DROP,
DR_ACTION_TYP_QP,
DR_ACTION_TYP_FT,
DR_ACTION_TYP_CTR,
DR_ACTION_TYP_TAG,
DR_ACTION_TYP_MODIFY_HDR,
DR_ACTION_TYP_VPORT,
DR_ACTION_TYP_METER,
DR_ACTION_TYP_MISS,
DR_ACTION_TYP_SAMPLER,
DR_ACTION_TYP_DEST_ARRAY,
DR_ACTION_TYP_POP_VLAN,
DR_ACTION_TYP_PUSH_VLAN,
DR_ACTION_TYP_ASO_FIRST_HIT,
DR_ACTION_TYP_ASO_FLOW_METER,
DR_ACTION_TYP_ASO_CT,
DR_ACTION_TYP_ROOT_FT,
DR_ACTION_TYP_MAX,
};
struct dr_icm_pool;
struct dr_icm_chunk;
struct dr_icm_buddy_mem;
struct dr_ste_htbl;
struct dr_match_param;
struct dr_devx_caps;
struct dr_rule_rx_tx;
struct dr_matcher_rx_tx;
struct dr_ste_ctx;
struct dr_ptrn_mngr;
struct dr_ptrn_obj;
struct dr_arg_mngr;
struct dr_arg_obj;
struct dr_data_seg {
uint64_t addr;
uint32_t length;
uint32_t lkey;
unsigned int send_flags;
};
enum send_info_type {
WRITE_ICM = 0,
GTA_ARG = 1,
};
struct postsend_info {
enum send_info_type type;
struct dr_data_seg write;
struct dr_data_seg read;
uint64_t remote_addr;
uint32_t rkey;
};
struct dr_ste {
uint8_t *hw_ste;
/* refcount: indicates the num of rules that using this ste */
atomic_int refcount;
/* attached to the miss_list head at each htbl entry */
struct list_node miss_list_node;
/* this ste is member of htbl */
struct dr_ste_htbl *htbl;
struct dr_ste_htbl *next_htbl;
/* The rule this STE belongs to */
struct dr_rule_rx_tx *rule_rx_tx;
/* this ste is part of a rule, located in ste's chain */
uint8_t ste_chain_location;
uint8_t size;
};
struct dr_ste_htbl_ctrl {
/* total number of valid entries belonging to this hash table. This
* includes the non collision and collision entries
*/
int num_of_valid_entries;
/* total number of collisions entries attached to this table */
int num_of_collisions;
};
enum dr_ste_htbl_type {
DR_STE_HTBL_TYPE_LEGACY = 0,
DR_STE_HTBL_TYPE_MATCH = 1,
};
struct dr_ste_htbl {
enum dr_ste_htbl_type type;
uint16_t lu_type;
uint16_t byte_mask;
atomic_int refcount;
struct dr_icm_chunk *chunk;
struct dr_ste *ste_arr;
uint8_t *hw_ste_arr;
struct list_head *miss_list;
enum dr_icm_chunk_size chunk_size;
struct dr_ste *pointing_ste;
struct dr_ste_htbl_ctrl ctrl;
};
struct dr_ste_send_info {
struct dr_ste *ste;
struct list_node send_list;
uint16_t size;
uint16_t offset;
uint8_t data_cont[DR_STE_SIZE];
uint8_t *data;
};
void dr_send_fill_and_append_ste_send_info(struct dr_ste *ste, uint16_t size,
uint16_t offset, uint8_t *data,
struct dr_ste_send_info *ste_info,
struct list_head *send_list,
bool copy_data);
struct dr_ste_build {
bool inner;
bool rx;
struct dr_devx_caps *caps;
uint16_t lu_type;
enum dr_ste_htbl_type htbl_type;
union {
struct {
uint16_t byte_mask;
uint8_t bit_mask[DR_STE_SIZE_MASK];
};
struct {
uint16_t format_id;
uint8_t match[DR_STE_SIZE_MATCH_TAG];
struct mlx5dv_devx_obj *definer_obj;
};
};
int (*ste_build_tag_func)(struct dr_match_param *spec,
struct dr_ste_build *sb,
uint8_t *tag);
};
struct dr_ste_htbl *dr_ste_htbl_alloc(struct dr_icm_pool *pool,
enum dr_icm_chunk_size chunk_size,
enum dr_ste_htbl_type type,
uint16_t lu_type, uint16_t byte_mask);
int dr_ste_htbl_free(struct dr_ste_htbl *htbl);
static inline void dr_htbl_put(struct dr_ste_htbl *htbl)
{
if (atomic_fetch_sub(&htbl->refcount, 1) == 1)
dr_ste_htbl_free(htbl);
}
static inline void dr_htbl_get(struct dr_ste_htbl *htbl)
{
atomic_fetch_add(&htbl->refcount, 1);
}
/* STE utils */
uint32_t dr_ste_calc_hash_index(uint8_t *hw_ste_p, struct dr_ste_htbl *htbl);
void dr_ste_set_miss_addr(struct dr_ste_ctx *ste_ctx, uint8_t *hw_ste_p,
uint64_t miss_addr);
void dr_ste_set_hit_addr_by_next_htbl(struct dr_ste_ctx *ste_ctx,
uint8_t *hw_ste,
struct dr_ste_htbl *next_htbl);
void dr_ste_set_hit_addr(struct dr_ste_ctx *ste_ctx, uint8_t *hw_ste_p,
uint64_t icm_addr, uint32_t ht_size);
void dr_ste_set_hit_gvmi(struct dr_ste_ctx *ste_ctx, uint8_t *hw_ste_p,
uint16_t gvmi);
void dr_ste_set_bit_mask(uint8_t *hw_ste_p, struct dr_ste_build *sb);
bool dr_ste_is_last_in_rule(struct dr_matcher_rx_tx *nic_matcher,
uint8_t ste_location);
uint64_t dr_ste_get_icm_addr(struct dr_ste *ste);
uint64_t dr_ste_get_mr_addr(struct dr_ste *ste);
struct list_head *dr_ste_get_miss_list(struct dr_ste *ste);
struct dr_ste *dr_ste_get_miss_list_top(struct dr_ste *ste);
static inline int dr_ste_tag_sz(struct dr_ste *ste)
{
if (ste->htbl->type == DR_STE_HTBL_TYPE_LEGACY)
return DR_STE_SIZE_TAG;
return DR_STE_SIZE_MATCH_TAG;
}
#define MAX_VLANS 2
struct dr_aso_cross_dmn_arrays {
struct dr_ste_htbl **action_htbl;
struct dr_ste_htbl **rule_htbl;
};
struct dr_action_aso {
struct mlx5dv_dr_domain *dmn;
struct mlx5dv_devx_obj *devx_obj;
uint32_t offset;
uint8_t dest_reg_id;
union {
struct {
bool set;
} first_hit;
struct {
uint8_t initial_color;
} flow_meter;
struct {
bool direction;
} ct;
};
};
#define DR_INVALID_PATTERN_INDEX 0xffffffff
struct dr_ste_actions_attr {
uint32_t modify_index;
uint32_t modify_pat_idx;
uint16_t modify_actions;
uint8_t *single_modify_action;
uint32_t decap_index;
uint32_t decap_pat_idx;
uint16_t decap_actions;
bool decap_with_vlan;
uint64_t final_icm_addr;
uint32_t flow_tag;
uint32_t ctr_id;
uint16_t gvmi;
uint16_t hit_gvmi;
uint32_t reformat_id;
uint32_t reformat_size;
bool prio_tag_required;
struct {
int count_pop;
int count_push;
uint32_t headers[MAX_VLANS];
} vlans;
struct dr_action_aso *aso;
uint32_t aso_ste_loc;
struct mlx5dv_dr_domain *dmn;
};
struct cross_dmn_params {
uint32_t cross_dmn_loc;
struct mlx5dv_dr_action *cross_dmn_action;
};
void dr_ste_set_actions_rx(struct dr_ste_ctx *ste_ctx,
uint8_t *action_type_set,
uint8_t *last_ste,
struct dr_ste_actions_attr *attr,
uint32_t *added_stes);
void dr_ste_set_actions_tx(struct dr_ste_ctx *ste_ctx,
uint8_t *action_type_set,
uint8_t *last_ste,
struct dr_ste_actions_attr *attr,
uint32_t *added_stes);
void dr_ste_set_action_set(struct dr_ste_ctx *ste_ctx,
__be64 *hw_action,
uint8_t hw_field,
uint8_t shifter,
uint8_t length,
uint32_t data);
void dr_ste_set_action_add(struct dr_ste_ctx *ste_ctx,
__be64 *hw_action,
uint8_t hw_field,
uint8_t shifter,
uint8_t length,
uint32_t data);
void dr_ste_set_action_copy(struct dr_ste_ctx *ste_ctx,
__be64 *hw_action,
uint8_t dst_hw_field,
uint8_t dst_shifter,
uint8_t dst_len,
uint8_t src_hw_field,
uint8_t src_shifter);
int dr_ste_set_action_decap_l3_list(struct dr_ste_ctx *ste_ctx,
void *data, uint32_t data_sz,
uint8_t *hw_action, uint32_t hw_action_sz,
uint16_t *used_hw_action_num);
void dr_ste_v1_set_aso_ct(uint8_t *d_action,
uint32_t object_id,
uint32_t offset,
uint8_t dest_reg_id,
bool direction);
const struct dr_ste_action_modify_field *
dr_ste_conv_modify_hdr_sw_field(struct dr_ste_ctx *ste_ctx,
struct dr_devx_caps *caps,
uint16_t sw_field);
struct dr_ste_ctx *dr_ste_get_ctx(uint8_t version);
void dr_ste_free(struct dr_ste *ste,
struct mlx5dv_dr_rule *rule,
struct dr_rule_rx_tx *nic_rule);
static inline void dr_ste_put(struct dr_ste *ste,
struct mlx5dv_dr_rule *rule,
struct dr_rule_rx_tx *nic_rule)
{
if (atomic_fetch_sub(&ste->refcount, 1) == 1)
dr_ste_free(ste, rule, nic_rule);
}
/* initial as 0, increased only when ste appears in a new rule */
static inline void dr_ste_get(struct dr_ste *ste)
{
atomic_fetch_add(&ste->refcount, 1);
}
static inline bool dr_ste_is_not_used(struct dr_ste *ste)
{
return !atomic_load(&ste->refcount);
}
bool dr_ste_equal_tag(void *src, void *dst, uint8_t tag_size);
int dr_ste_create_next_htbl(struct mlx5dv_dr_matcher *matcher,
struct dr_matcher_rx_tx *nic_matcher,
struct dr_ste *ste,
uint8_t *cur_hw_ste,
enum dr_icm_chunk_size log_table_size,
uint8_t send_ring_idx);
/* STE build functions */
int dr_ste_build_pre_check(struct mlx5dv_dr_domain *dmn,
uint8_t match_criteria,
struct dr_match_param *mask,
struct dr_match_param *value);
int dr_ste_build_ste_arr(struct mlx5dv_dr_matcher *matcher,
struct dr_matcher_rx_tx *nic_matcher,
struct dr_match_param *value,
uint8_t *ste_arr);
void dr_ste_build_eth_l2_src_dst(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l3_ipv4_5_tuple(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l3_ipv4_misc(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l3_ipv6_dst(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l3_ipv6_src(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l2_src(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l2_dst(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l2_tnl(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_ipv6_l3_l4(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_eth_l4_misc(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_tnl_gre(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_mpls(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_tnl_mpls_over_gre(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_tnl_mpls_over_udp(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_icmp(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_tnl_vxlan_gpe(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_tnl_geneve(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_tnl_geneve_tlv_opt(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_tnl_geneve_tlv_opt_exist(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_tnl_gtpu(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_tnl_gtpu_flex_parser_0(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_tnl_gtpu_flex_parser_1(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_general_purpose(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_register_0(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_register_1(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_src_gvmi_qpn(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_flex_parser_0(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_flex_parser_1(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_tunnel_header(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
void dr_ste_build_ib_l4(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def0(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
int dr_ste_build_def2(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
int dr_ste_build_def6(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def16(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
struct dr_devx_caps *caps,
bool inner, bool rx);
int dr_ste_build_def22(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def24(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def25(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def26(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def28(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
int dr_ste_build_def33(struct dr_ste_ctx *ste_ctx,
struct dr_ste_build *sb,
struct dr_match_param *mask,
bool inner, bool rx);
void dr_ste_build_empty_always_hit(struct dr_ste_build *sb, bool rx);
/* Actions utils */
int dr_actions_build_ste_arr(struct mlx5dv_dr_matcher *matcher,
struct dr_matcher_rx_tx *nic_matcher,
struct mlx5dv_dr_action *actions[],
uint32_t num_actions,
uint8_t *ste_arr,
uint32_t *new_hw_ste_arr_sz,
struct cross_dmn_params *cross_dmn_p,
uint8_t send_ring_idx);
int dr_actions_build_attr(struct mlx5dv_dr_matcher *matcher,
struct mlx5dv_dr_action *actions[],
size_t num_actions,
struct mlx5dv_flow_action_attr *attr,
struct mlx5_flow_action_attr_aux *attr_aux);
struct dr_match_spec {
uint32_t smac_47_16; /* Source MAC address of incoming packet */
uint32_t smac_15_0:16; /* Source MAC address of incoming packet */
uint32_t ethertype:16; /* Incoming packet Ethertype - this is the Ethertype following the last ;VLAN tag of the packet */
uint32_t dmac_47_16; /* Destination MAC address of incoming packet */
uint32_t dmac_15_0:16; /* Destination MAC address of incoming packet */
uint32_t first_prio:3; /* Priority of first VLAN tag in the incoming packet. Valid only when ;cvlan_tag==1 or svlan_tag==1 */
uint32_t first_cfi:1; /* CFI bit of first VLAN tag in the incoming packet. Valid only when ;cvlan_tag==1 or svlan_tag==1 */
uint32_t first_vid:12; /* VLAN ID of first VLAN tag in the incoming packet. Valid only ;when cvlan_tag==1 or svlan_tag==1 */
uint32_t ip_protocol:8; /* IP protocol */
uint32_t ip_dscp:6; /* Differentiated Services Code Point derived from Traffic Class/;TOS field of IPv6/v4 */
uint32_t ip_ecn:2; /* Explicit Congestion Notification derived from Traffic Class/TOS ;field of IPv6/v4 */
uint32_t cvlan_tag:1; /* The first vlan in the packet is c-vlan (0x8100). cvlan_tag and ;svlan_tag cannot be set together */
uint32_t svlan_tag:1; /* The first vlan in the packet is s-vlan (0x8a88). cvlan_tag and ;svlan_tag cannot be set together */
uint32_t frag:1; /* Packet is an IP fragment */
uint32_t ip_version:4; /* IP version */
uint32_t tcp_flags:9; /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK;Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS */
uint32_t tcp_sport:16; /* TCP source port.;tcp and udp sport/dport are mutually exclusive */
uint32_t tcp_dport:16; /* TCP destination port. ;tcp and udp sport/dport are mutually exclusive */
uint32_t reserved_at_c0:16;
uint32_t ipv4_ihl:4;
uint32_t l3_ok:1;
uint32_t l4_ok:1;
uint32_t ipv4_checksum_ok:1;
uint32_t l4_checksum_ok:1;
uint32_t ip_ttl_hoplimit:8;
uint32_t udp_sport:16; /* UDP source port.;tcp and udp sport/dport are mutually exclusive */
uint32_t udp_dport:16; /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */
uint32_t src_ip_127_96; /* IPv6 source address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t src_ip_95_64; /* IPv6 source address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t src_ip_63_32; /* IPv6 source address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t src_ip_31_0; /* IPv6 source address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t dst_ip_127_96; /* IPv6 destination address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t dst_ip_95_64; /* IPv6 destination address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t dst_ip_63_32; /* IPv6 destination address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
uint32_t dst_ip_31_0; /* IPv6 destination address of incoming packets ;For IPv4 address use bits 31:0 (rest of the bits are reserved);This field should be qualified by an appropriate ;ethertype */
};
struct dr_match_misc {
uint32_t gre_c_present:1; /* used with GRE, checksum exist when gre_c_present == 1 */
uint32_t bth_a:1;
uint32_t gre_k_present:1; /* used with GRE, key exist when gre_k_present == 1 */
uint32_t gre_s_present:1; /* used with GRE, sequence number exist when gre_s_present == 1 */
uint32_t source_vhca_port:4;
uint32_t source_sqn:24; /* Source SQN */
uint32_t source_eswitch_owner_vhca_id:16;
uint32_t source_port:16; /* Source port.;0xffff determines wire port */
uint32_t outer_second_prio:3; /* Priority of second VLAN tag in the outer header of the incoming ;packet. Valid only when outer_second_cvlan_tag ==1 or outer_sec;ond_svlan_tag ==1 */
uint32_t outer_second_cfi:1; /* CFI bit of first VLAN tag in the outer header of the incoming packet. ;Valid only when outer_second_cvlan_tag ==1 or outer_sec;ond_svlan_tag ==1 */
uint32_t outer_second_vid:12; /* VLAN ID of first VLAN tag the outer header of the incoming packet. ;Valid only when outer_second_cvlan_tag ==1 or outer_sec;ond_svlan_tag ==1 */
uint32_t inner_second_prio:3; /* Priority of second VLAN tag in the inner header of the incoming ;packet. Valid only when inner_second_cvlan_tag ==1 or inner_sec;ond_svlan_tag ==1 */
uint32_t inner_second_cfi:1; /* CFI bit of first VLAN tag in the inner header of the incoming packet. ;Valid only when inner_second_cvlan_tag ==1 or inner_sec;ond_svlan_tag ==1 */
uint32_t inner_second_vid:12; /* VLAN ID of first VLAN tag the inner header of the incoming packet. ;Valid only when inner_second_cvlan_tag ==1 or inner_sec;ond_svlan_tag ==1 */
uint32_t outer_second_cvlan_tag:1; /* The second vlan in the outer header of the packet is c-vlan (0x8100). ;outer_second_cvlan_tag and outer_second_svlan_tag cannot be set ;together */
uint32_t inner_second_cvlan_tag:1; /* The second vlan in the inner header of the packet is c-vlan (0x8100). ;inner_second_cvlan_tag and inner_second_svlan_tag cannot be set ;together */
uint32_t outer_second_svlan_tag:1; /* The second vlan in the outer header of the packet is s-vlan (0x8a88). ;outer_second_cvlan_tag and outer_second_svlan_tag cannot be set ;together */
uint32_t inner_second_svlan_tag:1; /* The second vlan in the inner header of the packet is s-vlan (0x8a88). ;inner_second_cvlan_tag and inner_second_svlan_tag cannot be set ;together */
uint32_t outer_emd_tag:1;
uint32_t reserved_at_65:11;
uint32_t gre_protocol:16; /* GRE Protocol (outer) */
uint32_t gre_key_h:24; /* GRE Key[31:8] (outer) */
uint32_t gre_key_l:8; /* GRE Key [7:0] (outer) */
uint32_t vxlan_vni:24; /* VXLAN VNI (outer) */
uint32_t bth_opcode:8; /* Opcode field from BTH header */
uint32_t geneve_vni:24; /* GENEVE VNI field (outer) */
uint32_t reserved_at_e4:6;
uint32_t geneve_tlv_option_0_exist:1;
uint32_t geneve_oam:1; /* GENEVE OAM field (outer) */
uint32_t reserved_at_ec:12;
uint32_t outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */
uint32_t reserved_at_100:12;
uint32_t inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */
uint32_t reserved_at_120:10;
uint32_t geneve_opt_len:6; /* GENEVE OptLen (outer) */
uint32_t geneve_protocol_type:16; /* GENEVE protocol type (outer) */
uint32_t reserved_at_140:8;
uint32_t bth_dst_qp:24; /* Destination QP in BTH header */
uint32_t inner_esp_spi;
uint32_t outer_esp_spi;
uint32_t reserved_at_1a0;
uint32_t reserved_at_1c0;
uint32_t reserved_at_1e0;
};
struct dr_match_misc2 {
uint32_t outer_first_mpls_label:20; /* First MPLS LABEL (outer) */
uint32_t outer_first_mpls_exp:3; /* First MPLS EXP (outer) */
uint32_t outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */
uint32_t outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */
uint32_t inner_first_mpls_label:20; /* First MPLS LABEL (inner) */
uint32_t inner_first_mpls_exp:3; /* First MPLS EXP (inner) */
uint32_t inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */
uint32_t inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */
uint32_t outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */
uint32_t outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */
uint32_t outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */
uint32_t outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */
uint32_t outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */
uint32_t outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */
uint32_t outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */
uint32_t outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */
uint32_t metadata_reg_c_7; /* metadata_reg_c_7 */
uint32_t metadata_reg_c_6; /* metadata_reg_c_6 */
uint32_t metadata_reg_c_5; /* metadata_reg_c_5 */
uint32_t metadata_reg_c_4; /* metadata_reg_c_4 */
uint32_t metadata_reg_c_3; /* metadata_reg_c_3 */
uint32_t metadata_reg_c_2; /* metadata_reg_c_2 */
uint32_t metadata_reg_c_1; /* metadata_reg_c_1 */
uint32_t metadata_reg_c_0; /* metadata_reg_c_0 */
uint32_t metadata_reg_a; /* metadata_reg_a */
uint32_t reserved_at_1a0;
uint32_t reserved_at_1c0;
uint32_t reserved_at_1e0;
};
struct dr_match_misc3 {
uint32_t inner_tcp_seq_num;
uint32_t outer_tcp_seq_num;
uint32_t inner_tcp_ack_num;
uint32_t outer_tcp_ack_num;
uint32_t reserved_at_80:8;
uint32_t outer_vxlan_gpe_vni:24;
uint32_t outer_vxlan_gpe_next_protocol:8;
uint32_t outer_vxlan_gpe_flags:8;
uint32_t reserved_at_b0:16;
uint32_t icmpv4_header_data;
uint32_t icmpv6_header_data;
uint8_t icmpv4_type;
uint8_t icmpv4_code;
uint8_t icmpv6_type;
uint8_t icmpv6_code;
uint32_t geneve_tlv_option_0_data;
uint32_t gtpu_teid;
uint32_t gtpu_msg_type:8;
uint32_t gtpu_msg_flags:8;
uint32_t reserved_at_170:16;
uint32_t gtpu_dw_2;
uint32_t gtpu_first_ext_dw_0;
uint32_t gtpu_dw_0;
uint32_t reserved_at_1e0;
};
struct dr_match_misc4 {
uint32_t prog_sample_field_value_0;
uint32_t prog_sample_field_id_0;
uint32_t prog_sample_field_value_1;
uint32_t prog_sample_field_id_1;
uint32_t prog_sample_field_value_2;
uint32_t prog_sample_field_id_2;
uint32_t prog_sample_field_value_3;
uint32_t prog_sample_field_id_3;
uint32_t prog_sample_field_value_4;
uint32_t prog_sample_field_id_4;
uint32_t prog_sample_field_value_5;
uint32_t prog_sample_field_id_5;
uint32_t prog_sample_field_value_6;
uint32_t prog_sample_field_id_6;
uint32_t prog_sample_field_value_7;
uint32_t prog_sample_field_id_7;
};
struct dr_match_misc5 {
uint32_t macsec_tag_0;
uint32_t macsec_tag_1;
uint32_t macsec_tag_2;
uint32_t macsec_tag_3;
uint32_t tunnel_header_0;
uint32_t tunnel_header_1;
uint32_t tunnel_header_2;
uint32_t tunnel_header_3;
uint32_t reserved_at_100;
uint32_t reserved_at_120;
uint32_t reserved_at_140;
uint32_t reserved_at_160;
uint32_t reserved_at_180;
uint32_t reserved_at_1a0;
uint32_t reserved_at_1c0;
uint32_t reserved_at_1e0;
};
struct dr_match_param {
struct dr_match_spec outer;
struct dr_match_misc misc;
struct dr_match_spec inner;
struct dr_match_misc2 misc2;
struct dr_match_misc3 misc3;
struct dr_match_misc4 misc4;
struct dr_match_misc5 misc5;
};
#define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \
(_misc3)->icmpv4_code || \
(_misc3)->icmpv4_header_data)
struct dr_esw_caps {
uint64_t drop_icm_address_rx;
uint64_t drop_icm_address_tx;
uint64_t uplink_icm_address_rx;
uint64_t uplink_icm_address_tx;
bool sw_owner;
bool sw_owner_v2;
};
struct dr_devx_vport_cap {
uint16_t vport_gvmi;
uint16_t vhca_gvmi;
uint64_t icm_address_rx;
uint64_t icm_address_tx;
uint16_t num;
uint32_t metadata_c;
uint32_t metadata_c_mask;
/* locate vports table */
struct dr_devx_vport_cap *next;
};
struct dr_devx_roce_cap {
bool roce_en;
bool fl_rc_qp_when_roce_disabled;
bool fl_rc_qp_when_roce_enabled;
uint8_t qp_ts_format;
};
struct dr_vports_table {
struct dr_devx_vport_cap *buckets[DR_VPORTS_BUCKETS];
};
struct dr_devx_vports {
/* E-Switch manager */
struct dr_devx_vport_cap esw_mngr;
/* Uplink */
struct dr_devx_vport_cap wire;
/* PF + VFS + SF */
struct dr_vports_table *vports;
/* IB ports to vport + other_vports */
struct dr_devx_vport_cap **ib_ports;
/* Number of vports PF + VFS + SFS + WIRE */
uint32_t num_ports;
/* Protect vport query and add*/
pthread_spinlock_t lock;
};
struct dr_devx_caps {
struct mlx5dv_dr_domain *dmn;
uint16_t gvmi;
uint64_t nic_rx_drop_address;
uint64_t nic_tx_drop_address;
uint64_t nic_tx_allow_address;
uint64_t esw_rx_drop_address;
uint64_t esw_tx_drop_address;
uint32_t log_icm_size;
uint8_t log_modify_hdr_icm_size;
uint64_t hdr_modify_icm_addr;
uint32_t log_modify_pattern_icm_size;
uint64_t hdr_modify_pattern_icm_addr;
uint32_t flex_protocols;
uint8_t flex_parser_header_modify;
uint8_t flex_parser_id_icmp_dw0;
uint8_t flex_parser_id_icmp_dw1;
uint8_t flex_parser_id_icmpv6_dw0;
uint8_t flex_parser_id_icmpv6_dw1;
uint8_t flex_parser_id_geneve_opt_0;
uint8_t flex_parser_id_mpls_over_gre;
uint8_t flex_parser_id_mpls_over_udp;
uint8_t flex_parser_id_gtpu_dw_0;
uint8_t flex_parser_id_gtpu_teid;
uint8_t flex_parser_id_gtpu_dw_2;
uint8_t flex_parser_id_gtpu_first_ext_dw_0;
uint8_t flex_parser_ok_bits_supp;
uint8_t definer_supp_checksum;
uint8_t max_ft_level;
uint8_t sw_format_ver;
bool isolate_vl_tc;
bool eswitch_manager;
bool rx_sw_owner;
bool tx_sw_owner;
bool fdb_sw_owner;
bool rx_sw_owner_v2;
bool tx_sw_owner_v2;
bool fdb_sw_owner_v2;
struct dr_devx_roce_cap roce_caps;
uint64_t definer_format_sup;
uint16_t log_header_modify_argument_granularity;
uint16_t log_header_modify_argument_max_alloc;
bool support_modify_argument;
bool prio_tag_required;
bool is_ecpf;
struct dr_devx_vports vports;
bool support_full_tnl_hdr;
};
struct dr_devx_flow_table_attr {
uint8_t type;
uint8_t level;
bool sw_owner;
bool term_tbl;
bool reformat_en;
uint64_t icm_addr_rx;
uint64_t icm_addr_tx;
};
struct dr_devx_flow_group_attr {
uint32_t table_id;
uint32_t table_type;
};
struct dr_devx_flow_dest_info {
enum dr_devx_flow_dest_type type;
union {
uint32_t vport_num;
uint32_t tir_num;