{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":64907432,"defaultBranch":"riscv-gcc-9.2.0","name":"riscv-gcc","ownerLogin":"kito-cheng","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2016-08-04T06:11:20.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/2723185?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1696872977.0","currentOid":""},"activityList":{"items":[{"before":"d2cd2e16c59ddd713619e816ff9702e600b4bea7","after":"291c93ae610c98ca73eaa2158e6d05dc434d3948","ref":"refs/heads/kitoc/target-attr","pushedAt":"2023-10-10T04:11:03.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kito-cheng","name":"Kito Cheng","path":"/kito-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2723185?s=80&v=4"},"commit":{"message":"RISC-V: Implement target attribute\n\nThe target attribute which proposed in [1], target attribute allow user\nto specify a local setting per-function basis.\n\nThe syntax of target attribute is `__attribute__((target(\"<ATTR-STRING>\")))`.\n\nand the syntax of `<ATTR-STRING>` describes below:\n```\nATTR-STRING := ATTR-STRING ';' ATTR\n             | ATTR\n\nATTR        := ARCH-ATTR\n             | CPU-ATTR\n             | TUNE-ATTR\n\nARCH-ATTR   := 'arch=' EXTENSIONS-OR-FULLARCH\n\nEXTENSIONS-OR-FULLARCH := <EXTENSIONS>\n                        | <FULLARCHSTR>\n\nEXTENSIONS             := <EXTENSION> ',' <EXTENSIONS>\n                        | <EXTENSION>\n\nFULLARCHSTR            := <full-arch-string>\n\nEXTENSION              := <OP> <EXTENSION-NAME> <VERSION>\n\nOP                     := '+'\n\nVERSION                := [0-9]+ 'p' [0-9]+\n                        | [1-9][0-9]*\n                        |\n\nEXTENSION-NAME         := Naming rule is defined in RISC-V ISA manual\n\nCPU-ATTR    := 'cpu=' <valid-cpu-name>\nTUNE-ATTR   := 'tune=' <valid-tune-name>\n```\n\n[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35\n\ngcc/ChangeLog:\n\n\t* config.gcc (riscv): Add riscv-target-attr.o.\n\t* config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New.\n\t* config/riscv/riscv-protos.h (riscv_declare_function_size) New.\n\t(riscv_option_valid_attribute_p): New.\n\t(riscv_override_options_internal): New.\n\t(struct riscv_tune_info): New.\n\t(riscv_parse_tune): New.\n\t* config/riscv/riscv-target-attr.cc\n\t(class riscv_target_attr_parser): New.\n\t(struct riscv_attribute_info): New.\n\t(riscv_attributes): New.\n\t(riscv_target_attr_parser::parse_arch):\n\t(riscv_target_attr_parser::handle_arch):\n\t(riscv_target_attr_parser::handle_cpu):\n\t(riscv_target_attr_parser::handle_tune):\n\t(riscv_target_attr_parser::update_settings):\n\t(riscv_process_one_target_attr):\n\t(num_occurences_in_str):\n\t(riscv_process_target_attr):\n\t(riscv_option_valid_attribute_p):\n\t* config/riscv/riscv.cc: Include target-globals.h and\n\triscv-subset.h.\n\t(struct riscv_tune_info): Move to riscv-protos.h.\n\t(get_tune_str):\n\t(riscv_parse_tune):\n\t(riscv_declare_function_size):\n\t(riscv_option_override): Build target_option_default_node and\n\ttarget_option_current_node.\n\t(riscv_save_restore_target_globals):\n\t(riscv_option_restore):\n\t(riscv_previous_fndecl):\n\t(riscv_set_current_function): Apply the target attribute.\n\t(TARGET_OPTION_RESTORE): Define.\n\t(TARGET_OPTION_VALID_ATTRIBUTE_P): Ditto.\n\t* config/riscv/riscv.h (SWITCHABLE_TARGET): Define to 1.\n\t(ASM_DECLARE_FUNCTION_SIZE) Define.\n\t* config/riscv/riscv.opt (mtune=): Add Save attribute.\n\t(mcpu=): Ditto.\n\t(mcmodel=): Ditto.\n\t* config/riscv/t-riscv: Add build rule for riscv-target-attr.o\n\t* doc/extend.texi: Add doc for target attribute.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/target-attr-01.c: New.\n\t* gcc.target/riscv/target-attr-02.c: Ditto.\n\t* gcc.target/riscv/target-attr-03.c: Ditto.\n\t* gcc.target/riscv/target-attr-04.c: Ditto.\n\t* gcc.target/riscv/target-attr-05.c: Ditto.\n\t* gcc.target/riscv/target-attr-06.c: Ditto.\n\t* gcc.target/riscv/target-attr-07.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-01.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-02.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-03.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-04.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-05.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-06.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-07.c: Ditto.\n\t* gcc.target/riscv/target-attr-warning-01.c: Ditto.\n\t* gcc.target/riscv/target-attr-warning-02.c: Ditto.\n\t* gcc.target/riscv/target-attr-warning-03.c: Ditto.","shortMessageHtmlLink":"RISC-V: Implement target attribute"}},{"before":"476466b95c4b58dff7b3c8c95ab4f4ec6648cb66","after":null,"ref":"refs/heads/riscv-gcc-10.2.0-rvv-cleanup-kito-dev","pushedAt":"2023-10-09T17:36:17.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"kito-cheng","name":"Kito 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                   | <FULLARCHSTR>\n\nEXTENSIONS             := <EXTENSION> ',' <EXTENSIONS>\n                        | <EXTENSION>\n\nFULLARCHSTR            := <full-arch-string>\n\nEXTENSION              := <OP> <EXTENSION-NAME> <VERSION>\n\nOP                     := '+'\n\nVERSION                := [0-9]+ 'p' [0-9]+\n                        | [1-9][0-9]*\n                        |\n\nEXTENSION-NAME         := Naming rule is defined in RISC-V ISA manual\n\nCPU-ATTR    := 'cpu=' <valid-cpu-name>\nTUNE-ATTR   := 'tune=' <valid-tune-name>\n```\n\n[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35\n\ngcc/ChangeLog:\n\n\t* config.gcc (riscv): Add riscv-target-attr.o.\n\t* config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New.\n\t* config/riscv/riscv-protos.h (riscv_declare_function_size) New.\n\t(riscv_option_valid_attribute_p): New.\n\t(riscv_override_options_internal): New.\n\t(struct riscv_tune_info): New.\n\t(riscv_parse_tune): New.\n\t* config/riscv/riscv-target-attr.cc\n\t(class riscv_target_attr_parser): New.\n\t(struct riscv_attribute_info): New.\n\t(riscv_attributes): New.\n\t(riscv_target_attr_parser::parse_arch):\n\t(riscv_target_attr_parser::handle_arch):\n\t(riscv_target_attr_parser::handle_cpu):\n\t(riscv_target_attr_parser::handle_tune):\n\t(riscv_target_attr_parser::update_settings):\n\t(riscv_process_one_target_attr):\n\t(num_occurences_in_str):\n\t(riscv_process_target_attr):\n\t(riscv_option_valid_attribute_p):\n\t* config/riscv/riscv.cc: Include target-globals.h and\n\triscv-subset.h.\n\t(struct riscv_tune_info): Move to riscv-protos.h.\n\t(get_tune_str):\n\t(riscv_parse_tune):\n\t(riscv_declare_function_size):\n\t(riscv_option_override): Build target_option_default_node and\n\ttarget_option_current_node.\n\t(riscv_save_restore_target_globals):\n\t(riscv_option_restore):\n\t(riscv_previous_fndecl):\n\t(riscv_set_current_function): Apply the target attribute.\n\t(TARGET_OPTION_RESTORE): Define.\n\t(TARGET_OPTION_VALID_ATTRIBUTE_P): Ditto.\n\t* config/riscv/riscv.h (SWITCHABLE_TARGET): Define to 1.\n\t(ASM_DECLARE_FUNCTION_SIZE) Define.\n\t* config/riscv/riscv.opt (mtune=): Add Save attribute.\n\t(mcpu=): Ditto.\n\t(mcmodel=): Ditto.\n\t* config/riscv/t-riscv: Add build rule for riscv-target-attr.o\n\t* doc/extend.texi: Add doc for target attribute.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/target-attr-01.c: New.\n\t* gcc.target/riscv/target-attr-02.c: Ditto.\n\t* gcc.target/riscv/target-attr-03.c: Ditto.\n\t* gcc.target/riscv/target-attr-04.c: Ditto.\n\t* gcc.target/riscv/target-attr-05.c: Ditto.\n\t* gcc.target/riscv/target-attr-06.c: Ditto.\n\t* gcc.target/riscv/target-attr-07.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-01.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-02.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-03.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-04.c: Ditto.\n\t* gcc.target/riscv/target-attr-bad-05.c: Ditto.\n\t* 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