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rtw8852a_rfk.c
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rtw8852a_rfk.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "coex.h"
#include "debug.h"
#include "mac.h"
#include "phy.h"
#include "reg.h"
#include "rtw8852a.h"
#include "rtw8852a_rfk.h"
#include "rtw8852a_rfk_table.h"
#include "rtw8852a_table.h"
static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n",
rtwdev->dbcc_en, phy_idx);
if (!rtwdev->dbcc_en)
return RF_AB;
if (phy_idx == RTW89_PHY_0)
return RF_A;
else
return RF_B;
}
static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};
static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852a_backup_bb_regs)
#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852a_backup_rf_regs)
static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])
{
u32 i;
for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
backup_bb_reg_val[i] =
rtw89_phy_read32_mask(rtwdev, rtw8852a_backup_bb_regs[i],
MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]backup bb reg : %x, value =%x\n",
rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]);
}
}
static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],
u8 rf_path)
{
u32 i;
for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
backup_rf_reg_val[i] =
rtw89_read_rf(rtwdev, rf_path,
rtw8852a_backup_rf_regs[i], RFREG_MASK);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]backup rf S%d reg : %x, value =%x\n", rf_path,
rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]);
}
}
static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
u32 backup_bb_reg_val[])
{
u32 i;
for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
rtw89_phy_write32_mask(rtwdev, rtw8852a_backup_bb_regs[i],
MASKDWORD, backup_bb_reg_val[i]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]restore bb reg : %x, value =%x\n",
rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]);
}
}
static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
u32 backup_rf_reg_val[], u8 rf_path)
{
u32 i;
for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
rtw89_write_rf(rtwdev, rf_path, rtw8852a_backup_rf_regs[i],
RFREG_MASK, backup_rf_reg_val[i]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]restore rf S%d reg: %x, value =%x\n", rf_path,
rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]);
}
}
static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
{
u8 path;
u32 rf_mode;
int ret;
for (path = 0; path < RF_PATH_MAX; path++) {
if (!(kpath & BIT(path)))
continue;
ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
2, 5000, false, rtwdev, path, 0x00,
RR_MOD_MASK);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
path, ret);
}
}
static void _dack_dump(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u8 i;
u8 t;
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
dack->addck_d[0][0], dack->addck_d[0][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
dack->addck_d[1][0], dack->addck_d[1][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
dack->dadck_d[0][0], dack->dadck_d[0][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
dack->dadck_d[1][0], dack->dadck_d[1][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
dack->biask_d[0][0], dack->biask_d[0][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
dack->biask_d[1][0], dack->biask_d[1][1]);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[0][0][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[0][1][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[1][0][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
t = dack->msbk_d[1][1][i];
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
}
}
static void _afe_init(struct rtw89_dev *rtwdev)
{
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_afe_init_defs_tbl);
}
static void _addck_backup(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
rtw89_phy_write32_clr(rtwdev, R_S0_RXDC2, B_S0_RXDC2_SEL);
dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
B_S0_ADDCK_Q);
dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
B_S0_ADDCK_I);
rtw89_phy_write32_clr(rtwdev, R_S1_RXDC2, B_S1_RXDC2_SEL);
dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
B_S1_ADDCK_Q);
dack->addck_d[1][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
B_S1_ADDCK_I);
}
static void _addck_reload(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]);
rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2, B_S0_RXDC2_Q2,
(dack->addck_d[0][1] >> 6));
rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_Q,
(dack->addck_d[0][1] & 0x3f));
rtw89_phy_write32_set(rtwdev, R_S0_RXDC2, B_S0_RXDC2_MEN);
rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]);
rtw89_phy_write32_mask(rtwdev, R_S1_RXDC2, B_S1_RXDC2_Q2,
(dack->addck_d[1][1] >> 6));
rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_Q,
(dack->addck_d[1][1] & 0x3f));
rtw89_phy_write32_set(rtwdev, R_S1_RXDC2, B_S1_RXDC2_EN);
}
static void _dack_backup_s0(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u8 i;
rtw89_phy_write32_set(rtwdev, R_S0_DACKI, B_S0_DACKI_EN);
rtw89_phy_write32_set(rtwdev, R_S0_DACKQ, B_S0_DACKQ_EN);
rtw89_phy_write32_set(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
rtw89_phy_write32_mask(rtwdev, R_S0_DACKI, B_S0_DACKI_AR, i);
dack->msbk_d[0][0][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI7, B_S0_DACKI7_K);
rtw89_phy_write32_mask(rtwdev, R_S0_DACKQ, B_S0_DACKQ_AR, i);
dack->msbk_d[0][1][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ7, B_S0_DACKQ7_K);
}
dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2,
B_S0_DACKI2_K);
dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2,
B_S0_DACKQ2_K);
dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8,
B_S0_DACKI8_K) - 8;
dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8,
B_S0_DACKQ8_K) - 8;
}
static void _dack_backup_s1(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u8 i;
rtw89_phy_write32_set(rtwdev, R_S1_DACKI, B_S1_DACKI_EN);
rtw89_phy_write32_set(rtwdev, R_S1_DACKQ, B_S1_DACKQ_EN);
rtw89_phy_write32_set(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
rtw89_phy_write32_mask(rtwdev, R_S1_DACKI, B_S1_DACKI_AR, i);
dack->msbk_d[1][0][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI7, B_S1_DACKI_K);
rtw89_phy_write32_mask(rtwdev, R_S1_DACKQ, B_S1_DACKQ_AR, i);
dack->msbk_d[1][1][i] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ7, B_S1_DACKQ7_K);
}
dack->biask_d[1][0] =
(u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI2, B_S1_DACKI2_K);
dack->biask_d[1][1] =
(u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ2, B_S1_DACKQ2_K);
dack->dadck_d[1][0] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI8, B_S1_DACKI8_K) - 8;
dack->dadck_d[1][1] =
(u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ8, B_S1_DACKQ8_K) - 8;
}
static void _dack_reload_by_path(struct rtw89_dev *rtwdev,
enum rtw89_rf_path path, u8 index)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 tmp = 0, tmp_offset, tmp_reg;
u8 i;
u32 idx_offset, path_offset;
if (index == 0)
idx_offset = 0;
else
idx_offset = 0x50;
if (path == RF_PATH_A)
path_offset = 0;
else
path_offset = 0x2000;
tmp_offset = idx_offset + path_offset;
/* msbk_d: 15/14/13/12 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
tmp_reg = 0x5e14 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* msbk_d: 11/10/9/8 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
tmp_reg = 0x5e18 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* msbk_d: 7/6/5/4 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
tmp_reg = 0x5e1c + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* msbk_d: 3/2/1/0 */
tmp = 0x0;
for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
tmp |= dack->msbk_d[path][index][i] << (i * 8);
tmp_reg = 0x5e20 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD));
/* dadak_d/biask_d */
tmp = 0x0;
tmp = (dack->biask_d[path][index] << 22) |
(dack->dadck_d[path][index] << 14);
tmp_reg = 0x5e24 + tmp_offset;
rtw89_phy_write32(rtwdev, tmp_reg, tmp);
}
static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
u8 i;
for (i = 0; i < 2; i++)
_dack_reload_by_path(rtwdev, path, i);
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_dack_reload_defs_a_tbl,
&rtw8852a_rfk_dack_reload_defs_b_tbl);
}
#define ADDC_T_AVG 100
static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
s32 dc_re = 0, dc_im = 0;
u32 tmp;
u32 i;
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_check_addc_defs_a_tbl,
&rtw8852a_rfk_check_addc_defs_b_tbl);
for (i = 0; i < ADDC_T_AVG; i++) {
tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD);
dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);
dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);
}
dc_re /= ADDC_T_AVG;
dc_im /= ADDC_T_AVG;
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
}
static void _addck(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 val;
int ret;
/* S0 */
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_a_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n");
_check_addc(rtwdev, RF_PATH_A);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_a_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x1e00, BIT(0));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
dack->addck_timeout[0] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n");
_check_addc(rtwdev, RF_PATH_A);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_a_tbl);
/* S1 */
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_b_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n");
_check_addc(rtwdev, RF_PATH_B);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_b_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x3e00, BIT(0));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
dack->addck_timeout[1] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n");
_check_addc(rtwdev, RF_PATH_B);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_b_tbl);
}
static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_check_dadc_defs_f_a_tbl,
&rtw8852a_rfk_check_dadc_defs_f_b_tbl);
_check_addc(rtwdev, path);
rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
&rtw8852a_rfk_check_dadc_defs_r_a_tbl,
&rtw8852a_rfk_check_dadc_defs_r_b_tbl);
}
static void _dack_s0(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 val;
int ret;
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_a_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e28, BIT(15));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e78, BIT(15));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n");
dack->msbk_timeout[0] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_a_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e48, BIT(17));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x5e98, BIT(17));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADACK timeout\n");
dack->dadck_timeout[0] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_a_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
_check_dadc(rtwdev, RF_PATH_A);
_dack_backup_s0(rtwdev);
_dack_reload(rtwdev, RF_PATH_A);
rtw89_phy_write32_clr(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG);
}
static void _dack_s1(struct rtw89_dev *rtwdev)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 val;
int ret;
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_b_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e28, BIT(15));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e78, BIT(15));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n");
dack->msbk_timeout[1] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_b_tbl);
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e48, BIT(17));
ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
false, rtwdev, 0x7e98, BIT(17));
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n");
dack->dadck_timeout[1] = true;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_b_tbl);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n");
_check_dadc(rtwdev, RF_PATH_B);
_dack_backup_s1(rtwdev);
_dack_reload(rtwdev, RF_PATH_B);
rtw89_phy_write32_clr(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON);
}
static void _dack(struct rtw89_dev *rtwdev)
{
_dack_s0(rtwdev);
_dack_s1(rtwdev);
}
static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
{
struct rtw89_dack_info *dack = &rtwdev->dack;
u32 rf0_0, rf1_0;
u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, RF_AB);
dack->dack_done = false;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK b\n");
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK);
_afe_init(rtwdev);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START);
_addck(rtwdev);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP);
_addck_backup(rtwdev);
_addck_reload(rtwdev);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START);
_dack(rtwdev);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP);
_dack_dump(rtwdev);
dack->dack_done = true;
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
dack->dack_cnt++;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
}
#define RTW8852A_NCTL_VER 0xd
#define RTW8852A_IQK_VER 0x2a
#define RTW8852A_IQK_SS 2
#define RTW8852A_IQK_THR_REK 8
#define RTW8852A_IQK_CFIR_GROUP_NR 4
enum rtw8852a_iqk_type {
ID_TXAGC,
ID_FLOK_COARSE,
ID_FLOK_FINE,
ID_TXK,
ID_RXAGC,
ID_RXK,
ID_NBTXK,
ID_NBRXK,
};
static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path)
{
u8 i = 0x0;
u32 fft[6] = {0x0};
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000);
fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000);
fft[1] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000);
fft[2] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000);
fft[3] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000);
fft[4] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000);
fft[5] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
for (i = 0; i < 6; i++)
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x,fft[%x]= %x\n",
path, i, fft[i]);
}
static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path)
{
u8 i = 0x0;
u32 tmp = 0x0;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1);
for (i = 0x0; i < 0x18; i++) {
rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i);
rtw89_phy_write32_clr(rtwdev, R_NCTL_N2, MASKDWORD);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n",
path, BIT(path), tmp);
udelay(1);
}
rtw89_phy_write32_clr(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX);
rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000);
rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100);
udelay(1);
}
static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
u8 group)
{
static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = {
{0x8f20, 0x8f54, 0x8f88, 0x8fbc},
{0x9320, 0x9354, 0x9388, 0x93bc},
};
u8 idx = 0x0;
u32 tmp = 0x0;
u32 base_addr;
if (path >= RTW8852A_IQK_SS) {
rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
return;
}
if (group >= RTW8852A_IQK_CFIR_GROUP_NR) {
rtw89_warn(rtwdev, "cfir group %d out of range\n", group);
return;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
base_addr = base_addrs[path][group];
for (idx = 0; idx < 0x0d; idx++) {
tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK] %x = %x\n",
base_addr + (idx << 2), tmp);
}
if (path == 0x0) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp);
} else {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp);
}
rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc);
udelay(1);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
BIT(path), tmp);
}
static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
u8 group)
{
static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = {
{0x8d00, 0x8d44, 0x8d88, 0x8dcc},
{0x9100, 0x9144, 0x9188, 0x91cc},
};
u8 idx = 0x0;
u32 tmp = 0x0;
u32 base_addr;
if (path >= RTW8852A_IQK_SS) {
rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
return;
}
if (group >= RTW8852A_IQK_CFIR_GROUP_NR) {
rtw89_warn(rtwdev, "cfir group %d out of range\n", group);
return;
}
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
base_addr = base_addrs[path][group];
for (idx = 0; idx < 0x10; idx++) {
tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]%x = %x\n",
base_addr + (idx << 2), tmp);
}
if (path == 0x0) {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp);
} else {
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n");
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C0, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C1, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C2, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp);
tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C3, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp);
}
rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
BIT(path), tmp);
}
static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
{
u32 tmp = 0x0;
u32 i = 0x0;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000);
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080);
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
for (i = 0; i <= 0x9f; i++) {
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
}
for (i = 0; i <= 0x9f; i++) {
rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
}
rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX2, MASKDWORD);
rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX, MASKDWORD);
}
static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
u32 tmp = 0x0;
rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
udelay(1);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
udelay(1);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0);
udelay(1);
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5);
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
break;
default:
break;
}
tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
fsleep_alt(128);
}
static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
{
u32 tmp;
u32 val;
int ret;
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200,
false, rtwdev, 0xbff8, MASKBYTE0);
if (ret)
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n");
rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
tmp = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
return false;
}
static bool _iqk_one_shot(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, u8 path, u8 ktype)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
bool fail = false;
u32 iqk_cmd = 0x0;
u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path);
u32 addr_rfc_ctl = 0x0;
if (path == RF_PATH_A)
addr_rfc_ctl = 0x5864;
else
addr_rfc_ctl = 0x7864;
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
switch (ktype) {
case ID_TXAGC:
iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
break;
case ID_FLOK_COARSE:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
iqk_cmd = 0x108 | (1 << (4 + path));
break;
case ID_FLOK_FINE:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
iqk_cmd = 0x208 | (1 << (4 + path));
break;
case ID_TXK:
rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
iqk_cmd = 0x008 | (1 << (path + 4)) |
(((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
break;
case ID_RXAGC:
iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
break;
case ID_RXK:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
iqk_cmd = 0x008 | (1 << (path + 4)) |
(((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
break;
case ID_NBTXK:
rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
iqk_cmd = 0x308 | (1 << (4 + path));
break;
case ID_NBRXK:
rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
iqk_cmd = 0x608 | (1 << (4 + path));
break;
default:
return false;
}
rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN);
udelay(1);
fail = _iqk_check_cal(rtwdev, path, ktype);
if (iqk_info->iqk_xym_en)
_iqk_read_xym_dbcc0(rtwdev, path);
if (iqk_info->iqk_fft_en)
_iqk_read_fft_dbcc0(rtwdev, path);
if (iqk_info->iqk_sram_en)
_iqk_sram(rtwdev, path);
if (iqk_info->iqk_cfir_en) {
if (ktype == ID_TXK) {
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x0);
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x1);
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x2);
_iqk_read_txcfir_dbcc0(rtwdev, path, 0x3);
} else {
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0);
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1);
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2);
_iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3);
}
}
rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
return fail;
}
static bool _rxk_group_sel(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, u8 path)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0};
static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30};
static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1};
static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0};
static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a};
static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0};
u8 gp = 0x0;
bool fail = false;
u32 rf0 = 0x0;
for (gp = 0; gp < 0x4; gp++) {
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]);
rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]);
rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]);
rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]);
rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]);
break;
default:
break;
}
rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI,
rf0 | iqk_info->syn1to2);
rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1);
rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
}
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
break;
default:
break;
}
iqk_info->nb_rxcfir[path] = 0x40000000;
rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
B_IQK_RES_RXCFIR, 0x5);
iqk_info->is_wb_rxiqk[path] = true;
return false;
}
static bool _iqk_nbrxk(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, u8 path)
{
struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
u8 group = 0x0;
u32 rf0 = 0x0, tmp = 0x0;
u32 idxrxgain_a = 0x1a0;
u32 idxattc2_a = 0x00;
u32 idxattc1_a = 0x5;
u32 idxrxgain_g = 0x1E0;
u32 idxattc2_g = 0x15;
u32 idxattc1_g = 0x0;
bool fail = false;
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g);
rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g);
rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g);
break;
case RTW89_BAND_5G:
rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a);
rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a);
rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a);
break;
default:
break;
}
rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET);
rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI,
rf0 | iqk_info->syn1to2);
rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
B_CFIR_LUT_GP, group);
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN);
rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP);
fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
switch (iqk_info->iqk_band[path]) {
case RTW89_BAND_2G:
rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
break;