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sd.c
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sd.c
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/* Driver for Realtek RTS51xx USB card reader
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http:https://www.gnu.org/licenses/>.
*
* Author:
* wwang ([email protected])
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
* Maintainer:
* Edwin Rong ([email protected])
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
*/
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include "debug.h"
#include "trace.h"
#include "rts51x.h"
#include "rts51x_transport.h"
#include "rts51x_scsi.h"
#include "rts51x_card.h"
#include "sd.h"
static inline void sd_set_reset_fail(struct rts51x_chip *chip, u8 err_code)
{
struct sd_info *sd_card = &(chip->sd_card);
sd_card->sd_reset_fail |= err_code;
}
static inline void sd_clear_reset_fail(struct rts51x_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
sd_card->sd_reset_fail = 0;
}
static inline int sd_check_reset_fail(struct rts51x_chip *chip, u8 err_code)
{
struct sd_info *sd_card = &(chip->sd_card);
return sd_card->sd_reset_fail & err_code;
}
static inline void sd_set_err_code(struct rts51x_chip *chip, u8 err_code)
{
struct sd_info *sd_card = &(chip->sd_card);
sd_card->err_code |= err_code;
}
static inline void sd_clr_err_code(struct rts51x_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
sd_card->err_code = 0;
}
static inline int sd_check_err_code(struct rts51x_chip *chip, u8 err_code)
{
struct sd_info *sd_card = &(chip->sd_card);
return sd_card->err_code & err_code;
}
static int sd_parse_err_code(struct rts51x_chip *chip)
{
TRACE_RET(chip, STATUS_FAIL);
}
int sd_check_data0_status(struct rts51x_chip *chip)
{
int retval;
u8 stat;
retval = rts51x_ep0_read_register(chip, SD_BUS_STAT, &stat);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
if (!(stat & SD_DAT0_STATUS)) {
sd_set_err_code(chip, SD_BUSY);
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int sd_send_cmd_get_rsp(struct rts51x_chip *chip, u8 cmd_idx,
u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int timeout = 50;
u16 reg_addr;
u8 buf[17], stat;
int len = 2;
int rty_cnt = 0;
sd_clr_err_code(chip);
RTS51X_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
if (rsp_type == SD_RSP_TYPE_R1b)
timeout = 3000;
RTY_SEND_CMD:
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8) (arg >> 24));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8) (arg >> 16));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8) (arg >> 8));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8) arg);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
PINGPONG_BUFFER);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
SD_TM_CMD_RSP | SD_TRANSFER_START);
rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
SD_TRANSFER_END | SD_STAT_IDLE,
SD_TRANSFER_END | SD_STAT_IDLE);
rts51x_add_cmd(chip, READ_REG_CMD, SD_STAT1, 0, 0);
if (CHECK_USB(chip, USB_20)) {
if (rsp_type == SD_RSP_TYPE_R2) {
/* Read data from ping-pong buffer */
for (reg_addr = PPBUF_BASE2;
reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0,
0);
}
len = 18;
} else if (rsp_type != SD_RSP_TYPE_R0) {
/* Read data from SD_CMDx registers */
for (reg_addr = SD_CMD0; reg_addr <= SD_CMD4;
reg_addr++) {
rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0,
0);
}
len = 7;
} else {
len = 2;
}
} else {
len = 2;
}
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, len, timeout);
if (CHECK_SD_TRANS_FAIL(chip, retval)) {
u8 val;
rts51x_ep0_read_register(chip, SD_STAT1, &val);
RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val);
rts51x_ep0_read_register(chip, SD_STAT2, &val);
RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val);
if (val & SD_RSP_80CLK_TIMEOUT)
sd_set_err_code(chip, SD_RSP_TIMEOUT);
rts51x_ep0_read_register(chip, SD_BUS_STAT, &val);
RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
if (retval == STATUS_TIMEDOUT) {
if (rsp_type & SD_WAIT_BUSY_END) {
retval = sd_check_data0_status(chip);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
} else {
sd_set_err_code(chip, SD_TO_ERR);
}
}
rts51x_clear_sd_error(chip);
TRACE_RET(chip, STATUS_FAIL);
}
if (rsp_type == SD_RSP_TYPE_R0)
return STATUS_SUCCESS;
if (CHECK_USB(chip, USB_20)) {
rts51x_read_rsp_buf(chip, 2, buf, len - 2);
} else {
if (rsp_type == SD_RSP_TYPE_R2) {
reg_addr = PPBUF_BASE2;
len = 16;
} else {
reg_addr = SD_CMD0;
len = 5;
}
retval = rts51x_seq_read_register(chip, reg_addr,
(unsigned short)len, buf);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
}
stat = chip->rsp_buf[1];
/* Check (Start,Transmission) bit of Response */
if ((buf[0] & 0xC0) != 0) {
sd_set_err_code(chip, SD_STS_ERR);
TRACE_RET(chip, STATUS_FAIL);
}
/* Check CRC7 */
if (!(rsp_type & SD_NO_CHECK_CRC7)) {
if (stat & SD_CRC7_ERR) {
if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
sd_set_err_code(chip, SD_CRC_ERR);
TRACE_RET(chip, STATUS_FAIL);
}
if (rty_cnt < SD_MAX_RETRY_COUNT) {
wait_timeout(20);
rty_cnt++;
goto RTY_SEND_CMD;
} else {
sd_set_err_code(chip, SD_CRC_ERR);
TRACE_RET(chip, STATUS_FAIL);
}
}
}
/* Check Status */
if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
if ((cmd_idx != SEND_RELATIVE_ADDR)
&& (cmd_idx != SEND_IF_COND)) {
if (cmd_idx != STOP_TRANSMISSION) {
if (buf[1] & 0x80)
TRACE_RET(chip, STATUS_FAIL);
}
if (buf[1] & 0x7F) {
RTS51X_DEBUGP("buf[1]: 0x%02x\n", buf[1]);
TRACE_RET(chip, STATUS_FAIL);
}
if (buf[2] & 0xFF) {
RTS51X_DEBUGP("buf[2]: 0x%02x\n", buf[2]);
TRACE_RET(chip, STATUS_FAIL);
}
if (buf[3] & 0x80) {
RTS51X_DEBUGP("buf[3]: 0x%02x\n", buf[3]);
TRACE_RET(chip, STATUS_FAIL);
}
if (buf[3] & 0x01) {
/* Get "READY_FOR_DATA" bit */
sd_card->sd_data_buf_ready = 1;
} else {
sd_card->sd_data_buf_ready = 0;
}
}
}
if (rsp && rsp_len)
memcpy(rsp, buf, rsp_len);
return STATUS_SUCCESS;
}
static inline void sd_print_debug_reg(struct rts51x_chip *chip)
{
#ifdef CONFIG_RTS5139_DEBUG
u8 val = 0;
rts51x_ep0_read_register(chip, SD_STAT1, &val);
RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val);
rts51x_ep0_read_register(chip, SD_STAT2, &val);
RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val);
rts51x_ep0_read_register(chip, SD_BUS_STAT, &val);
RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
#endif
}
int sd_read_data(struct rts51x_chip *chip, u8 trans_mode, u8 *cmd, int cmd_len,
u16 byte_cnt, u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
int timeout)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int i;
sd_clr_err_code(chip);
if (!buf)
buf_len = 0;
if (buf_len > 512)
/* This function can't read data more than one page */
TRACE_RET(chip, STATUS_FAIL);
rts51x_init_cmd(chip);
if (cmd_len) {
RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
cmd[i]);
}
}
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF,
(u8) (byte_cnt >> 8));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8) blk_cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
(u8) (blk_cnt >> 8));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7 | SD_RSP_LEN_6);
if (trans_mode != SD_TM_AUTO_TUNING) {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
PINGPONG_BUFFER);
}
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
trans_mode | SD_TRANSFER_START);
rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
SD_TRANSFER_END);
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, 1, timeout);
if (CHECK_SD_TRANS_FAIL(chip, retval)) {
sd_print_debug_reg(chip);
if (retval == STATUS_TIMEDOUT) {
sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
SD_RSP_TYPE_R1, NULL, 0);
}
TRACE_RET(chip, STATUS_FAIL);
}
if (buf && buf_len) {
retval = rts51x_read_ppbuf(chip, buf, buf_len);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
}
return STATUS_SUCCESS;
}
static int sd_write_data(struct rts51x_chip *chip, u8 trans_mode,
u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
u8 bus_width, u8 *buf, int buf_len, int timeout)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int i;
sd_clr_err_code(chip);
if (!buf)
buf_len = 0;
/* This function can't write data more than one page */
if (buf_len > 512)
TRACE_RET(chip, STATUS_FAIL);
if (buf && buf_len) {
retval = rts51x_write_ppbuf(chip, buf, buf_len);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
}
rts51x_init_cmd(chip);
if (cmd_len) {
RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
cmd[i]);
}
}
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF,
(u8) (byte_cnt >> 8));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8) blk_cnt);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
(u8) (blk_cnt >> 8));
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
if (cmd_len) {
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
SD_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
} else {
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
SD_RSP_LEN_6);
}
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
trans_mode | SD_TRANSFER_START);
rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
SD_TRANSFER_END);
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
retval = rts51x_get_rsp(chip, 1, timeout);
if (CHECK_SD_TRANS_FAIL(chip, retval)) {
sd_print_debug_reg(chip);
if (retval == STATUS_TIMEDOUT)
sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
SD_RSP_TYPE_R1, NULL, 0);
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int sd_check_csd(struct rts51x_chip *chip, char check_wp)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int i;
u8 csd_ver, trans_speed;
u8 rsp[16];
for (i = 0; i < 6; i++) {
if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
sd_set_reset_fail(chip, SD_RESET_FAIL);
TRACE_RET(chip, STATUS_FAIL);
}
retval =
sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
SD_RSP_TYPE_R2, rsp, 16);
if (retval == STATUS_SUCCESS)
break;
}
if (i == 6)
TRACE_RET(chip, STATUS_FAIL);
memcpy(sd_card->raw_csd, rsp + 1, 15);
/* Get CRC7 */
RTS51X_READ_REG(chip, SD_CMD5, sd_card->raw_csd + 15);
RTS51X_DEBUGP("CSD Response:\n");
RTS51X_DUMP(rsp, 16);
/* Get CSD Version */
csd_ver = (rsp[1] & 0xc0) >> 6;
RTS51X_DEBUGP("csd_ver = %d\n", csd_ver);
trans_speed = rsp[4];
if ((trans_speed & 0x07) == 0x02) { /* 10Mbits/s */
if ((trans_speed & 0xf8) >= 0x30) { /* >25Mbits/s */
if (chip->asic_code)
sd_card->sd_clock = 46;
else
sd_card->sd_clock = CLK_50;
} else if ((trans_speed & 0xf8) == 0x28) { /* 20Mbits/s */
if (chip->asic_code)
sd_card->sd_clock = 39;
else
sd_card->sd_clock = CLK_40;
} else if ((trans_speed & 0xf8) == 0x20) { /* 15Mbits/s */
if (chip->asic_code)
sd_card->sd_clock = 29;
else
sd_card->sd_clock = CLK_30;
} else if ((trans_speed & 0xf8) >= 0x10) { /* 12Mbits/s */
if (chip->asic_code)
sd_card->sd_clock = 23;
else
sd_card->sd_clock = CLK_20;
} else if ((trans_speed & 0x08) >= 0x08) { /* 10Mbits/s */
if (chip->asic_code)
sd_card->sd_clock = 19;
else
sd_card->sd_clock = CLK_20;
} /*else { */
/*If this ,then slow card will use 30M clock */
/* TRACE_RET(chip, STATUS_FAIL); */
/* } */
}
/*else {
TRACE_RET(chip, STATUS_FAIL);
} */
if (CHK_MMC_SECTOR_MODE(sd_card)) {
sd_card->capacity = 0;
} else {
/* For High-Capacity Card, CSD_STRUCTURE always be "0x1" */
if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
/* Calculate total sector according to C_SIZE,
* C_SIZE_MULT & READ_BL_LEN */
u8 blk_size, c_size_mult;
u16 c_size;
/* Get READ_BL_LEN */
blk_size = rsp[6] & 0x0F;
/* Get C_SIZE */
c_size = ((u16) (rsp[7] & 0x03) << 10)
+ ((u16) rsp[8] << 2)
+ ((u16) (rsp[9] & 0xC0) >> 6);
/* Get C_SIZE_MUL */
c_size_mult = (u8) ((rsp[10] & 0x03) << 1);
c_size_mult += (rsp[11] & 0x80) >> 7;
/* Calculate total Capacity */
sd_card->capacity =
(((u32) (c_size + 1)) *
(1 << (c_size_mult + 2))) << (blk_size - 9);
} else {
/* High Capacity Card and Use CSD2.0 Version */
u32 total_sector = 0;
total_sector = (((u32) rsp[8] & 0x3f) << 16) |
((u32) rsp[9] << 8) | (u32) rsp[10];
/* Total Capacity= (C_SIZE+1) *
* 512K Byte = (C_SIZE+1)K Sector,1K = 1024 Bytes */
sd_card->capacity = (total_sector + 1) << 10;
}
}
/* We need check Write-Protected Status by Field PERM WP or TEMP WP */
if (check_wp) {
if (rsp[15] & 0x30)
chip->card_wp |= SD_CARD;
RTS51X_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
}
return STATUS_SUCCESS;
}
static int sd_set_sample_push_timing(struct rts51x_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
rts51x_init_cmd(chip);
if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1,
0x0C | SD_ASYNC_FIFO_RST,
SD_30_MODE | SD_ASYNC_FIFO_RST);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
} else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1,
0x0C | SD_ASYNC_FIFO_RST,
SD_DDR_MODE | SD_ASYNC_FIFO_RST);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
} else {
u8 val = 0;
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x0C, SD_20_MODE);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
if ((chip->option.sd_ctl & SD_PUSH_POINT_CTL_MASK) ==
SD_PUSH_POINT_AUTO) {
val = SD20_TX_NEG_EDGE;
} else if ((chip->option.sd_ctl & SD_PUSH_POINT_CTL_MASK) ==
SD_PUSH_POINT_DELAY) {
val = SD20_TX_14_AHEAD;
} else {
val = SD20_TX_NEG_EDGE;
}
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
SD20_TX_SEL_MASK, val);
if ((chip->option.sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
SD_SAMPLE_POINT_AUTO) {
if (chip->asic_code) {
if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card))
val = SD20_RX_14_DELAY;
else
val = SD20_RX_POS_EDGE;
} else {
val = SD20_RX_14_DELAY;
}
} else if ((chip->option.sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
SD_SAMPLE_POINT_DELAY) {
val = SD20_RX_14_DELAY;
} else {
val = SD20_RX_POS_EDGE;
}
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
SD20_RX_SEL_MASK, val);
}
if (CHK_MMC_DDR52(sd_card) && CHK_MMC_8BIT(sd_card)) {
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DMA1_CTL,
EXTEND_DMA1_ASYNC_SIGNAL, 0);
}
retval = rts51x_send_cmd(chip, MODE_C, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return STATUS_SUCCESS;
}
static void sd_choose_proper_clock(struct rts51x_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
if (CHK_SD_SDR104(sd_card)) {
if (chip->asic_code)
sd_card->sd_clock = chip->option.asic_sd_sdr104_clk;
else
sd_card->sd_clock = chip->option.fpga_sd_sdr104_clk;
} else if (CHK_SD_DDR50(sd_card)) {
if (chip->asic_code)
sd_card->sd_clock = chip->option.asic_sd_ddr50_clk;
else
sd_card->sd_clock = chip->option.fpga_sd_ddr50_clk;
} else if (CHK_SD_SDR50(sd_card)) {
if (chip->asic_code)
sd_card->sd_clock = chip->option.asic_sd_sdr50_clk;
else
sd_card->sd_clock = chip->option.fpga_sd_sdr50_clk;
} else if (CHK_SD_HS(sd_card)) {
if (chip->asic_code)
sd_card->sd_clock = chip->option.asic_sd_hs_clk;
else
sd_card->sd_clock = chip->option.fpga_sd_hs_clk;
} else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
if (chip->asic_code)
sd_card->sd_clock = chip->option.asic_mmc_52m_clk;
else
sd_card->sd_clock = chip->option.fpga_mmc_52m_clk;
} else if (CHK_MMC_26M(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = 46;
RTS51X_DEBUGP("Set MMC clock to 22.5MHz\n");
} else {
sd_card->sd_clock = CLK_50;
}
}
}
static int sd_set_init_para(struct rts51x_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
retval = sd_set_sample_push_timing(chip);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
sd_choose_proper_clock(chip);
retval = switch_clock(chip, sd_card->sd_clock);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return STATUS_SUCCESS;
}
int rts51x_sd_select_card(struct rts51x_chip *chip, int select)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
u8 cmd_idx, cmd_type;
u32 addr;
if (select) {
cmd_idx = SELECT_CARD;
cmd_type = SD_RSP_TYPE_R1;
addr = sd_card->sd_addr;
} else {
cmd_idx = DESELECT_CARD;
cmd_type = SD_RSP_TYPE_R0;
addr = 0;
}
retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
return STATUS_SUCCESS;
}
static int sd_wait_currentstate_dataready(struct rts51x_chip *chip, u8 statechk,
u8 rdychk, u16 pollingcnt)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
u8 rsp[5];
u16 i;
for (i = 0; i < pollingcnt; i++) {
retval =
sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
SD_RSP_TYPE_R1, rsp, 5);
if (retval == STATUS_SUCCESS) {
if (((rsp[3] & 0x1E) == statechk)
&& ((rsp[3] & 0x01) == rdychk)) {
return STATUS_SUCCESS;
}
} else {
rts51x_clear_sd_error(chip);
TRACE_RET(chip, STATUS_FAIL);
}
}
return STATUS_TIMEDOUT;
}
static int sd_voltage_switch(struct rts51x_chip *chip)
{
int retval;
u8 stat;
RTS51X_WRITE_REG(chip, SD_BUS_STAT,
SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
SD_CLK_TOGGLE_EN);
retval =
sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL,
0);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
RTS51X_READ_REG(chip, SD_BUS_STAT, &stat);
if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
SD_DAT1_STATUS | SD_DAT0_STATUS))
TRACE_RET(chip, STATUS_FAIL);
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BUS_STAT, 0xFF,
SD_CLK_FORCE_STOP);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PAD_CTL, SD_IO_USING_1V8,
SD_IO_USING_1V8);
if (chip->asic_code)
rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG,
TUNE_SD18_MASK, TUNE_SD18_1V8);
retval = rts51x_send_cmd(chip, MODE_C, 100);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, retval);
wait_timeout(chip->option.D3318_off_delay);
RTS51X_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
wait_timeout(10);
RTS51X_READ_REG(chip, SD_BUS_STAT, &stat);
if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
(SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
SD_DAT1_STATUS | SD_DAT0_STATUS)) {
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BUS_STAT, 0xFF,
SD_CLK_FORCE_STOP);
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, 0xFF, 0);
rts51x_send_cmd(chip, MODE_C, 100);
TRACE_RET(chip, STATUS_FAIL);
}
RTS51X_WRITE_REG(chip, SD_BUS_STAT,
SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
return STATUS_SUCCESS;
}
static int sd_change_phase(struct rts51x_chip *chip, u8 sample_point,
u8 tune_dir)
{
u16 SD_VP_CTL, SD_DCMPS_CTL;
u8 val;
int retval;
RTS51X_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
sample_point, tune_dir);
if (tune_dir == TUNE_RX) {
SD_VP_CTL = SD_VPCLK1_CTL;
SD_DCMPS_CTL = SD_DCMPS1_CTL;
} else {
SD_VP_CTL = SD_VPCLK0_CTL;
SD_DCMPS_CTL = SD_DCMPS0_CTL;
}
if (chip->asic_code) {
RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
RTS51X_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
RTS51X_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
RTS51X_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET,
PHASE_NOT_RESET);
RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
} else {
#ifdef CONFIG_RTS5139_DEBUG
RTS51X_READ_REG(chip, SD_VP_CTL, &val);
RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val);
RTS51X_READ_REG(chip, SD_DCMPS_CTL, &val);
RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
#endif
RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
udelay(100);
RTS51X_WRITE_REG(chip, SD_VP_CTL, 0xFF,
PHASE_NOT_RESET | sample_point);
udelay(200);
rts51x_init_cmd(chip);
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
DCMPS_CHANGE);
rts51x_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
retval = rts51x_send_cmd(chip, MODE_CR, 100);
if (retval != STATUS_SUCCESS)
TRACE_GOTO(chip, Fail);
retval = rts51x_get_rsp(chip, 1, 500);
if (retval != STATUS_SUCCESS)
TRACE_GOTO(chip, Fail);
val = chip->rsp_buf[0];
if (val & DCMPS_ERROR)
TRACE_GOTO(chip, Fail);
if ((val & DCMPS_CURRENT_PHASE) != sample_point)
TRACE_GOTO(chip, Fail);
RTS51X_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
udelay(100);
}
RTS51X_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_RST, 0);
return STATUS_SUCCESS;
Fail:
#ifdef CONFIG_RTS5139_DEBUG
rts51x_ep0_read_register(chip, SD_VP_CTL, &val);
RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val);
rts51x_ep0_read_register(chip, SD_DCMPS_CTL, &val);
RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
#endif
RTS51X_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
RTS51X_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
wait_timeout(10);
return STATUS_FAIL;
}
static int sd_check_spec(struct rts51x_chip *chip, u8 bus_width)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
u8 cmd[5], buf[8];
retval =
sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
NULL, 0);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, STATUS_FAIL);
cmd[0] = 0x40 | SEND_SCR;
cmd[1] = 0;
cmd[2] = 0;
cmd[3] = 0;
cmd[4] = 0;
retval =
sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf,
8, 250);
if (retval != STATUS_SUCCESS) {
rts51x_clear_sd_error(chip);
TRACE_RET(chip, retval);
}
memcpy(sd_card->raw_scr, buf, 8);
if ((buf[0] & 0x0F) == 0)
TRACE_RET(chip, STATUS_FAIL);
return STATUS_SUCCESS;
}
static int sd_query_switch_result(struct rts51x_chip *chip, u8 func_group,
u8 func_to_switch, u8 *buf, int buf_len)
{
u8 support_mask = 0, query_switch = 0, switch_busy = 0;
int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
if (func_group == SD_FUNC_GROUP_1) {
support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
switch (func_to_switch) {
case HS_SUPPORT:
support_mask = HS_SUPPORT_MASK;
query_switch = HS_QUERY_SWITCH_OK;
switch_busy = HS_SWITCH_BUSY;
break;
case SDR50_SUPPORT:
support_mask = SDR50_SUPPORT_MASK;
query_switch = SDR50_QUERY_SWITCH_OK;
switch_busy = SDR50_SWITCH_BUSY;
break;
case SDR104_SUPPORT:
support_mask = SDR104_SUPPORT_MASK;
query_switch = SDR104_QUERY_SWITCH_OK;
switch_busy = SDR104_SWITCH_BUSY;
break;
case DDR50_SUPPORT:
support_mask = DDR50_SUPPORT_MASK;
query_switch = DDR50_QUERY_SWITCH_OK;
switch_busy = DDR50_SWITCH_BUSY;
break;
default:
TRACE_RET(chip, STATUS_FAIL);
}
} else if (func_group == SD_FUNC_GROUP_3) {
support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
switch (func_to_switch) {
case DRIVING_TYPE_A:
support_mask = DRIVING_TYPE_A_MASK;
query_switch = TYPE_A_QUERY_SWITCH_OK;
switch_busy = TYPE_A_SWITCH_BUSY;
break;
case DRIVING_TYPE_C:
support_mask = DRIVING_TYPE_C_MASK;
query_switch = TYPE_C_QUERY_SWITCH_OK;
switch_busy = TYPE_C_SWITCH_BUSY;
break;
case DRIVING_TYPE_D:
support_mask = DRIVING_TYPE_D_MASK;
query_switch = TYPE_D_QUERY_SWITCH_OK;
switch_busy = TYPE_D_SWITCH_BUSY;
break;
default:
TRACE_RET(chip, STATUS_FAIL);
}
} else if (func_group == SD_FUNC_GROUP_4) {
support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
switch (func_to_switch) {
case CURRENT_LIMIT_400:
support_mask = CURRENT_LIMIT_400_MASK;
query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
break;
case CURRENT_LIMIT_600:
support_mask = CURRENT_LIMIT_600_MASK;
query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
break;
case CURRENT_LIMIT_800:
support_mask = CURRENT_LIMIT_800_MASK;
query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
break;
default:
TRACE_RET(chip, STATUS_FAIL);
}
} else {
TRACE_RET(chip, STATUS_FAIL);
}