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Numa #1556
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Numa #1556
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6fc5f17
detect NUMA systems and pin work threads to nodes (linux)
zrm 0d23f8c
disable mmap prefetch/readahead for NUMA systems
zrm 9d058c2
avoid sending finalize op to thread pool if it does nothing
zrm 2c1b5ae
silence robot
zrm 8502d51
fix args
zrm bf83dcb
make --numa a param
zrm b71dfe6
recommendation that n_nodes evenly divide n_threads did not warrant s…
zrm adaad10
lower synchronization overhead
zrm c31d51d
statically allocate
zrm 2f5bb46
move numa state to g_state
zrm 4b94582
add description for --numa
zrm 90a0e65
Merge branch 'master' into HEAD
ggerganov d0e3596
ggml : minor style changes
ggerganov 67ba34e
ggml : minor style + try fix sanitizer build
ggerganov 8f98035
Merge branch 'master' into HEAD
ggerganov 0fe4b00
llama : allow to initialize backend with NUMA support
ggerganov 875a1e1
llama : avoid ggml include in llama-util.h
ggerganov 4a555b4
ggml : style / formatting
ggerganov 81a40e9
ggml : fix handling of ops with n_threads > n_tasks > 1
ggerganov 9aec2b7
server : utilize numa parameter
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Hi, sorry for this comment. I have limit experiences of NUMA node and processes placement optimization to utilize NUMA node's memory access locality. But I am sure such locality helps to improve end to end latencies.
I want to understand what the optimization exactly made by this PR.
which part does this job ?
when I/O compute overlap , disabling prefetch surely gave bad performance in latencies and throughput. But why is this related to NUMA nodes ?
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Do we use mmap to implement pin memory allocation for streams/weights inputs ?
I am a little confused when you talk about page (paged memory) and mmap (which maps memory from device to DRAM and ready to be read by DMA)
Thank you if you can help to clarify my concerns. Happy to learn your solutions.