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The common\r\npolicy for instructions is to act as undisturbed if one is (i.e. tail or\r\nmask), or write all 1s if none.\r\n\r\nFor those instructions in which multiple micro instructions are\r\ninstantiated to write to the same register (`VlStride` and `VlIndex` for\r\nmemory, and `VectorGather`, `VectorSlideUp` and `VectorSlideDown` for\r\narithmetic), a (new) micro instruction named `VPinVdCpyVsMicroInst` has\r\nbeen used to pin the destination register so that there's no need to\r\ncopy the partial results between them. This idea is similar to what's on\r\nARM's SVE code. This micro also implements the tail/mask policy for this\r\ncases.\r\n\r\nFinally, it's worth noting that while now using an agnostic policy for\r\nboth tail/mask should remove all dependencies with old destination\r\nregisters, there's an exception with `VectorSlideUp`. The\r\n`vslideup_{vx,vi}` instructions need the elements in the offset to be\r\nunchanged. The current implementation overrides the current vta/vma and\r\nmakes them act as undisturbed, since they require the old destination\r\nregister anyways. There's a minor issue with this though, as\r\n`v{,f}slide1up` variants do not need this, but since they share the same\r\nconstructor, will act all the same.\r\n\r\nRelated issue #997.","shortMessageHtmlLink":"arch-riscv: add agnostic option to vector tail/mask policy for mem an…"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEinec_gA","startCursor":null,"endCursor":null}},"title":"Activity · gem5/gem5"}