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Issues list

v2x: Solve issues to have working tests arch-* Issue related to all architectures. lang-verilog Issue uses (or requires) Verilog language. lang-xml Issues uses (or requires) XML language. type-sim Issue is related to xxx.sim.v files. type-utils Issues is related to the scripts inside the repo. type-vpr
#599 opened Apr 16, 2019 by acomodi Use v2x for XML generation
@acomodi
24
Missing support for xc7a35tftg256-1 in archive
#1800 opened Nov 21, 2020 by dnltz
18
parse_pdf_modules.py seems to be not working
#1243 opened Dec 18, 2019 by rodrigomelo9
16
OpenTitan support
#1442 opened Apr 24, 2020 by rw1nkler
15
MMCM primitive generate incorect clock frequencies in hardware
#2248 opened Aug 26, 2021 by WhiteNinjaZ
14
Modeling the FDCE with timing for VPR
#788 opened May 28, 2019 by mkurc-ant
14
Add schema checks to make sure all block have metadata arch-* Issue related to all architectures. help wanted lang-xml Issues uses (or requires) XML language. type-vpr
#623 opened Apr 23, 2019 by mithro
12
v2x: Add features to enable replacing handwritten XML with generated from .sim.v files
#595 opened Apr 16, 2019 by litghost
1 of 7 tasks
Use v2x for XML generation
12
Merge the channel.py and channel2.py files in utils dependencies help wanted lang-python Issue uses (or requires) Python language. lang-xml Issues uses (or requires) XML language. type-defs Issue is related to pb_type.xml / model.xml files used by Verilog to Routing. type-utils Issues is related to the scripts inside the repo. type-vpr
#338 opened Jan 24, 2019 by mithro
11
Litex: drop the --symbiflow flag when generating the minilitex design
#1753 opened Nov 4, 2020 by acomodi
1
9
SDC/XDC create_clock and set_false_path constraints should propigate through Yosys
#1291 opened Jan 31, 2020 by litghost
@tmichalak
9
cmake setup depends on users Python install
#1155 opened Nov 18, 2019 by mithro
9
Write a Python library for decoding Xilinx Series 7 wire names arch-xc7 Issues related to the XC7 architecture good first issue help wanted lang-python Issue uses (or requires) Python language. type-utils Issues is related to the scripts inside the repo.
#181 opened Jul 11, 2018 by mithro
9
Need help adding support for Spartan-7 board to arch-defs
#2372 opened Jan 29, 2022 by MidsummerNight
8
Wrong synthesis result when signed signal is used for bit indexing
#2307 opened Oct 17, 2021 by gergoerdi
8
Errors in implement a Verilog design involving in uart485 and rom bug
#2103 opened Mar 16, 2021 by zjenny09
8
Instability due to small changes to memory initialization
#1776 opened Nov 16, 2020 by acomodi
8
Unresolved $_TBUF_ cells after Yosys synthesis
#1668 opened Sep 16, 2020 by rw1nkler
8
Quicklogic: Router run time very high
#1486 opened May 14, 2020 by tpagarani
8
Clean up the top level directory
#626 opened Apr 23, 2019 by mithro
4 tasks
8
Rename library to common/verilog
#571 opened Apr 10, 2019 by mithro
8
Conda lock pull requests not running CI?
#2319 opened Nov 16, 2021 by mithro
7
Artix 200T missing bits
#1750 opened Nov 4, 2020 by acomodi
7
Create a tool to extract the library definitions from the Spartan 6 Library User Guide
#1246 opened Dec 19, 2019 by rodrigomelo9
7
Rely on external package management as much as possible type-build Issues related to the build system (IE Make and stuff)
#559 opened Apr 8, 2019 by HackerFoo
7
ProTip! no:milestone will show everything without a milestone.