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AT32F403Axx_v2.svd
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AT32F403Axx_v2.svd
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<?xml version="1.0" encoding="utf-8"?>
<!-- File naming: <vendor>_<part/series name>.svd -->
<!--
Copyright (C) 2012-2014 ARM Limited. All rights reserved.
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
This is a description of a none-existent and incomplete device
for demonstration purposes only.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-->
<device schemaVersion="1.1" xmlns:xs="https://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>Keil</vendor> <!-- device vendor name -->
<vendorID>ArteryTek</vendorID> <!-- device vendor short name -->
<name>AT32F403Axx_v2</name> <!-- name of part-->
<series>AT32F403A</series> <!-- device series the device belongs to -->
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
<description>ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. </description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
suitable processor architectures. This file can be freely distributed.\n
Modifications to this file shall be clearly marked.\n
\n
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
and register that do not define "size" themselves -->
<access>read-write</access> <!-- default access permission for all subsequent registers -->
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
<peripherals>
<peripheral>
<name>XMC</name>
<description>Flexible static memory controller</description>
<groupName>XMC</groupName>
<baseAddress>0xA0000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>XMC</name>
<description>XMC global interrupt</description>
<value>48</value>
</interrupt>
<registers>
<register>
<name>BK1CTRL1</name>
<displayName>BK1CTRL1</displayName>
<description>SRAM/NOR-Flash chip-select control register
1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030DB</resetValue>
<fields>
<field>
<name>MWMC</name>
<description>Memory write mode control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRPGS</name>
<description>CRAM page size</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>NWASEN</name>
<description>NWAIT in asynchronous transfer enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWTD</name>
<description>Read-write timing different</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWSEN</name>
<description>NWAIT in synchronous transfer enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WEN</name>
<description>Write enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWTCFG</name>
<description>Wait timing configuration</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRAPEN</name>
<description>Wrapped enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWPOL</name>
<description>NWAIT polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCBEN</name>
<description>Synchronous burst enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOREN</name>
<description>Nor flash access enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMDBW</name>
<description>External memory data bus width</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DEV</name>
<description>Memory device type</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADMUXEN</name>
<description>Address and data multiplexing enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Memory bank enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK1TMG1</name>
<displayName>BK1TMG1</displayName>
<description>SRAM/NOR-Flash chip-select timing register
1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ASYNCM</name>
<description>Asynchronous mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTLAT</name>
<description>Data latency</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKPSC</name>
<description>Clock prescale</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BUSLAT</name>
<description>Bus latency</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTST</name>
<description>Asynchronous data setup time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDRHT</name>
<description>Address-hold time</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDRST</name>
<description>Address setup time</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK1CTRL4</name>
<displayName>BK1CTRL4</displayName>
<description>SRAM/NOR-Flash chip-select control register 4</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030D2</resetValue>
<fields>
<field>
<name>MWMC</name>
<description>Memory write mode control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRPGS</name>
<description>CRAM page size</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>NWASEN</name>
<description>NWAIT in asynchronous transfer enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWTD</name>
<description>Read-write timing different</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWSEN</name>
<description>NWAIT in synchronous transfer enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WEN</name>
<description>Write enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWTCFG</name>
<description>Wait timing configuration</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRAPEN</name>
<description>Wrapped enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWPOL</name>
<description>NWAIT polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCBEN</name>
<description>Synchronous burst enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOREN</name>
<description>Nor flash access enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMDBW</name>
<description>External memory data bus width</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DEV</name>
<description>Memory device type</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADMUXEN</name>
<description>Address and data multiplexing enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Memory bank enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK1TMG4</name>
<displayName>BK1TMG4</displayName>
<description>SRAM/NOR-Flash chip-select timing register
4</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ASYNCM</name>
<description>Asynchronous mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTLAT</name>
<description>Data latency</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKPSC</name>
<description>Clock prescale</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BUSLAT</name>
<description>Bus latency</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTST</name>
<description>Asynchronous data setup time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDRHT</name>
<description>Address-hold time</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDRST</name>
<description>Address setup time</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK2CTRL</name>
<displayName>BK2CTRL</displayName>
<description>PC Card/NAND Flash control register 2</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000018</resetValue>
<fields>
<field>
<name>ECCPGS</name>
<description>ECC page size</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TAR</name>
<description>ALE to RE delay</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TCR</name>
<description>CLE to RE delay</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ECCEN</name>
<description>ECC enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTMDBW</name>
<description>External memory data bus width</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DEV</name>
<description>Memory device type</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Memory bank enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NWEN</name>
<description>Wait feature enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK2IS</name>
<displayName>BK2IS</displayName>
<description>FIFO status and interrupt register 2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>FIFOE</name>
<description>FIFO empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FEIEN</name>
<description>Falling edge interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HLIEN</name>
<description>High-level interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REIEN</name>
<description>Rising edge interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FES</name>
<description>Falling edge status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HLS</name>
<description>High-level status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RES</name>
<description>Rising edge capture status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BK2TMGMEM</name>
<displayName>BK2TMGMEM</displayName>
<description>Regular memory space timing register 2</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>RGDHIZT</name>
<description>Regular memory databus High resistance time</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RGHT</name>
<description>Regular memory hold time</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RGWT</name>
<description>Regular memory wait time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RGST</name>
<description>Regular memory setup time</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK2TMGATT</name>
<displayName>BK2TMGATT</displayName>
<description>special memory space timing register 2</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>SPDHIZT</name>
<description>special memory databus High resistance time</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SPHT</name>
<description>special memory hold time</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SPWT</name>
<description>special memory wait time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SPST</name>
<description>special memory setup time</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK2ECC</name>
<displayName>BK2ECC</displayName>
<description>ECC result register 2</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECC</name>
<description>ECC result</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK1TMGWR1</name>
<displayName>BK1TMGWR1</displayName>
<description>SRAM/NOR-Flash write timing registers
1</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ASYNCM</name>
<description>Asynchronous mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>BUSLAT</name>
<description>Bus latency</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTST</name>
<description>Asynchronous data setup time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDRHT</name>
<description>Address-hold time</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDRST</name>
<description>Address setup time</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BK1TMGWR4</name>
<displayName>BK1TMGWR4</displayName>
<description>SRAM/NOR-Flash write timing registers
4</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ASYNCM</name>
<description>Asynchronous mode</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>BUSLAT</name>
<description>Bus latency</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DTST</name>
<description>Asynchronous data setup time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDRHT</name>
<description>Address-hold time</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADDRST</name>
<description>Address setup time</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT1</name>
<displayName>EXT1</displayName>
<description>externl timeing register 1</description>
<addressOffset>0x220</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000808</resetValue>
<fields>
<field>
<name>BUSLATW2W</name>
<description>Bus turnaround phase for consecutive write duration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSLATR2R</name>
<description>Bus turnaround phase for consecutive read duration</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT4</name>
<displayName>EXT4</displayName>
<description>externl timeing register 4</description>
<addressOffset>0x22C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000808</resetValue>
<fields>
<field>
<name>BUSLATW2W</name>
<description>BUSLATW2W</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BUSLATR2R</name>
<description>BUSLATR2R</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWC</name>
<description>Power control</description>
<groupName>PWC</groupName>
<baseAddress>0x40007000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Power control register
(PWC_CTRL)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VRSEL</name>
<description>Voltage regulator state select when deepsleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPSEL</name>
<description>Low power mode select when Cortex-M4F sleepdeep</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLSWEF</name>
<description>Clear SWEF flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLSEF</name>
<description>Clear SEF flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVMEN</name>
<description>Power voltage monitoring enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVMSEL</name>
<description>Power voltage monitoring boundary select</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BPWEN</name>
<description>Battery powered domain write enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRLSTS</name>
<displayName>CTRLSTS</displayName>
<description>Power control and status register
(PWC_CTRLSTS)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWEF</name>
<description>Standby wake-up event flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SEF</name>
<description>Standby mode entry flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PVMOF</name>
<description>Power voltage monitoring output flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SWPEN</name>
<description>Standby wake-up pin enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRM</name>
<description>Clock and reset management</description>
<groupName>CRM</groupName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRM</name>
<description>CRM global interrupt</description>
<value>5</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>Clock control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000083</resetValue>
<fields>
<field>
<name>HICKEN</name>
<description>High speed internal clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICKSTBL</name>
<description>High speed internal clock ready flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HICKTRIM</name>
<description>High speed internal clock trimming</description>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HICKCAL</name>
<description>High speed internal clock calibration</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HEXTEN</name>
<description>High speed exernal crystal enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HEXTSTBL</name>
<description>High speed exernal crystal ready flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HEXTBYPS</name>
<description>High speed exernal crystal bypass</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CFDEN</name>
<description>Clock failure detection enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLEN</name>
<description>PLL enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLSTBL</name>
<description>PLL clock ready flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CFG</name>
<displayName>CFG</displayName>
<description>Clock configuration register
(CRM_CFG)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCLKSEL</name>
<description>System clock select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SCLKSTS</name>
<description>System Clock select Status</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AHBDIV</name>
<description>AHB division</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APB1DIV</name>
<description>APB1 division</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APB2DIV</name>
<description>APB2 division</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADCDIV1_0</name>
<description>ADC division bit1 and bit0</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLRCS</name>
<description>PLL reference clock select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLHEXTDIV</name>
<description>HEXT division selection for PLL entry clock</description>