-
Notifications
You must be signed in to change notification settings - Fork 316
/
drv_types.h
1854 lines (1571 loc) · 46.2 KB
/
drv_types.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/******************************************************************************
*
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*-------------------------------------------------------------------------------
For type defines and data structure defines
--------------------------------------------------------------------------------*/
#ifndef __DRV_TYPES_H__
#define __DRV_TYPES_H__
#include <drv_conf.h>
#include <basic_types.h>
#include <osdep_service.h>
#include <rtw_byteorder.h>
#include <wlan_bssdef.h>
#include <wifi.h>
#include <ieee80211.h>
#ifdef CONFIG_ARP_KEEP_ALIVE
#include <net/neighbour.h>
#include <net/arp.h>
#endif
#ifdef PLATFORM_OS_XP
#include <drv_types_xp.h>
#endif
#ifdef PLATFORM_OS_CE
#include <drv_types_ce.h>
#endif
#ifdef PLATFORM_LINUX
#include <drv_types_linux.h>
#endif
enum _NIC_VERSION {
RTL8711_NIC,
RTL8712_NIC,
RTL8713_NIC,
RTL8716_NIC
};
typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
#include <rtw_debug.h>
#include <cmn_info/rtw_sta_info.h>
#include <rtw_rf.h>
#include "../core/rtw_chplan.h"
#ifdef CONFIG_80211N_HT
#include <rtw_ht.h>
#endif
#ifdef CONFIG_80211AC_VHT
#include <rtw_vht.h>
#endif
#include <rtw_cmd.h>
#include <cmd_osdep.h>
#include <rtw_security.h>
#include <rtw_xmit.h>
#include <xmit_osdep.h>
#include <rtw_recv.h>
#include <rtw_rm.h>
#ifdef CONFIG_BEAMFORMING
#include <rtw_beamforming.h>
#endif
#include <recv_osdep.h>
#include <rtw_efuse.h>
#include <rtw_sreset.h>
#include <hal_intf.h>
#include <hal_com.h>
#include<hal_com_h2c.h>
#include <hal_com_led.h>
#include "../hal/hal_dm.h"
#include <rtw_qos.h>
#include <rtw_pwrctrl.h>
#include <rtw_mlme.h>
#include <mlme_osdep.h>
#include <rtw_io.h>
#include <rtw_ioctl.h>
#include <rtw_ioctl_set.h>
#include <rtw_ioctl_query.h>
#include <osdep_intf.h>
#include <rtw_eeprom.h>
#include <sta_info.h>
#include <rtw_event.h>
#include <rtw_mlme_ext.h>
#include <rtw_mi.h>
#include <rtw_ap.h>
#ifdef CONFIG_RTW_MESH
#include "../core/mesh/rtw_mesh.h"
#endif
#include <rtw_efuse.h>
#include <rtw_version.h>
#include <rtw_odm.h>
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#include <rtw_mem.h>
#endif
#include <rtw_p2p.h>
#ifdef CONFIG_TDLS
#include <rtw_tdls.h>
#endif /* CONFIG_TDLS */
#ifdef CONFIG_WAPI_SUPPORT
#include <rtw_wapi.h>
#endif /* CONFIG_WAPI_SUPPORT */
#ifdef CONFIG_MP_INCLUDED
#include <rtw_mp.h>
#endif /* CONFIG_MP_INCLUDED */
#ifdef CONFIG_BR_EXT
#include <rtw_br_ext.h>
#endif /* CONFIG_BR_EXT */
#ifdef CONFIG_IOL
#include <rtw_iol.h>
#endif /* CONFIG_IOL */
#include <ip.h>
#include <if_ether.h>
#include <ethernet.h>
#include <circ_buf.h>
#include <rtw_android.h>
#include <rtw_btcoex_wifionly.h>
#include <rtw_btcoex.h>
#ifdef CONFIG_MCC_MODE
#include <rtw_mcc.h>
#endif /*CONFIG_MCC_MODE */
#ifdef CONFIG_RTW_REPEATER_SON
#include <rtw_rson.h>
#endif /*CONFIG_RTW_REPEATER_SON */
#define SPEC_DEV_ID_NONE BIT(0)
#define SPEC_DEV_ID_DISABLE_HT BIT(1)
#define SPEC_DEV_ID_ENABLE_PS BIT(2)
#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
struct specific_device_id {
u32 flags;
u16 idVendor;
u16 idProduct;
};
struct registry_priv {
u8 chip_version;
u8 rfintfs;
u8 lbkmode;
u8 hci;
NDIS_802_11_SSID ssid;
u8 network_mode; /* infra, ad-hoc, auto */
u8 channel;/* ad-hoc support requirement */
u8 wireless_mode;/* A, B, G, auto */
u8 scan_mode;/* active, passive */
u8 radio_enable;
u8 preamble;/* long, short, auto */
u8 vrtl_carrier_sense;/* Enable, Disable, Auto */
u8 vcs_type;/* RTS/CTS, CTS-to-self */
u16 rts_thresh;
u16 frag_thresh;
u8 adhoc_tx_pwr;
u8 soft_ap;
u8 power_mgnt;
u8 ips_mode;
u8 lps_level;
#ifdef CONFIG_LPS_1T1R
u8 lps_1t1r;
#endif
u8 lps_chk_by_tp;
#ifdef CONFIG_WOWLAN
u8 wow_power_mgnt;
u8 wow_lps_level;
#ifdef CONFIG_LPS_1T1R
u8 wow_lps_1t1r;
#endif
#endif /* CONFIG_WOWLAN */
u8 smart_ps;
#ifdef CONFIG_WMMPS_STA
u8 wmm_smart_ps;
#endif /* CONFIG_WMMPS_STA */
u8 usb_rxagg_mode;
u8 dynamic_agg_enable;
u8 long_retry_lmt;
u8 short_retry_lmt;
u16 busy_thresh;
u16 max_bss_cnt;
u8 ack_policy;
u8 mp_mode;
#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
u8 mp_customer_str;
#endif
u8 mp_dm;
u8 software_encrypt;
u8 software_decrypt;
#ifdef CONFIG_TX_EARLY_MODE
u8 early_mode;
#endif
#ifdef CONFIG_NARROWBAND_SUPPORTING
u8 rtw_nb_config;
#endif
u8 acm_method;
/* WMM */
u8 wmm_enable;
#ifdef CONFIG_WMMPS_STA
/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
u8 uapsd_max_sp_len;
/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
u8 uapsd_ac_enable;
#endif /* CONFIG_WMMPS_STA */
WLAN_BSSID_EX dev_network;
#if CONFIG_TX_AC_LIFETIME
u8 tx_aclt_flags;
struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
#endif
u8 tx_bw_mode;
#ifdef CONFIG_AP_MODE
u8 bmc_tx_rate;
#endif
#ifdef CONFIG_80211N_HT
u8 ht_enable;
/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */
/* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
/* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
u8 bw_mode;
u8 ampdu_enable;/* for tx */
u8 rx_stbc;
u8 rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */
u8 tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */
u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */
/* Short GI support Bit Map */
/* BIT0 - 20MHz, 1: support, 0: non-support */
/* BIT1 - 40MHz, 1: support, 0: non-support */
/* BIT2 - 80MHz, 1: support, 0: non-support */
/* BIT3 - 160MHz, 1: support, 0: non-support */
u8 short_gi;
/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
u8 ldpc_cap;
/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
u8 stbc_cap;
#if defined(CONFIG_RTW_TX_NPATH_EN)
u8 tx_npath;
#endif
#if defined(CONFIG_RTW_PATH_DIV)
u8 path_div;
#endif
/*
* BIT0: Enable VHT SU Beamformer
* BIT1: Enable VHT SU Beamformee
* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
* BIT4: Enable HT Beamformer
* BIT5: Enable HT Beamformee
*/
u8 beamform_cap;
u8 beamformer_rf_num;
u8 beamformee_rf_num;
#endif /* CONFIG_80211N_HT */
#ifdef CONFIG_80211AC_VHT
u8 vht_enable; /* 0:disable, 1:enable, 2:auto */
u8 ampdu_factor;
u8 vht_rx_mcs_map[2];
#endif /* CONFIG_80211AC_VHT */
u8 lowrate_two_xmit;
u8 low_power ;
u8 wifi_spec;/* !turbo_mode */
u8 rf_path; /*rf_config*/
u8 tx_nss;
u8 rx_nss;
char alpha2[2];
u8 channel_plan;
u8 excl_chs[MAX_CHANNEL_NUM];
u8 full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/
#ifdef CONFIG_BT_COEXIST
u8 btcoex;
u8 bt_iso;
u8 bt_sco;
u8 bt_ampdu;
u8 ant_num;
u8 single_ant_path;
#endif
BOOLEAN bAcceptAddbaReq;
u8 antdiv_cfg;
u8 antdiv_type;
u8 drv_ant_band_switch;
u8 switch_usb_mode;
u8 usbss_enable;/* 0:disable,1:enable */
u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
u8 hwpwrp_detect;/* 0:disable,1:enable */
u8 hw_wps_pbc;/* 0:disable,1:enable */
#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
char adaptor_info_caching_file_path[PATH_LENGTH_MAX];
#endif
#ifdef CONFIG_LAYER2_ROAMING
u8 max_roaming_times; /* the max number driver will try to roaming */
#endif
#ifdef CONFIG_IOL
u8 fw_iol; /* enable iol without other concern */
#endif
#ifdef CONFIG_80211D
u8 enable80211d;
#endif
u8 ifname[16];
u8 if2name[16];
u8 notch_filter;
/* for pll reference clock selction */
u8 pll_ref_clk_sel;
/* define for tx power adjust */
#if CONFIG_TXPWR_LIMIT
u8 RegEnableTxPowerLimit;
#endif
u8 RegEnableTxPowerByRate;
u8 target_tx_pwr_valid;
s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];
#if CONFIG_IEEE80211_BAND_5GHZ
s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
#endif
u8 tsf_update_pause_factor;
u8 tsf_update_restore_factor;
s8 TxBBSwing_2G;
s8 TxBBSwing_5G;
u8 AmplifierType_2G;
u8 AmplifierType_5G;
u8 bEn_RFE;
u8 RFE_Type;
u8 PowerTracking_Type;
u8 GLNA_Type;
u8 check_fw_ps;
u8 RegPwrTrimEnable;
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
u8 load_phy_file;
u8 RegDecryptCustomFile;
#endif
#ifdef CONFIG_CONCURRENT_MODE
u8 virtual_iface_num;
#ifdef CONFIG_P2P
u8 sel_p2p_iface;
#endif
#endif
u8 qos_opt_enable;
u8 hiq_filter;
u8 adaptivity_en;
u8 adaptivity_mode;
s8 adaptivity_th_l2h_ini;
s8 adaptivity_th_edcca_hl_diff;
u8 boffefusemask;
BOOLEAN bFileMaskEfuse;
BOOLEAN bBTFileMaskEfuse;
#ifdef CONFIG_RTW_ACS
u8 acs_auto_scan;
u8 acs_mode;
#endif
#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
u8 nm_mode;
#endif
u32 reg_rxgain_offset_2g;
u32 reg_rxgain_offset_5gl;
u32 reg_rxgain_offset_5gm;
u32 reg_rxgain_offset_5gh;
#ifdef CONFIG_DFS_MASTER
u8 dfs_region_domain;
#endif
#ifdef CONFIG_MCC_MODE
u8 en_mcc;
u32 rtw_mcc_single_tx_cri;
u32 rtw_mcc_ap_bw20_target_tx_tp;
u32 rtw_mcc_ap_bw40_target_tx_tp;
u32 rtw_mcc_ap_bw80_target_tx_tp;
u32 rtw_mcc_sta_bw20_target_tx_tp;
u32 rtw_mcc_sta_bw40_target_tx_tp;
u32 rtw_mcc_sta_bw80_target_tx_tp;
s8 rtw_mcc_policy_table_idx;
u8 rtw_mcc_duration;
u8 rtw_mcc_enable_runtime_duration;
u8 rtw_mcc_phydm_offload;
#endif /* CONFIG_MCC_MODE */
#ifdef CONFIG_RTW_NAPI
u8 en_napi;
#ifdef CONFIG_RTW_NAPI_DYNAMIC
u32 napi_threshold; /* unit: Mbps */
#endif /* CONFIG_RTW_NAPI_DYNAMIC */
#ifdef CONFIG_RTW_GRO
u8 en_gro;
#endif /* CONFIG_RTW_GRO */
#endif /* CONFIG_RTW_NAPI */
#ifdef CONFIG_WOWLAN
u8 wakeup_event;
u8 suspend_type;
#endif
#ifdef CONFIG_SUPPORT_TRX_SHARED
u8 trx_share_mode;
#endif
u8 check_hw_status;
u8 wowlan_sta_mix_mode;
#ifdef CONFIG_PCI_HCI
u32 pci_aspm_config;
u32 pci_dynamic_aspm_linkctrl;
#endif
u8 iqk_fw_offload;
u8 ch_switch_offload;
#ifdef CONFIG_TDLS
u8 en_tdls;
#endif
#ifdef CONFIG_ADVANCE_OTA
u8 adv_ota;
#endif
#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
u8 fw_param_init;
#endif
#ifdef CONFIG_DYNAMIC_SOML
u8 dyn_soml_en;
u8 dyn_soml_train_num;
u8 dyn_soml_interval;
u8 dyn_soml_period;
u8 dyn_soml_delay;
#endif
#ifdef CONFIG_FW_HANDLE_TXBCN
u8 fw_tbtt_rpt;
#endif
#ifdef DBG_LA_MODE
u8 la_mode_en;
#endif
u32 phydm_ability;
u32 halrf_ability;
#ifdef CONFIG_TDMADIG
u8 tdmadig_en;
u8 tdmadig_mode;
u8 tdmadig_dynamic;
#endif/*CONFIG_TDMADIG*/
#ifdef CONFIG_RTW_MESH
u8 peer_alive_based_preq;
#endif
/*
* vht_2g4: use VHT rate on 2.4G or not
* 0: deny
* 1: allow
*/
u8 vht_2g4;
};
/* For registry parameters */
#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field))
#define RGTRY_SZ(field) sizeof(((struct registry_priv *) 0)->field)
#define GetRegAmplifierType2G(_Adapter) (_Adapter->registrypriv.AmplifierType_2G)
#define GetRegAmplifierType5G(_Adapter) (_Adapter->registrypriv.AmplifierType_5G)
#define GetRegTxBBSwing_2G(_Adapter) (_Adapter->registrypriv.TxBBSwing_2G)
#define GetRegTxBBSwing_5G(_Adapter) (_Adapter->registrypriv.TxBBSwing_5G)
#define GetRegbENRFEType(_Adapter) (_Adapter->registrypriv.bEn_RFE)
#define GetRegRFEType(_Adapter) (_Adapter->registrypriv.RFE_Type)
#define GetRegGLNAType(_Adapter) (_Adapter->registrypriv.GLNA_Type)
#define GetRegPowerTrackingType(_Adapter) (_Adapter->registrypriv.PowerTracking_Type)
#define WOWLAN_IS_STA_MIX_MODE(_Adapter) (_Adapter->registrypriv.wowlan_sta_mix_mode)
#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field))
#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)
#ifdef CONFIG_80211N_HT
#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)
#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)
#else
#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20
#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20
#endif
#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))
#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))
#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)
#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)
#define rtw_is_vht_2g4(adapter) ((adapter)->registrypriv.vht_2g4 != 0)
#define rtw_set_vht_2g4(adapter, enable) \
((adapter)->registrypriv.vht_2g4 = (enable ? 1 : 0))
typedef struct rtw_if_operations {
int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,
size_t len, bool fixed);
int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf,
size_t len, bool fixed);
} RTW_IF_OPS, *PRTW_IF_OPS;
#ifdef CONFIG_SDIO_HCI
#include <drv_types_sdio.h>
#define INTF_DATA SDIO_DATA
#define INTF_OPS PRTW_IF_OPS
#elif defined(CONFIG_GSPI_HCI)
#include <drv_types_gspi.h>
#define INTF_DATA GSPI_DATA
#elif defined(CONFIG_PCI_HCI)
#include <drv_types_pci.h>
#endif
#define get_hw_port(adapter) (adapter->hw_port)
#ifdef CONFIG_CONCURRENT_MODE
#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
#define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)
#else
#define is_primary_adapter(adapter) (1)
#define is_vir_adapter(adapter) (0)
#endif
#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])
#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
#define GetDefaultAdapter(padapter) padapter
enum _IFACE_ID {
IFACE_ID0, /*PRIMARY_ADAPTER*/
IFACE_ID1,
IFACE_ID2,
IFACE_ID3,
IFACE_ID4,
IFACE_ID5,
IFACE_ID6,
IFACE_ID7,
IFACE_ID_MAX,
};
#define VIF_START_ID 1
#ifdef CONFIG_DBG_COUNTER
struct rx_logs {
u32 intf_rx;
u32 intf_rx_err_recvframe;
u32 intf_rx_err_skb;
u32 intf_rx_report;
u32 core_rx;
u32 core_rx_pre;
u32 core_rx_pre_ver_err;
u32 core_rx_pre_mgmt;
u32 core_rx_pre_mgmt_err_80211w;
u32 core_rx_pre_mgmt_err;
u32 core_rx_pre_ctrl;
u32 core_rx_pre_ctrl_err;
u32 core_rx_pre_data;
u32 core_rx_pre_data_wapi_seq_err;
u32 core_rx_pre_data_wapi_key_err;
u32 core_rx_pre_data_handled;
u32 core_rx_pre_data_err;
u32 core_rx_pre_data_unknown;
u32 core_rx_pre_unknown;
u32 core_rx_enqueue;
u32 core_rx_dequeue;
u32 core_rx_post;
u32 core_rx_post_decrypt;
u32 core_rx_post_decrypt_wep;
u32 core_rx_post_decrypt_tkip;
u32 core_rx_post_decrypt_aes;
u32 core_rx_post_decrypt_wapi;
u32 core_rx_post_decrypt_hw;
u32 core_rx_post_decrypt_unknown;
u32 core_rx_post_decrypt_err;
u32 core_rx_post_defrag_err;
u32 core_rx_post_portctrl_err;
u32 core_rx_post_indicate;
u32 core_rx_post_indicate_in_oder;
u32 core_rx_post_indicate_reoder;
u32 core_rx_post_indicate_err;
u32 os_indicate;
u32 os_indicate_ap_mcast;
u32 os_indicate_ap_forward;
u32 os_indicate_ap_self;
u32 os_indicate_err;
u32 os_netif_ok;
u32 os_netif_err;
};
struct tx_logs {
u32 os_tx;
u32 os_tx_err_up;
u32 os_tx_err_xmit;
u32 os_tx_m2u;
u32 os_tx_m2u_ignore_fw_linked;
u32 os_tx_m2u_ignore_self;
u32 os_tx_m2u_entry;
u32 os_tx_m2u_entry_err_xmit;
u32 os_tx_m2u_entry_err_skb;
u32 os_tx_m2u_stop;
u32 core_tx;
u32 core_tx_err_pxmitframe;
u32 core_tx_err_brtx;
u32 core_tx_upd_attrib;
u32 core_tx_upd_attrib_adhoc;
u32 core_tx_upd_attrib_sta;
u32 core_tx_upd_attrib_ap;
u32 core_tx_upd_attrib_unknown;
u32 core_tx_upd_attrib_dhcp;
u32 core_tx_upd_attrib_icmp;
u32 core_tx_upd_attrib_active;
u32 core_tx_upd_attrib_err_ucast_sta;
u32 core_tx_upd_attrib_err_ucast_ap_link;
u32 core_tx_upd_attrib_err_sta;
u32 core_tx_upd_attrib_err_link;
u32 core_tx_upd_attrib_err_sec;
u32 core_tx_ap_enqueue_warn_fwstate;
u32 core_tx_ap_enqueue_warn_sta;
u32 core_tx_ap_enqueue_warn_nosta;
u32 core_tx_ap_enqueue_warn_link;
u32 core_tx_ap_enqueue_warn_trigger;
u32 core_tx_ap_enqueue_mcast;
u32 core_tx_ap_enqueue_ucast;
u32 core_tx_ap_enqueue;
u32 intf_tx;
u32 intf_tx_pending_ac;
u32 intf_tx_pending_fw_under_survey;
u32 intf_tx_pending_fw_under_linking;
u32 intf_tx_pending_xmitbuf;
u32 intf_tx_enqueue;
u32 core_tx_enqueue;
u32 core_tx_enqueue_class;
u32 core_tx_enqueue_class_err_sta;
u32 core_tx_enqueue_class_err_nosta;
u32 core_tx_enqueue_class_err_fwlink;
u32 intf_tx_direct;
u32 intf_tx_direct_err_coalesce;
u32 intf_tx_dequeue;
u32 intf_tx_dequeue_err_coalesce;
u32 intf_tx_dump_xframe;
u32 intf_tx_dump_xframe_err_txdesc;
u32 intf_tx_dump_xframe_err_port;
};
struct int_logs {
u32 all;
u32 err;
u32 tbdok;
u32 tbder;
u32 bcnderr;
u32 bcndma;
u32 bcndma_e;
u32 rx;
u32 rx_rdu;
u32 rx_fovw;
u32 txfovw;
u32 mgntok;
u32 highdok;
u32 bkdok;
u32 bedok;
u32 vidok;
u32 vodok;
};
#endif /* CONFIG_DBG_COUNTER */
struct debug_priv {
u32 dbg_sdio_free_irq_error_cnt;
u32 dbg_sdio_alloc_irq_error_cnt;
u32 dbg_sdio_free_irq_cnt;
u32 dbg_sdio_alloc_irq_cnt;
u32 dbg_sdio_deinit_error_cnt;
u32 dbg_sdio_init_error_cnt;
u32 dbg_suspend_error_cnt;
u32 dbg_suspend_cnt;
u32 dbg_resume_cnt;
u32 dbg_resume_error_cnt;
u32 dbg_deinit_fail_cnt;
u32 dbg_carddisable_cnt;
u32 dbg_carddisable_error_cnt;
u32 dbg_ps_insuspend_cnt;
u32 dbg_dev_unload_inIPS_cnt;
u32 dbg_wow_leave_ps_fail_cnt;
u32 dbg_scan_pwr_state_cnt;
u32 dbg_downloadfw_pwr_state_cnt;
u32 dbg_fw_read_ps_state_fail_cnt;
u32 dbg_leave_ips_fail_cnt;
u32 dbg_leave_lps_fail_cnt;
u32 dbg_h2c_leave32k_fail_cnt;
u32 dbg_diswow_dload_fw_fail_cnt;
u32 dbg_enwow_dload_fw_fail_cnt;
u32 dbg_ips_drvopen_fail_cnt;
u32 dbg_poll_fail_cnt;
u32 dbg_rpwm_toogle_cnt;
u32 dbg_rpwm_timeout_fail_cnt;
u32 dbg_sreset_cnt;
u32 dbg_fw_mem_dl_error_cnt;
u64 dbg_rx_fifo_last_overflow;
u64 dbg_rx_fifo_curr_overflow;
u64 dbg_rx_fifo_diff_overflow;
};
struct rtw_traffic_statistics {
/* tx statistics */
u64 tx_bytes;
u64 tx_pkts;
u64 tx_drop;
u64 cur_tx_bytes;
u64 last_tx_bytes;
u32 cur_tx_tp; /* Tx throughput in Mbps. */
/* rx statistics */
u64 rx_bytes;
u64 rx_pkts;
u64 rx_drop;
u64 cur_rx_bytes;
u64 last_rx_bytes;
u32 cur_rx_tp; /* Rx throughput in Mbps. */
};
#define SEC_CAP_CHK_BMC BIT0
#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0
struct sec_cam_bmp {
u32 m0;
#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
u32 m1;
#endif
#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
u32 m2;
#endif
#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
u32 m3;
#endif
};
struct cam_ctl_t {
_lock lock;
u8 sec_cap;
u32 flags;
u8 num;
struct sec_cam_bmp used;
_mutex sec_cam_access_mutex;
};
struct sec_cam_ent {
u16 ctrl;
u8 mac[ETH_ALEN];
u8 key[16];
};
#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
#define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
#define RTW_DEFAULT_MGMT_MACID 1
struct macid_bmp {
u32 m0;
#if (MACID_NUM_SW_LIMIT > 32)
u32 m1;
#endif
#if (MACID_NUM_SW_LIMIT > 64)
u32 m2;
#endif
#if (MACID_NUM_SW_LIMIT > 96)
u32 m3;
#endif
};
#ifdef CONFIG_CLIENT_PORT_CFG
struct clt_port_t{
_lock lock;
u8 bmp;
s8 num;
};
#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)
#endif
struct macid_ctl_t {
_lock lock;
u8 num;
struct macid_bmp used;
struct macid_bmp bmc;
struct macid_bmp if_g[CONFIG_IFACE_NUMBER];
struct macid_bmp ch_g[2]; /* 2 ch concurrency */
u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/
u8 h2c_msr[MACID_NUM_SW_LIMIT];
u8 bw[MACID_NUM_SW_LIMIT];
u8 vht_en[MACID_NUM_SW_LIMIT];
u32 rate_bmp0[MACID_NUM_SW_LIMIT];
u32 rate_bmp1[MACID_NUM_SW_LIMIT];
u8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */
struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */
/* macid sleep registers */
#ifdef CONFIG_PROTSEL_MACSLEEP
u16 reg_sleep_ctrl;
u16 reg_sleep_info;
#else
u16 reg_sleep_m0;
#if (MACID_NUM_SW_LIMIT > 32)
u16 reg_sleep_m1;
#endif
#if (MACID_NUM_SW_LIMIT > 64)
u16 reg_sleep_m2;
#endif
#if (MACID_NUM_SW_LIMIT > 96)
u16 reg_sleep_m3;
#endif
#endif
};
/* used for rf_ctl_t.rate_bmp_cck_ofdm */
#define RATE_BMP_CCK 0x000F
#define RATE_BMP_OFDM 0xFFF0
#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK)
#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_OFDM)
#define RATE_BMP_GET_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK)
#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm) ((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4)
/* used for rf_ctl_t.rate_bmp_ht_by_bw */
#define RATE_BMP_HT_1SS 0x000000FF
#define RATE_BMP_HT_2SS 0x0000FF00
#define RATE_BMP_HT_3SS 0x00FF0000
#define RATE_BMP_HT_4SS 0xFF000000
#define RATE_BMP_HAS_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS)
#define RATE_BMP_HAS_HT_2SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_2SS)
#define RATE_BMP_HAS_HT_3SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_3SS)
#define RATE_BMP_HAS_HT_4SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_4SS)
#define RATE_BMP_GET_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS)
#define RATE_BMP_GET_HT_2SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_2SS) >> 8)
#define RATE_BMP_GET_HT_3SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_3SS) >> 16)
#define RATE_BMP_GET_HT_4SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_4SS) >> 24)
/* used for rf_ctl_t.rate_bmp_vht_by_bw */
#define RATE_BMP_VHT_1SS 0x00000003FF
#define RATE_BMP_VHT_2SS 0x00000FFC00
#define RATE_BMP_VHT_3SS 0x003FF00000
#define RATE_BMP_VHT_4SS 0xFFC0000000
#define RATE_BMP_HAS_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS)
#define RATE_BMP_HAS_VHT_2SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_2SS)
#define RATE_BMP_HAS_VHT_3SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_3SS)
#define RATE_BMP_HAS_VHT_4SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_4SS)
#define RATE_BMP_GET_VHT_1SS(_bmp_vht) ((u16)(_bmp_vht & RATE_BMP_VHT_1SS))
#define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_2SS) >> 10))
#define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_3SS) >> 20))
#define RATE_BMP_GET_VHT_4SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_4SS) >> 30))
#define TXPWR_LMT_REF_VHT_FROM_HT BIT0
#define TXPWR_LMT_REF_HT_FROM_VHT BIT1
#define TXPWR_LMT_HAS_CCK_1T BIT0
#define TXPWR_LMT_HAS_CCK_2T BIT1
#define TXPWR_LMT_HAS_CCK_3T BIT2
#define TXPWR_LMT_HAS_CCK_4T BIT3
#define TXPWR_LMT_HAS_OFDM_1T BIT4
#define TXPWR_LMT_HAS_OFDM_2T BIT5
#define TXPWR_LMT_HAS_OFDM_3T BIT6
#define TXPWR_LMT_HAS_OFDM_4T BIT7
#define OFFCHS_NONE 0
#define OFFCHS_LEAVING_OP 1
#define OFFCHS_LEAVE_OP 2
#define OFFCHS_BACKING_OP 3
struct rf_ctl_t {
const struct country_chplan *country_ent;
u8 ChannelPlan;
u8 max_chan_nums;
RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
struct p2p_channels channel_list;
_mutex offch_mutex;
u8 offch_state;
/* used for debug or by tx power limit */
u16 rate_bmp_cck_ofdm; /* 20MHz */
u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */
u64 rate_bmp_vht_by_bw[4]; /* 20MHz, 40MHz, 80MHz, 160MHz. 4SS supported */
#if CONFIG_TXPWR_LIMIT
u8 highest_ht_rate_bw_bmp;
u8 highest_vht_rate_bw_bmp;
_mutex txpwr_lmt_mutex;
_list reg_exc_list;
u8 regd_exc_num;
_list txpwr_lmt_list;
u8 txpwr_regd_num;
const char *regd_name;
u8 txpwr_lmt_2g_cck_ofdm_state;
#if CONFIG_IEEE80211_BAND_5GHZ
u8 txpwr_lmt_5g_cck_ofdm_state;
u8 txpwr_lmt_5g_20_40_ref;
#endif
#endif
bool ch_sel_within_same_band;
#if CONFIG_DFS
u8 csa_ch;
#ifdef CONFIG_DFS_MASTER
u8 dfs_region_domain;
_timer radar_detect_timer;
bool radar_detect_by_others;
u8 radar_detect_enabled;
bool radar_detected;
u8 radar_detect_ch;
u8 radar_detect_bw;
u8 radar_detect_offset;
systime cac_start_time;
systime cac_end_time;
u8 cac_force_stop;
#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
u8 dfs_slave_with_rd;
#endif
u8 dfs_ch_sel_d_flags;
u8 dbg_dfs_fake_radar_detect_cnt;
u8 dbg_dfs_radar_detect_trigger_non;
u8 dbg_dfs_choose_dfs_ch_first;
#endif /* CONFIG_DFS_MASTER */
#endif /* CONFIG_DFS */
};
#define RTW_CAC_STOPPED 0
#ifdef CONFIG_DFS_MASTER
#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)
#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))
#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))
#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)
#else