-
Notifications
You must be signed in to change notification settings - Fork 198
Issues: chipsalliance/verible
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
linter: Add lint rule for DFF name suffixes
enhancement
New feature or request
style-linter
Verilog style-linter issues
#1913
opened May 10, 2023 by
sifferman
ReadTheDocs CI throws ImportError with urllib
documentation
Improvements or additions to documentation
#1910
opened May 5, 2023 by
jbylicki
Autoc-ompletion feature request
language-server
Language server related issues
#1905
opened May 3, 2023 by
adibis
Auto-push to chipsalliance/homebrew-verible from CI
package management
General support for external package managers
#1904
opened May 2, 2023 by
hzeller
syntax error at token "`elsif"
formatter
Verilog code formatter issues
#1893
opened Apr 26, 2023 by
skazarynau1
different formatting of return and non-return functions
bug
Something isn't working
formatter
Verilog code formatter issues
#1892
opened Apr 25, 2023 by
skazarynau1
formatting failed to converge
bug
Something isn't working
formatter
Verilog code formatter issues
#1891
opened Apr 25, 2023 by
skazarynau1
Instantiations Wrapped with One Port
formatter
Verilog code formatter issues
#1889
opened Apr 24, 2023 by
bkueffle
verible-verilog-format fails verification with macro
formatter
Verilog code formatter issues
#1883
opened Apr 22, 2023 by
nathanbeckmann
Use tabs for indentation instead of spaces
enhancement
New feature or request
formatter
Verilog code formatter issues
#1859
opened Apr 9, 2023 by
hrivu21
Build fails needs the c++20 flag
build system
matters pertaining to building Verible
#1856
opened Apr 5, 2023 by
yurivict
Bracket position depends on comment length
formatter
Verilog code formatter issues
#1855
opened Apr 4, 2023 by
skazarynau1
format long for with commas
formatter
Verilog code formatter issues
#1854
opened Apr 4, 2023 by
skazarynau1
alignment by equals sign (feature req)
formatter
Verilog code formatter issues
#1853
opened Apr 4, 2023 by
skazarynau1
No indent on a new line in a function call with macro
formatter
Verilog code formatter issues
#1852
opened Apr 4, 2023 by
skazarynau1
[Discussion] Smoke Test improvement roadmap
help wanted
Extra attention is needed
#1839
opened Mar 28, 2023 by
jbylicki
Sequence rejects clocking event as invalid syntax
rejects-valid syntax
If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1838
opened Mar 28, 2023 by
jbylicki
Macro call inside preprocessor control flow causes syntax erros
rejects-valid syntax
If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1837
opened Mar 28, 2023 by
jbylicki
Cannot go to module instantiation definition when file is located in different path
language-server
Language server related issues
#1834
opened Mar 24, 2023 by
miguelcruz97
Option to have alignment only apply to blocks of code
formatter
Verilog code formatter issues
#1832
opened Mar 24, 2023 by
patrickrst
linter: Add rule for spaces around binary operators
enhancement
New feature or request
style-linter
Verilog style-linter issues
#1829
opened Mar 23, 2023 by
glatosinski
linter: Add rule for allowing ASCII characters
enhancement
New feature or request
style-linter
Verilog style-linter issues
#1828
opened Mar 23, 2023 by
glatosinski
ProTip!
Type g p on any issue or pull request to go back to the pull request listing page.