PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

Verilog AXI components for FPGA implementation

Verilog PCI express components

An open source GPU based off of the AMD Southern Islands ISA.

An Open-source FPGA IP Generator

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A High-performance Timing Analysis Tool for VLSI Systems

Verilog I2C interface for FPGA implementation

iCESugar FPGA Board (base on iCE40UP5k)

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog SDRAM memory controller

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OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

SystemC/TLM-2.0 Co-simulation framework

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

A 32-bit Microcontroller featuring a RISC-V core

IEEE 754 floating point unit in Verilog

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

Graphics demos

Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

8051 core

Parallel Array of Simple Cores. Multicore processor.

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.

OpenSPARC-based SoC

Test for video output using the ADV7513 chip on a de10 nano board

Altera Cyclone IV FPGA project for the PCIe LimeSDR board

Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.