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SystemC/TLM-2.0 Co-simulation framework
Verilog I2C interface for FPGA implementation
SystemVerilog VIP for AMBA APB protocol
Tenjin is a very fast and full-featured template engine available in Python, Ruby, PHP, Perl, and JS
Tutorial for integrating PyMTL and Vivado HLS
HDL IP manager with similar capabilities as software package managers.
NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
VS Code extension api 공식 문서의 한글 번역입니다.
Publication-ready NN-architecture schematics.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
A diagramming framework for the web
[ 웹에 날개를 달아주는 성능 최적화 기법 ] 을 함께 읽으며 공부하는 스터디입니다. (2021.12.08 ~ 2022.03.16)
Sample code illustrating the VS Code extension API.
Language server protocol implementation for VSCode. This allows implementing language services in JS/TS running on node.js
Defines a common protocol for language servers.
Eclipse Layout Kernel - Automatic layout for Java applications.