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Why RISC-V up_testset use lr/sc and not amoswap? #6569
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The implementation is same as you want: |
@xiaoxiang781216 the issue is that currently it is implemented as you pointed, but it use
But can be something like
|
Sorry, I misunderstand your meaning. |
Maybe my suggestion has some drawbacks compared to current implementation so I'm posting this as an issue so people some discussion may happen |
@pkarashchenko |
The RISC-V supports "Atomic Memory Operations" instructions. Seems like up_testset can be implemented with the less number of instruction using
amoswap.w.aq
/amoswap.w.rl
than current implementation that uselr
/sc
instructions.The text was updated successfully, but these errors were encountered: