diff --git a/pnr/output/UART.def b/pnr/output/UART.def deleted file mode 100644 index 4b7c7ec..0000000 --- a/pnr/output/UART.def +++ /dev/null @@ -1,8315 +0,0 @@ -# -# IC Compiler II write_def -# Release : O-2018.06-SP1 -# User Name : ICer -# Date : Wed Apr 24 19:58:08 2024 -# -# This DEF file was generated with the -include_tech_via_definitions option, -# which includes all library technology via definitions (i.e., contact codes). -# Undetermined results will occur if this file is read into any database. -# -VERSION 5.7 ; -DIVIDERCHAR "/" ; -BUSBITCHARS "[]" ; -DESIGN UART ; -UNITS DISTANCE MICRONS 1000 ; -PROPERTYDEFINITIONS -COMPONENTPIN ACCESS_DIRECTION STRING ; -END PROPERTYDEFINITIONS -DIEAREA ( 0 0 ) ( 0 47800 ) ( 48712 47800 ) ( 48712 0 ) ; -ROW unit_row_1 unit 3000 3000 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_2 unit 3000 4672 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_3 unit 3000 6344 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_4 unit 3000 8016 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_5 unit 3000 9688 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_6 unit 3000 11360 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_7 unit 3000 13032 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_8 unit 3000 14704 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_9 unit 3000 16376 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_10 unit 3000 18048 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_11 unit 3000 19720 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_12 unit 3000 21392 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_13 unit 3000 23064 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_14 unit 3000 24736 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_15 unit 3000 26408 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_16 unit 3000 28080 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_17 unit 3000 29752 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_18 unit 3000 31424 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_19 unit 3000 33096 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_20 unit 3000 34768 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_21 unit 3000 36440 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_22 unit 3000 38112 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_23 unit 3000 39784 FS DO 281 BY 1 STEP 152 0 ; -ROW unit_row_24 unit 3000 41456 N DO 281 BY 1 STEP 152 0 ; -ROW unit_row_25 unit 3000 43128 FS DO 281 BY 1 STEP 152 0 ; -TRACKS Y 112 DO 314 STEP 152 LAYER M1 ; -TRACKS X 112 DO 320 STEP 152 LAYER M1 ; -TRACKS Y 112 DO 314 STEP 152 LAYER M2 ; -TRACKS X 112 DO 320 STEP 152 LAYER M2 ; -TRACKS Y 264 DO 157 STEP 304 LAYER M3 ; -TRACKS X 264 DO 160 STEP 304 LAYER M3 ; -TRACKS Y 264 DO 157 STEP 304 LAYER M4 ; -TRACKS X 264 DO 160 STEP 304 LAYER M4 ; -TRACKS Y 568 DO 78 STEP 608 LAYER M5 ; -TRACKS X 568 DO 80 STEP 608 LAYER M5 ; -TRACKS Y 568 DO 78 STEP 608 LAYER M6 ; -TRACKS X 568 DO 80 STEP 608 LAYER M6 ; -TRACKS Y 568 DO 39 STEP 1216 LAYER M7 ; -TRACKS X 568 DO 40 STEP 1216 LAYER M7 ; -TRACKS Y 568 DO 39 STEP 1216 LAYER M8 ; -TRACKS X 568 DO 40 STEP 1216 LAYER M8 ; -TRACKS Y 568 DO 20 STEP 2432 LAYER M9 ; -TRACKS X 568 DO 20 STEP 2432 LAYER M9 ; -TRACKS Y 3000 DO 10 STEP 4864 LAYER MRDL ; -TRACKS X 3000 DO 10 STEP 4864 LAYER MRDL ; -VIAS 67 ; - - VIA12SQ_C - + RECT M1 ( -55 -30 ) ( 55 30 ) - + RECT VIA1 ( -25 -25 ) ( 25 25 ) - + RECT M2 ( -30 -55 ) ( 30 55 ) ; - - VIA12BAR_C - + RECT M1 ( -55 -55 ) ( 55 55 ) - + RECT VIA1 ( -25 -50 ) ( 25 50 ) - + RECT M2 ( -30 -80 ) ( 30 80 ) ; - - VIA12LG_C - + RECT M1 ( -80 -55 ) ( 80 55 ) - + RECT VIA1 ( -50 -50 ) ( 50 50 ) - + RECT M2 ( -80 -55 ) ( 80 55 ) ; - - VIA12SQ - + RECT M1 ( -55 -30 ) ( 55 30 ) - + RECT VIA1 ( -25 -25 ) ( 25 25 ) - + RECT M2 ( -55 -30 ) ( 55 30 ) ; - - VIA12BAR - + RECT M1 ( -55 -55 ) ( 55 55 ) - + RECT VIA1 ( -25 -50 ) ( 25 50 ) - + RECT M2 ( -55 -55 ) ( 55 55 ) ; - - VIA12LG - + RECT M1 ( -80 -55 ) ( 80 55 ) - + RECT VIA1 ( -50 -50 ) ( 50 50 ) - + RECT M2 ( -80 -55 ) ( 80 55 ) ; - - VIA23SQ_C - + RECT M2 ( -55 -30 ) ( 55 30 ) - + RECT VIA2 ( -25 -25 ) ( 25 25 ) - + RECT M3 ( -30 -55 ) ( 30 55 ) ; - - VIA23BAR_C - + RECT M2 ( -55 -55 ) ( 55 55 ) - + RECT VIA2 ( -25 -50 ) ( 25 50 ) - + RECT M3 ( -30 -80 ) ( 30 80 ) ; - - VIA23LG_C - + RECT M2 ( -80 -55 ) ( 80 55 ) - + RECT VIA2 ( -50 -50 ) ( 50 50 ) - + RECT M3 ( -80 -55 ) ( 80 55 ) ; - - VIA23SQ - + RECT M2 ( -55 -30 ) ( 55 30 ) - + RECT VIA2 ( -25 -25 ) ( 25 25 ) - + RECT M3 ( -55 -30 ) ( 55 30 ) ; - - VIA23BAR - + RECT M2 ( -55 -55 ) ( 55 55 ) - + RECT VIA2 ( -25 -50 ) ( 25 50 ) - + RECT M3 ( -55 -55 ) ( 55 55 ) ; - - VIA23LG - + RECT M2 ( -80 -55 ) ( 80 55 ) - + RECT VIA2 ( -50 -50 ) ( 50 50 ) - + RECT M3 ( -80 -55 ) ( 80 55 ) ; - - VIA34SQ_C - + RECT M3 ( -55 -30 ) ( 55 30 ) - + RECT VIA3 ( -25 -25 ) ( 25 25 ) - + RECT M4 ( -30 -55 ) ( 30 55 ) ; - - VIA34BAR_C - + RECT M3 ( -55 -55 ) ( 55 55 ) - + RECT VIA3 ( -25 -50 ) ( 25 50 ) - + RECT M4 ( -30 -80 ) ( 30 80 ) ; - - VIA34LG_C - + RECT M3 ( -80 -55 ) ( 80 55 ) - + RECT VIA3 ( -50 -50 ) ( 50 50 ) - + RECT M4 ( -80 -55 ) ( 80 55 ) ; - - VIA34SQ - + RECT M3 ( -55 -30 ) ( 55 30 ) - + RECT VIA3 ( -25 -25 ) ( 25 25 ) - + RECT M4 ( -55 -30 ) ( 55 30 ) ; - - VIA34BAR - + RECT M3 ( -55 -55 ) ( 55 55 ) - + RECT VIA3 ( -25 -50 ) ( 25 50 ) - + RECT M4 ( -55 -55 ) ( 55 55 ) ; - - VIA34LG - + RECT M3 ( -80 -55 ) ( 80 55 ) - + RECT VIA3 ( -50 -50 ) ( 50 50 ) - + RECT M4 ( -80 -55 ) ( 80 55 ) ; - - VIA45SQ_C - + RECT M4 ( -55 -30 ) ( 55 30 ) - + RECT VIA4 ( -25 -25 ) ( 25 25 ) - + RECT M5 ( -30 -55 ) ( 30 55 ) ; - - VIA45BAR_C - + RECT M4 ( -55 -55 ) ( 55 55 ) - + RECT VIA4 ( -25 -50 ) ( 25 50 ) - + RECT M5 ( -30 -80 ) ( 30 80 ) ; - - VIA45LG_C - + RECT M4 ( -80 -55 ) ( 80 55 ) - + RECT VIA4 ( -50 -50 ) ( 50 50 ) - + RECT M5 ( -80 -55 ) ( 80 55 ) ; - - VIA45SQ - + RECT M4 ( -55 -30 ) ( 55 30 ) - + RECT VIA4 ( -25 -25 ) ( 25 25 ) - + RECT M5 ( -55 -30 ) ( 55 30 ) ; - - VIA45BAR - + RECT M4 ( -55 -55 ) ( 55 55 ) - + RECT VIA4 ( -25 -50 ) ( 25 50 ) - + RECT M5 ( -55 -55 ) ( 55 55 ) ; - - VIA45LG - + RECT M4 ( -80 -55 ) ( 80 55 ) - + RECT VIA4 ( -50 -50 ) ( 50 50 ) - + RECT M5 ( -80 -55 ) ( 80 55 ) ; - - VIA56SQ_C - + RECT M5 ( -55 -30 ) ( 55 30 ) - + RECT VIA5 ( -25 -25 ) ( 25 25 ) - + RECT M6 ( -30 -55 ) ( 30 55 ) ; - - VIA56BAR_C - + RECT M5 ( -55 -55 ) ( 55 55 ) - + RECT VIA5 ( -25 -50 ) ( 25 50 ) - + RECT M6 ( -30 -80 ) ( 30 80 ) ; - - VIA56LG_C - + RECT M5 ( -80 -55 ) ( 80 55 ) - + RECT VIA5 ( -50 -50 ) ( 50 50 ) - + RECT M6 ( -80 -55 ) ( 80 55 ) ; - - VIA56SQ - + RECT M5 ( -55 -30 ) ( 55 30 ) - + RECT VIA5 ( -25 -25 ) ( 25 25 ) - + RECT M6 ( -55 -30 ) ( 55 30 ) ; - - VIA56BAR - + RECT M5 ( -55 -55 ) ( 55 55 ) - + RECT VIA5 ( -25 -50 ) ( 25 50 ) - + RECT M6 ( -55 -55 ) ( 55 55 ) ; - - VIA56LG - + RECT M5 ( -80 -55 ) ( 80 55 ) - + RECT VIA5 ( -50 -50 ) ( 50 50 ) - + RECT M6 ( -80 -55 ) ( 80 55 ) ; - - VIA67SQ_C - + RECT M6 ( -55 -30 ) ( 55 30 ) - + RECT VIA6 ( -25 -25 ) ( 25 25 ) - + RECT M7 ( -30 -55 ) ( 30 55 ) ; - - VIA67BAR_C - + RECT M6 ( -55 -55 ) ( 55 55 ) - + RECT VIA6 ( -25 -50 ) ( 25 50 ) - + RECT M7 ( -30 -80 ) ( 30 80 ) ; - - VIA67LG_C - + RECT M6 ( -80 -55 ) ( 80 55 ) - + RECT VIA6 ( -50 -50 ) ( 50 50 ) - + RECT M7 ( -80 -55 ) ( 80 55 ) ; - - VIA67SQ - + RECT M6 ( -55 -30 ) ( 55 30 ) - + RECT VIA6 ( -25 -25 ) ( 25 25 ) - + RECT M7 ( -55 -30 ) ( 55 30 ) ; - - VIA67BAR - + RECT M6 ( -55 -55 ) ( 55 55 ) - + RECT VIA6 ( -25 -50 ) ( 25 50 ) - + RECT M7 ( -55 -55 ) ( 55 55 ) ; - - VIA67LG - + RECT M6 ( -80 -55 ) ( 80 55 ) - + RECT VIA6 ( -50 -50 ) ( 50 50 ) - + RECT M7 ( -80 -55 ) ( 80 55 ) ; - - VIA78SQ_C - + RECT M7 ( -55 -30 ) ( 55 30 ) - + RECT VIA7 ( -25 -25 ) ( 25 25 ) - + RECT M8 ( -30 -55 ) ( 30 55 ) ; - - VIA78BAR_C - + RECT M7 ( -55 -55 ) ( 55 55 ) - + RECT VIA7 ( -25 -50 ) ( 25 50 ) - + RECT M8 ( -30 -80 ) ( 30 80 ) ; - - VIA78LG_C - + RECT M7 ( -80 -55 ) ( 80 55 ) - + RECT VIA7 ( -50 -50 ) ( 50 50 ) - + RECT M8 ( -80 -55 ) ( 80 55 ) ; - - VIA78SQ - + RECT M7 ( -55 -30 ) ( 55 30 ) - + RECT VIA7 ( -25 -25 ) ( 25 25 ) - + RECT M8 ( -55 -30 ) ( 55 30 ) ; - - VIA78BAR - + RECT M7 ( -55 -55 ) ( 55 55 ) - + RECT VIA7 ( -25 -50 ) ( 25 50 ) - + RECT M8 ( -55 -55 ) ( 55 55 ) ; - - VIA78LG - + RECT M7 ( -80 -55 ) ( 80 55 ) - + RECT VIA7 ( -50 -50 ) ( 50 50 ) - + RECT M8 ( -80 -55 ) ( 80 55 ) ; - - VIA89_C - + RECT M8 ( -95 -80 ) ( 95 80 ) - + RECT VIA8 ( -65 -65 ) ( 65 65 ) - + RECT M9 ( -80 -95 ) ( 80 95 ) ; - - VIA89 - + RECT M8 ( -95 -80 ) ( 95 80 ) - + RECT VIA8 ( -65 -65 ) ( 65 65 ) - + RECT M9 ( -95 -80 ) ( 95 80 ) ; - - VIA9RDL - + RECT M9 ( -1500 -1500 ) ( 1500 1500 ) - + RECT VIARDL ( -1000 -1000 ) ( 1000 1000 ) - + RECT MRDL ( -1500 -1500 ) ( 1500 1500 ) ; - - VIA12SQ_C_1_2 + VIARULE VIA12SQ_C - + CUTSIZE 50 50 - + LAYERS M1 VIA1 M2 - + CUTSPACING 70 70 - + ENCLOSURE 30 5 5 30 - + ROWCOL 1 2 - + PATTERN 1_C ; - - VIA78LG_C_3_2 + VIARULE VIA78LG_C - + CUTSIZE 100 100 - + LAYERS M7 VIA7 M8 - + CUTSPACING 86 86 - + ENCLOSURE 30 5 30 5 - + ROWCOL 3 2 - + PATTERN 3_C ; - - cts_w2_s2_vlg_VIA12LG_1_1 + VIARULE VIA12LG - + CUTSIZE 100 100 - + LAYERS M1 VIA1 M2 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA12LG_C_1_1 + VIARULE VIA12LG_C - + CUTSIZE 100 100 - + LAYERS M1 VIA1 M2 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA23LG_1_1 + VIARULE VIA23LG - + CUTSIZE 100 100 - + LAYERS M2 VIA2 M3 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA23LG_C_1_1 + VIARULE VIA23LG_C - + CUTSIZE 100 100 - + LAYERS M2 VIA2 M3 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA34LG_1_1 + VIARULE VIA34LG - + CUTSIZE 100 100 - + LAYERS M3 VIA3 M4 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA34LG_C_1_1 + VIARULE VIA34LG_C - + CUTSIZE 100 100 - + LAYERS M3 VIA3 M4 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA45LG_1_1 + VIARULE VIA45LG - + CUTSIZE 100 100 - + LAYERS M4 VIA4 M5 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA45LG_C_1_1 + VIARULE VIA45LG_C - + CUTSIZE 100 100 - + LAYERS M4 VIA4 M5 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA56LG_1_1 + VIARULE VIA56LG - + CUTSIZE 100 100 - + LAYERS M5 VIA5 M6 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_VIA56LG_C_1_1 + VIARULE VIA56LG_C - + CUTSIZE 100 100 - + LAYERS M5 VIA5 M6 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA12LG_1_1 + VIARULE VIA12LG - + CUTSIZE 100 100 - + LAYERS M1 VIA1 M2 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA12LG_C_1_1 + VIARULE VIA12LG_C - + CUTSIZE 100 100 - + LAYERS M1 VIA1 M2 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA23LG_1_1 + VIARULE VIA23LG - + CUTSIZE 100 100 - + LAYERS M2 VIA2 M3 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA23LG_C_1_1 + VIARULE VIA23LG_C - + CUTSIZE 100 100 - + LAYERS M2 VIA2 M3 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA34LG_1_1 + VIARULE VIA34LG - + CUTSIZE 100 100 - + LAYERS M3 VIA3 M4 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA34LG_C_1_1 + VIARULE VIA34LG_C - + CUTSIZE 100 100 - + LAYERS M3 VIA3 M4 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA45LG_1_1 + VIARULE VIA45LG - + CUTSIZE 100 100 - + LAYERS M4 VIA4 M5 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA45LG_C_1_1 + VIARULE VIA45LG_C - + CUTSIZE 100 100 - + LAYERS M4 VIA4 M5 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA56LG_1_1 + VIARULE VIA56LG - + CUTSIZE 100 100 - + LAYERS M5 VIA5 M6 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; - - cts_w2_s2_vlg_ext_spacing_VIA56LG_C_1_1 + VIARULE VIA56LG_C - + CUTSIZE 100 100 - + LAYERS M5 VIA5 M6 - + CUTSPACING 85 85 - + ENCLOSURE 30 5 30 5 - + PATTERN 1_8 ; -END VIAS -NONDEFAULTRULES 5 ; - - cts_w2_s2_vlg - + HARDSPACING - + LAYER M1 WIDTH 100 SPACING 50 - + LAYER M2 WIDTH 110 SPACING 160 - + LAYER M3 WIDTH 110 SPACING 450 - + LAYER M4 WIDTH 110 SPACING 450 - + LAYER M5 WIDTH 110 SPACING 1100 - + LAYER M6 WIDTH 56 SPACING 56 - + LAYER M7 WIDTH 56 SPACING 56 - + LAYER M8 WIDTH 56 SPACING 56 - + LAYER M9 WIDTH 160 SPACING 160 - + LAYER MRDL WIDTH 2000 SPACING 2000 - + VIA cts_w2_s2_vlg_VIA12LG_C_1_1 - + VIA cts_w2_s2_vlg_VIA12LG_1_1 - + VIA cts_w2_s2_vlg_VIA23LG_C_1_1 - + VIA cts_w2_s2_vlg_VIA23LG_1_1 - + VIA cts_w2_s2_vlg_VIA34LG_C_1_1 - + VIA cts_w2_s2_vlg_VIA34LG_1_1 - + VIA cts_w2_s2_vlg_VIA45LG_C_1_1 - + VIA cts_w2_s2_vlg_VIA45LG_1_1 - + VIA cts_w2_s2_vlg_VIA56LG_C_1_1 - + VIA cts_w2_s2_vlg_VIA56LG_1_1 ; - - cts_w1_s2 - + HARDSPACING - + LAYER M1 WIDTH 50 SPACING 50 - + LAYER M2 WIDTH 56 SPACING 160 - + LAYER M3 WIDTH 56 SPACING 450 - + LAYER M4 WIDTH 56 SPACING 450 - + LAYER M5 WIDTH 56 SPACING 1100 - + LAYER M6 WIDTH 56 SPACING 56 - + LAYER M7 WIDTH 56 SPACING 56 - + LAYER M8 WIDTH 56 SPACING 56 - + LAYER M9 WIDTH 160 SPACING 160 - + LAYER MRDL WIDTH 2000 SPACING 2000 ; - - default_rule_equivalent_ndr_double_spacing - + HARDSPACING - + LAYER M1 WIDTH 50 SPACING 50 - + LAYER M2 WIDTH 56 SPACING 56 - + LAYER M3 WIDTH 56 SPACING 56 - + LAYER M4 WIDTH 56 SPACING 112 - + LAYER M5 WIDTH 56 SPACING 112 - + LAYER M6 WIDTH 56 SPACING 56 - + LAYER M7 WIDTH 56 SPACING 56 - + LAYER M8 WIDTH 56 SPACING 56 - + LAYER M9 WIDTH 160 SPACING 160 - + LAYER MRDL WIDTH 2000 SPACING 2000 ; - - cts_w2_s2_vlg_ext_spacing - + HARDSPACING - + LAYER M1 WIDTH 100 SPACING 50 - + LAYER M2 WIDTH 110 SPACING 160 - + LAYER M3 WIDTH 110 SPACING 450 - + LAYER M4 WIDTH 110 SPACING 506 - + LAYER M5 WIDTH 110 SPACING 1156 - + LAYER M6 WIDTH 56 SPACING 56 - + LAYER M7 WIDTH 56 SPACING 56 - + LAYER M8 WIDTH 56 SPACING 56 - + LAYER M9 WIDTH 160 SPACING 160 - + LAYER MRDL WIDTH 2000 SPACING 2000 - + VIA cts_w2_s2_vlg_ext_spacing_VIA12LG_C_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA12LG_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA23LG_C_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA23LG_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA34LG_C_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA34LG_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA45LG_C_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA45LG_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA56LG_C_1_1 - + VIA cts_w2_s2_vlg_ext_spacing_VIA56LG_1_1 ; - - cts_w1_s2_ext_spacing - + HARDSPACING - + LAYER M1 WIDTH 50 SPACING 50 - + LAYER M2 WIDTH 56 SPACING 160 - + LAYER M3 WIDTH 56 SPACING 450 - + LAYER M4 WIDTH 56 SPACING 506 - + LAYER M5 WIDTH 56 SPACING 1156 - + LAYER M6 WIDTH 56 SPACING 56 - + LAYER M7 WIDTH 56 SPACING 56 - + LAYER M8 WIDTH 56 SPACING 56 - + LAYER M9 WIDTH 160 SPACING 160 - + LAYER MRDL WIDTH 2000 SPACING 2000 ; -END NONDEFAULTRULES -COMPONENTS 501 ; - - HFSBUF_156_0 NBUFFX8_RVT + PLACED ( 21240 41456 ) FN ; - - U0_mux2X1/U1 MUX21X2_RVT + PLACED ( 29600 34768 ) N ; - - U1_mux2X1/U1 MUX21X2_RVT + PLACED ( 28992 14704 ) N ; - - U2_mux2X1/U1 MUX21X1_RVT + PLACED ( 21848 3000 ) FS ; - - U0_UART_RX/HFSBUF_432_1 NBUFFX8_RVT + PLACED ( 20024 4672 ) FN ; - - U0_UART_TX/U0_fsm/current_state_reg_0_ SDFFARX1_RVT + PLACED ( 40240 3000 ) FS ; - - U0_UART_TX/U0_fsm/current_state_reg_1_ SDFFARX1_RVT + PLACED ( 40240 6344 ) FS ; - - U0_UART_TX/U0_fsm/current_state_reg_2_ SDFFARX1_RVT + PLACED ( 34160 11360 ) N ; - - U0_UART_TX/U0_fsm/busy_reg SDFFARX1_RVT + PLACED ( 35224 4672 ) N ; - - U0_UART_TX/U0_fsm/U9 NOR3X0_RVT + PLACED ( 39632 11360 ) FN ; - - U0_UART_TX/U0_fsm/U10 OA21X1_RVT + PLACED ( 37808 14704 ) FN ; - - U0_UART_TX/U0_fsm/U11 OA21X1_RVT + PLACED ( 40696 9688 ) S ; - - U0_UART_TX/U0_fsm/U12 AND2X1_RVT + PLACED ( 39632 8016 ) N ; - - U0_UART_TX/U0_fsm/U13 AO22X1_RVT + PLACED ( 37656 8016 ) FN ; - - U0_UART_TX/U0_fsm/U14 OR2X1_RVT + PLACED ( 38568 3000 ) S ; - - U0_UART_TX/U0_fsm/U15 AO21X1_RVT + PLACED ( 44040 8016 ) N ; - - U0_UART_TX/U0_fsm/U16 AO22X1_RVT + PLACED ( 41608 11360 ) FN ; - - U0_UART_TX/U0_fsm/U17 AO21X1_RVT + PLACED ( 41456 4672 ) FN ; - - U0_UART_TX/U0_fsm/U18 AND3X1_RVT + PLACED ( 39024 9688 ) S ; - - U0_UART_TX/U0_fsm/U19 AND2X1_RVT + PLACED ( 42216 8016 ) FN ; - - U0_UART_TX/U0_fsm/U20 AO21X1_RVT + PLACED ( 43432 9688 ) FS ; - - U0_UART_TX/U0_fsm/U21 AND2X1_RVT + PLACED ( 44040 4672 ) FN ; - - U0_UART_TX/U0_fsm/U7 INVX1_RVT + PLACED ( 44344 11360 ) FN ; - - U0_UART_TX/U0_fsm/U8 INVX1_RVT + PLACED ( 40088 14704 ) FN ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_7_ SDFFARX1_RVT + PLACED ( 13944 3000 ) FS ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_6_ SDFFARX1_RVT + PLACED ( 14856 6344 ) FS ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_5_ SDFFARX1_RVT + PLACED ( 15768 8016 ) N ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_4_ SDFFARX1_RVT + PLACED ( 24584 6344 ) FS ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_3_ SDFFARX1_RVT + PLACED ( 26712 3000 ) FS ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_2_ SDFFARX1_RVT + PLACED ( 33704 6344 ) FS ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_1_ SDFFARX1_RVT + PLACED ( 33096 9688 ) FS ; - - U0_UART_TX/U0_Serializer/DATA_V_reg_0_ SDFFARX1_RVT + PLACED ( 33248 13032 ) FS ; - - U0_UART_TX/U0_Serializer/ser_count_reg_0_ SDFFARX1_RVT + PLACED ( 34464 19720 ) FS ; - - U0_UART_TX/U0_Serializer/ser_count_reg_1_ SDFFARX1_RVT + PLACED ( 35224 23064 ) FS ; - - U0_UART_TX/U0_Serializer/ser_count_reg_2_ SDFFARX1_RVT + PLACED ( 40240 19720 ) FS ; - - U0_UART_TX/U0_Serializer/U18 AND3X1_RVT + PLACED ( 40392 18048 ) FN ; - - U0_UART_TX/U0_Serializer/U19 AO222X1_RVT + PLACED ( 29448 8016 ) N ; - - U0_UART_TX/U0_Serializer/U20 AO22X1_RVT + PLACED ( 23216 4672 ) FN ; - - U0_UART_TX/U0_Serializer/U21 AO222X1_RVT + PLACED ( 22000 6344 ) S ; - - U0_UART_TX/U0_Serializer/U22 AO222X1_RVT + PLACED ( 21240 8016 ) FN ; - - U0_UART_TX/U0_Serializer/U23 AO222X1_RVT + PLACED ( 23520 8016 ) N ; - - U0_UART_TX/U0_Serializer/U24 AO222X1_RVT + PLACED ( 28992 4672 ) FN ; - - U0_UART_TX/U0_Serializer/U25 AO222X1_RVT + PLACED ( 30968 6344 ) FS ; - - U0_UART_TX/U0_Serializer/U26 AO222X1_RVT + PLACED ( 31576 8016 ) N ; - - U0_UART_TX/U0_Serializer/U27 AND2X1_RVT + PLACED ( 33096 4672 ) FN ; - - U0_UART_TX/U0_Serializer/U28 NAND2X0_RVT + PLACED ( 35376 8016 ) N ; - - U0_UART_TX/U0_Serializer/U29 NAND2X0_RVT + PLACED ( 35376 3000 ) S ; - - U0_UART_TX/U0_Serializer/U30 AO21X1_RVT + PLACED ( 43432 21392 ) FN ; - - U0_UART_TX/U0_Serializer/U31 AND4X1_RVT + PLACED ( 44192 23064 ) S ; - - U0_UART_TX/U0_Serializer/U32 AO21X1_RVT + PLACED ( 41304 21392 ) N ; - - U0_UART_TX/U0_Serializer/U33 AND2X1_RVT + PLACED ( 39936 21392 ) FN ; - - U0_UART_TX/U0_Serializer/U34 AND2X1_RVT + PLACED ( 37808 21392 ) FN ; - - U0_UART_TX/U0_Serializer/U14 INVX1_RVT + PLACED ( 32944 6344 ) S ; - - U0_UART_TX/U0_Serializer/U15 INVX1_RVT + PLACED ( 32184 3000 ) S ; - - U0_UART_TX/U0_Serializer/U16 INVX1_RVT + PLACED ( 37048 3000 ) S ; - - U0_UART_TX/U0_Serializer/U17 XNOR2X1_RVT + PLACED ( 41456 23064 ) S ; - - U0_UART_TX/U0_mux/OUT_reg SDFFARX1_RVT + PLACED ( 40240 16376 ) FS ; - - U0_UART_TX/U0_mux/U6 AO22X1_RVT + PLACED ( 44192 14704 ) FN ; - - U0_UART_TX/U0_mux/U7 AO22X1_RVT + PLACED ( 41608 13032 ) FS ; - - U0_UART_TX/U0_mux/U8 AO22X1_RVT + PLACED ( 41912 14704 ) N ; - - U0_UART_TX/U0_mux/U4 INVX1_RVT + PLACED ( 43584 13032 ) S ; - - U0_UART_TX/U0_mux/U5 INVX1_RVT + PLACED ( 44648 13032 ) S ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ SDFFARX1_RVT + PLACED ( 17896 14704 ) N ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ SDFFARX1_RVT + PLACED ( 21088 16376 ) FS ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ SDFFARX1_RVT + PLACED ( 17136 13032 ) FS ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ SDFFARX1_RVT + PLACED ( 15464 9688 ) FS ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ SDFFARX1_RVT + PLACED ( 28080 19720 ) FS ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ SDFFARX1_RVT + PLACED ( 27320 16376 ) FS ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ SDFFARX1_RVT + PLACED ( 27016 13032 ) FS ; - - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ SDFFARX1_RVT + PLACED ( 24736 9688 ) FS ; - - U0_UART_TX/U0_parity_calc/parity_reg SDFFARX1_RVT + PLACED ( 34768 16376 ) FS ; - - U0_UART_TX/U0_parity_calc/U2 AO22X1_RVT + PLACED ( 36896 18048 ) FN ; - - U0_UART_TX/U0_parity_calc/U3 XNOR3X1_RVT + PLACED ( 32032 18048 ) FN ; - - U0_UART_TX/U0_parity_calc/U4 XNOR3X1_RVT + PLACED ( 23216 18048 ) N ; - - U0_UART_TX/U0_parity_calc/U9 AO22X1_RVT + PLACED ( 25040 11360 ) FN ; - - U0_UART_TX/U0_parity_calc/U11 AO22X1_RVT + PLACED ( 27472 11360 ) FN ; - - U0_UART_TX/U0_parity_calc/U13 AO22X1_RVT + PLACED ( 25952 14704 ) N ; - - U0_UART_TX/U0_parity_calc/U15 AO22X1_RVT + PLACED ( 27624 18048 ) N ; - - U0_UART_TX/U0_parity_calc/U17 AO22X1_RVT + PLACED ( 21848 9688 ) FS ; - - U0_UART_TX/U0_parity_calc/U19 AO22X1_RVT + PLACED ( 19872 11360 ) FN ; - - U0_UART_TX/U0_parity_calc/U21 AO22X1_RVT + PLACED ( 23520 14704 ) FN ; - - U0_UART_TX/U0_parity_calc/U23 AO22X1_RVT + PLACED ( 25040 13032 ) FS ; - - U0_UART_TX/U0_parity_calc/U5 INVX1_RVT + PLACED ( 23672 9688 ) FS ; - - U0_UART_TX/U0_parity_calc/U6 XNOR3X1_RVT + PLACED ( 32032 14704 ) N ; - - U0_UART_TX/U0_parity_calc/U7 XNOR2X1_RVT + PLACED ( 30056 11360 ) N ; - - U0_UART_TX/U0_parity_calc/U8 XOR2X1_RVT + PLACED ( 22000 11360 ) N ; - - U0_UART_TX/U0_parity_calc/U10 NAND2X0_RVT + PLACED ( 33096 3000 ) S ; - - U0_UART_TX/U0_parity_calc/U12 INVX1_RVT + PLACED ( 34464 3000 ) S ; - - U0_UART_TX/U0_parity_calc/U14 INVX1_RVT + PLACED ( 39632 18048 ) FN ; - - HFSBUF_223_2 NBUFFX8_RVT + PLACED ( 24736 4672 ) N ; - - U0_UART_RX/U0_uart_fsm/current_state_reg_0_ SDFFARX1_RVT + PLACED ( 27472 28080 ) N ; - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_ SDFFARX1_RVT + PLACED ( 33704 26408 ) FS ; - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_ SDFFARX1_RVT + PLACED ( 27472 33096 ) FS ; - - U0_UART_RX/U0_uart_fsm/U4 INVX1_RVT + PLACED ( 6952 23064 ) FS ; - - U0_UART_RX/U0_uart_fsm/U5 INVX1_RVT + PLACED ( 4216 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U6 INVX1_RVT + PLACED ( 3000 18048 ) N ; - - U0_UART_RX/U0_uart_fsm/U9 INVX1_RVT + PLACED ( 10752 26408 ) FS ; - - U0_UART_RX/U0_uart_fsm/U10 XNOR2X1_RVT + PLACED ( 5128 9688 ) FS ; - - U0_UART_RX/U0_uart_fsm/U11 OR2X1_RVT + PLACED ( 5280 8016 ) N ; - - U0_UART_RX/U0_uart_fsm/U12 XNOR2X1_RVT + PLACED ( 4368 4672 ) N ; - - U0_UART_RX/U0_uart_fsm/U13 OR2X1_RVT + PLACED ( 3760 8016 ) N ; - - U0_UART_RX/U0_uart_fsm/U14 XNOR2X1_RVT + PLACED ( 3456 6344 ) FS ; - - U0_UART_RX/U0_uart_fsm/U15 OR2X1_RVT + PLACED ( 3760 16376 ) S ; - - U0_UART_RX/U0_uart_fsm/U16 XNOR2X1_RVT + PLACED ( 6800 19720 ) FS ; - - U0_UART_RX/U0_uart_fsm/U17 INVX0_RVT + PLACED ( 13032 19720 ) FS ; - - U0_UART_RX/U0_uart_fsm/U18 OR2X1_RVT + PLACED ( 5736 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U19 AO21X1_RVT + PLACED ( 6952 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U20 OR2X1_RVT + PLACED ( 3000 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U21 AO21X1_RVT + PLACED ( 4976 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U22 NOR2X0_RVT + PLACED ( 3000 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U23 AO21X1_RVT + PLACED ( 4216 23064 ) FS ; - - U0_UART_RX/U0_uart_fsm/U24 XNOR2X1_RVT + PLACED ( 3456 19720 ) FS ; - - U0_UART_RX/U0_uart_fsm/U25 NAND2X0_RVT + PLACED ( 5432 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U26 XNOR2X1_RVT + PLACED ( 6648 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U27 INVX0_RVT + PLACED ( 34768 33096 ) S ; - - U0_UART_RX/U0_uart_fsm/U28 AND2X1_RVT + PLACED ( 35680 29752 ) FS ; - - U0_UART_RX/U0_uart_fsm/U29 NAND2X0_RVT + PLACED ( 34008 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U30 NAND3X0_RVT + PLACED ( 32184 24736 ) FN ; - - U0_UART_RX/U0_uart_fsm/U31 MUX21X1_RVT + PLACED ( 32944 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U32 AND2X1_RVT + PLACED ( 31424 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U33 AO21X1_RVT + PLACED ( 34160 29752 ) S ; - - U0_UART_RX/U0_uart_fsm/U34 AO21X1_RVT + PLACED ( 32640 29752 ) FS ; - - U0_UART_RX/U0_uart_fsm/U35 INVX0_RVT + PLACED ( 34008 33096 ) S ; - - U0_UART_RX/U0_uart_fsm/U36 AO221X1_RVT + PLACED ( 27776 26408 ) S ; - - U0_UART_RX/U0_uart_fsm/U37 NAND2X0_RVT + PLACED ( 27472 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U38 NAND4X0_RVT + PLACED ( 18656 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U39 AND4X1_RVT + PLACED ( 16680 23064 ) FS ; - - U0_UART_RX/U0_uart_fsm/U40 AND3X1_RVT + PLACED ( 30816 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U41 NAND2X0_RVT + PLACED ( 21544 23064 ) FS ; - - U0_UART_RX/U0_uart_fsm/U42 XNOR2X1_RVT + PLACED ( 15768 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U43 INVX0_RVT + PLACED ( 34920 24736 ) FN ; - - U0_UART_RX/U0_uart_fsm/U44 NAND2X0_RVT + PLACED ( 36592 24736 ) FN ; - - U0_UART_RX/U0_uart_fsm/U45 INVX0_RVT + PLACED ( 31424 29752 ) FS ; - - U0_UART_RX/U0_uart_fsm/U46 XNOR2X1_RVT + PLACED ( 12728 26408 ) FS ; - - U0_UART_RX/U0_uart_fsm/U47 AND3X1_RVT + PLACED ( 13488 6344 ) FS ; - - U0_UART_RX/U0_uart_fsm/U48 XNOR2X1_RVT + PLACED ( 10904 6344 ) FS ; - - U0_UART_RX/U0_uart_fsm/U49 XNOR2X1_RVT + PLACED ( 11816 4672 ) N ; - - U0_UART_RX/U0_uart_fsm/U50 XNOR2X1_RVT + PLACED ( 9536 19720 ) FS ; - - U0_UART_RX/U0_uart_fsm/U51 XNOR2X1_RVT + PLACED ( 12728 8016 ) N ; - - U0_UART_RX/U0_uart_fsm/U52 MUX21X1_RVT + PLACED ( 28536 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U53 INVX0_RVT + PLACED ( 30208 18048 ) FN ; - - U0_UART_RX/U0_uart_fsm/U54 AO21X1_RVT + PLACED ( 32336 31424 ) FN ; - - U0_UART_RX/U0_uart_fsm/U55 OR2X1_RVT + PLACED ( 29904 31424 ) N ; - - U0_UART_RX/U0_uart_fsm/U56 AND4X1_RVT + PLACED ( 31880 26408 ) FS ; - - U0_UART_RX/U0_uart_fsm/U57 INVX0_RVT + PLACED ( 30816 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U58 NAND3X0_RVT + PLACED ( 29752 24736 ) FN ; - - U0_UART_RX/U0_uart_fsm/U59 INVX0_RVT + PLACED ( 28840 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U60 NOR2X0_RVT + PLACED ( 16376 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U61 NAND4X0_RVT + PLACED ( 11664 23064 ) FS ; - - U0_UART_RX/U0_uart_fsm/U62 XNOR2X1_RVT + PLACED ( 8168 23064 ) FS ; - - U0_UART_RX/U0_uart_fsm/U63 XNOR2X1_RVT + PLACED ( 10296 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U64 XNOR2X1_RVT + PLACED ( 12880 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U65 XNOR2X1_RVT + PLACED ( 11360 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U66 NAND4X0_RVT + PLACED ( 15464 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U67 INVX0_RVT + PLACED ( 18200 23064 ) S ; - - U0_UART_RX/U0_uart_fsm/U68 INVX0_RVT + PLACED ( 18504 24736 ) FN ; - - U0_UART_RX/U0_uart_fsm/U69 XNOR2X1_RVT + PLACED ( 13032 21392 ) N ; - - U0_UART_RX/U0_uart_fsm/U70 XNOR2X1_RVT + PLACED ( 8776 24736 ) N ; - - U0_UART_RX/U0_uart_fsm/U71 INVX0_RVT + PLACED ( 27016 29752 ) FS ; - - U0_UART_RX/U0_uart_fsm/U72 INVX0_RVT + PLACED ( 30664 26408 ) S ; - - U0_UART_RX/U0_uart_fsm/U73 NAND2X0_RVT + PLACED ( 25952 29752 ) S ; - - U0_UART_RX/U0_uart_fsm/U74 NAND2X0_RVT + PLACED ( 30512 29752 ) FS ; - - U0_UART_RX/U0_uart_fsm/U75 AND3X1_RVT + PLACED ( 34768 28080 ) N ; - - U0_UART_RX/U0_uart_fsm/U76 NOR3X0_RVT + PLACED ( 43584 28080 ) N ; - - U0_UART_RX/U0_uart_fsm/U77 NAND3X0_RVT + PLACED ( 32944 28080 ) N ; - - U0_UART_RX/U0_uart_fsm/U78 NAND2X0_RVT + PLACED ( 26560 33096 ) FS ; - - U0_UART_RX/U0_uart_fsm/U79 AO21X1_RVT + PLACED ( 28232 29752 ) S ; - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ SDFFARX1_RVT + PLACED ( 16376 29752 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ SDFFARX1_RVT + PLACED ( 16680 43128 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ SDFFARX1_RVT + PLACED ( 15312 26408 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ SDFFARX1_RVT + PLACED ( 16832 33096 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ SDFFARX1_RVT + PLACED ( 16376 36440 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ SDFFARX1_RVT + PLACED ( 15768 39784 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ SDFFARX1_RVT + PLACED ( 21848 31424 ) N ; - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ SDFFARX1_RVT + PLACED ( 21848 28080 ) N ; - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ SDFFARX1_RVT + PLACED ( 23064 23064 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ SDFFARX1_RVT + PLACED ( 22456 21392 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U16 NAND2X0_RVT + PLACED ( 22608 19720 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U17 NAND4X0_RVT + PLACED ( 19872 19720 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U18 AND2X1_RVT + PLACED ( 20328 18048 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U19 AO21X1_RVT + PLACED ( 21088 19720 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U20 AO21X1_RVT + PLACED ( 20024 23064 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U21 AND2X1_RVT + PLACED ( 19264 24736 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U22 AO22X1_RVT + PLACED ( 22608 24736 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U23 NOR2X0_RVT + PLACED ( 25040 24736 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U24 AO21X1_RVT + PLACED ( 25648 26408 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U25 AO22X1_RVT + PLACED ( 23064 26408 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U26 AND3X1_RVT + PLACED ( 20784 24736 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U27 AO21X1_RVT + PLACED ( 20784 26408 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U28 AO22X1_RVT + PLACED ( 22912 29752 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U29 AND2X1_RVT + PLACED ( 20480 31424 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U30 AND2X1_RVT + PLACED ( 16376 41456 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U31 AND2X1_RVT + PLACED ( 15464 38112 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U32 AND2X1_RVT + PLACED ( 16680 38112 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U33 AND2X1_RVT + PLACED ( 17136 34768 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U34 AND2X1_RVT + PLACED ( 16224 31424 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U35 AND2X1_RVT + PLACED ( 18200 31424 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U36 OR2X1_RVT + PLACED ( 18656 19720 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_1 HADDX1_RVT + PLACED ( 14096 31424 ) N ; - - U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_2 HADDX1_RVT + PLACED ( 14704 33096 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_3 HADDX1_RVT + PLACED ( 14248 36440 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_4 HADDX1_RVT + PLACED ( 13488 39784 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U6 INVX1_RVT + PLACED ( 20632 28080 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U14 INVX1_RVT + PLACED ( 21392 21392 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U15 INVX1_RVT + PLACED ( 17440 16376 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U37 INVX1_RVT + PLACED ( 8016 16376 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U38 INVX1_RVT + PLACED ( 6800 13032 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U39 INVX1_RVT + PLACED ( 5736 3000 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U40 OR2X1_RVT + PLACED ( 6648 16376 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U41 AO21X1_RVT + PLACED ( 10296 18048 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U42 OR2X1_RVT + PLACED ( 6648 14704 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U43 AO21X1_RVT + PLACED ( 7864 14704 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U44 NOR2X0_RVT + PLACED ( 6648 6344 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U45 AO21X1_RVT + PLACED ( 8168 6344 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U46 XNOR2X1_RVT + PLACED ( 7560 3000 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U47 NAND2X0_RVT + PLACED ( 7256 4672 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U48 XNOR2X1_RVT + PLACED ( 7560 8016 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U49 XOR2X1_RVT + PLACED ( 13488 43128 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U50 XNOR2X1_RVT + PLACED ( 10144 8016 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U51 XNOR2X1_RVT + PLACED ( 10752 13032 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U52 XNOR2X1_RVT + PLACED ( 9232 4672 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U53 NAND3X0_RVT + PLACED ( 12120 9688 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U54 XOR2X1_RVT + PLACED ( 13792 13032 ) FS ; - - U0_UART_RX/U0_edge_bit_counter/U55 NOR2X0_RVT + PLACED ( 17592 18048 ) N ; - - U0_UART_RX/U0_edge_bit_counter/U56 OA22X1_RVT + PLACED ( 18352 16376 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U57 AND2X1_RVT + PLACED ( 14400 18048 ) FN ; - - U0_UART_RX/U0_edge_bit_counter/U58 OA22X1_RVT + PLACED ( 15920 16376 ) S ; - - U0_UART_RX/U0_edge_bit_counter/U59 NOR4X0_RVT + PLACED ( 15464 14704 ) N ; - - U0_UART_RX/U0_data_sampling/Samples_reg_2_ SDFFARX1_RVT + PLACED ( 22152 34768 ) N ; - - U0_UART_RX/U0_data_sampling/Samples_reg_1_ SDFFARX1_RVT + PLACED ( 23216 43128 ) FS ; - - U0_UART_RX/U0_data_sampling/Samples_reg_0_ SDFFARX1_RVT + PLACED ( 22608 39784 ) FS ; - - U0_UART_RX/U0_data_sampling/sampled_bit_reg SDFFARX1_RVT + PLACED ( 30360 38112 ) N ; - - U0_UART_RX/U0_data_sampling/add_21_U1_1_1 HADDX1_RVT + PLACED ( 4520 33096 ) FS ; - - U0_UART_RX/U0_data_sampling/add_21_U1_1_2 HADDX1_RVT + PLACED ( 5280 31424 ) N ; - - U0_UART_RX/U0_data_sampling/add_21_U1_1_3 HADDX1_RVT + PLACED ( 7864 29752 ) FS ; - - U0_UART_RX/U0_data_sampling/U4 INVX1_RVT + PLACED ( 6496 41456 ) FN ; - - U0_UART_RX/U0_data_sampling/U5 INVX1_RVT + PLACED ( 3000 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U6 INVX1_RVT + PLACED ( 3000 29752 ) FS ; - - U0_UART_RX/U0_data_sampling/U10 INVX1_RVT + PLACED ( 6040 19720 ) FS ; - - U0_UART_RX/U0_data_sampling/U11 INVX0_RVT + PLACED ( 3000 33096 ) FS ; - - U0_UART_RX/U0_data_sampling/U12 OR2X1_RVT + PLACED ( 4520 26408 ) FS ; - - U0_UART_RX/U0_data_sampling/U13 AO21X1_RVT + PLACED ( 3456 31424 ) N ; - - U0_UART_RX/U0_data_sampling/U14 NOR2X0_RVT + PLACED ( 3304 28080 ) N ; - - U0_UART_RX/U0_data_sampling/U15 AO21X1_RVT + PLACED ( 3760 29752 ) FS ; - - U0_UART_RX/U0_data_sampling/U16 XNOR2X1_RVT + PLACED ( 5432 28080 ) N ; - - U0_UART_RX/U0_data_sampling/U17 NAND2X0_RVT + PLACED ( 5888 26408 ) FS ; - - U0_UART_RX/U0_data_sampling/U18 XNOR2X1_RVT + PLACED ( 6800 26408 ) FS ; - - U0_UART_RX/U0_data_sampling/U19 XOR2X1_RVT + PLACED ( 8472 28080 ) N ; - - U0_UART_RX/U0_data_sampling/U20 OR2X1_RVT + PLACED ( 4976 34768 ) FN ; - - U0_UART_RX/U0_data_sampling/U21 AO21X1_RVT + PLACED ( 3000 34768 ) FN ; - - U0_UART_RX/U0_data_sampling/U22 NOR2X0_RVT + PLACED ( 3152 39784 ) FS ; - - U0_UART_RX/U0_data_sampling/U23 AO21X1_RVT + PLACED ( 4216 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U24 XNOR2X1_RVT + PLACED ( 3912 41456 ) N ; - - U0_UART_RX/U0_data_sampling/U25 NAND2X0_RVT + PLACED ( 5584 43128 ) FS ; - - U0_UART_RX/U0_data_sampling/U26 XNOR2X1_RVT + PLACED ( 7256 43128 ) FS ; - - U0_UART_RX/U0_data_sampling/U27 MUX21X1_RVT + PLACED ( 19720 34768 ) N ; - - U0_UART_RX/U0_data_sampling/U28 NOR4X0_RVT + PLACED ( 12576 34768 ) N ; - - U0_UART_RX/U0_data_sampling/U29 XOR2X1_RVT + PLACED ( 9232 33096 ) FS ; - - U0_UART_RX/U0_data_sampling/U30 NAND2X0_RVT + PLACED ( 13488 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U31 NAND4X0_RVT + PLACED ( 12272 31424 ) FN ; - - U0_UART_RX/U0_data_sampling/U32 XNOR2X1_RVT + PLACED ( 9840 29752 ) FS ; - - U0_UART_RX/U0_data_sampling/U33 XNOR2X1_RVT + PLACED ( 11056 28080 ) N ; - - U0_UART_RX/U0_data_sampling/U34 XNOR2X1_RVT + PLACED ( 13792 29752 ) S ; - - U0_UART_RX/U0_data_sampling/U35 XNOR2X1_RVT + PLACED ( 7256 31424 ) N ; - - U0_UART_RX/U0_data_sampling/U36 AND2X1_RVT + PLACED ( 24280 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U37 MUX21X1_RVT + PLACED ( 21392 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U38 AND4X1_RVT + PLACED ( 11512 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U39 AND4X1_RVT + PLACED ( 11968 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U40 XOR2X1_RVT + PLACED ( 9992 34768 ) N ; - - U0_UART_RX/U0_data_sampling/U41 XOR2X1_RVT + PLACED ( 6648 34768 ) N ; - - U0_UART_RX/U0_data_sampling/U42 XOR2X1_RVT + PLACED ( 8776 39784 ) FS ; - - U0_UART_RX/U0_data_sampling/U43 XOR2X1_RVT + PLACED ( 10752 41456 ) N ; - - U0_UART_RX/U0_data_sampling/U44 XOR2X1_RVT + PLACED ( 6344 36440 ) FS ; - - U0_UART_RX/U0_data_sampling/U45 AND2X1_RVT + PLACED ( 24280 38112 ) FN ; - - U0_UART_RX/U0_data_sampling/U46 MUX21X1_RVT + PLACED ( 18808 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U47 NAND4X0_RVT + PLACED ( 10296 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U48 AND3X1_RVT + PLACED ( 9232 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U49 XOR2X1_RVT + PLACED ( 5584 39784 ) FS ; - - U0_UART_RX/U0_data_sampling/U50 INVX0_RVT + PLACED ( 8928 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U51 INVX0_RVT + PLACED ( 14400 38112 ) FN ; - - U0_UART_RX/U0_data_sampling/U52 XOR2X1_RVT + PLACED ( 7256 41456 ) N ; - - U0_UART_RX/U0_data_sampling/U53 INVX0_RVT + PLACED ( 9232 34768 ) FN ; - - U0_UART_RX/U0_data_sampling/U54 XOR2X1_RVT + PLACED ( 11816 33096 ) S ; - - U0_UART_RX/U0_data_sampling/U55 INVX0_RVT + PLACED ( 13032 29752 ) S ; - - U0_UART_RX/U0_data_sampling/U56 XOR2X1_RVT + PLACED ( 3760 36440 ) FS ; - - U0_UART_RX/U0_data_sampling/U57 INVX0_RVT + PLACED ( 7256 33096 ) S ; - - U0_UART_RX/U0_data_sampling/U58 XOR2X1_RVT + PLACED ( 10144 43128 ) S ; - - U0_UART_RX/U0_data_sampling/U59 INVX0_RVT + PLACED ( 12424 39784 ) S ; - - U0_UART_RX/U0_data_sampling/U60 AND2X1_RVT + PLACED ( 22608 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U61 AND2X1_RVT + PLACED ( 26864 36440 ) S ; - - U0_UART_RX/U0_data_sampling/U62 AND2X1_RVT + PLACED ( 27776 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U63 AO22X1_RVT + PLACED ( 25800 38112 ) N ; - - U0_UART_RX/U0_data_sampling/U64 NAND2X0_RVT + PLACED ( 27472 41456 ) FN ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_7_ SDFFARX1_RVT + PLACED ( 40088 31424 ) N ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_6_ SDFFARX1_RVT + PLACED ( 36592 34768 ) N ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_5_ SDFFARX1_RVT + PLACED ( 35376 36440 ) FS ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_4_ SDFFARX1_RVT + PLACED ( 40240 38112 ) N ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_3_ SDFFARX1_RVT + PLACED ( 40240 43128 ) FS ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_2_ SDFFARX1_RVT + PLACED ( 40240 39784 ) FS ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_1_ SDFFARX1_RVT + PLACED ( 28688 43128 ) FS ; - - U0_UART_RX/U0_deserializer/P_DATA_reg_0_ SDFFARX1_RVT + PLACED ( 28232 39784 ) FS ; - - U0_UART_RX/U0_deserializer/U3 AO22X1_RVT + PLACED ( 32792 41456 ) FN ; - - U0_UART_RX/U0_deserializer/U4 AO22X1_RVT + PLACED ( 35224 43128 ) S ; - - U0_UART_RX/U0_deserializer/U6 AO22X1_RVT + PLACED ( 38720 41456 ) N ; - - U0_UART_RX/U0_deserializer/U8 AO22X1_RVT + PLACED ( 38416 39784 ) FS ; - - U0_UART_RX/U0_deserializer/U10 AO22X1_RVT + PLACED ( 38112 38112 ) N ; - - U0_UART_RX/U0_deserializer/U12 AO22X1_RVT + PLACED ( 35984 38112 ) FN ; - - U0_UART_RX/U0_deserializer/U14 AO22X1_RVT + PLACED ( 35072 34768 ) FN ; - - U0_UART_RX/U0_deserializer/U16 AO22X1_RVT + PLACED ( 37200 33096 ) FS ; - - U0_UART_RX/U0_deserializer/U5 INVX1_RVT + PLACED ( 35376 31424 ) N ; - - U0_UART_RX/U0_deserializer/U7 INVX1_RVT + PLACED ( 9384 14704 ) N ; - - U0_UART_RX/U0_deserializer/U9 NAND2X0_RVT + PLACED ( 35528 21392 ) N ; - - U0_UART_RX/U0_deserializer/U11 INVX1_RVT + PLACED ( 13336 16376 ) S ; - - U0_UART_RX/U0_deserializer/U13 INVX1_RVT + PLACED ( 6648 18048 ) N ; - - U0_UART_RX/U0_deserializer/U15 INVX1_RVT + PLACED ( 4520 13032 ) FS ; - - U0_UART_RX/U0_deserializer/U17 INVX1_RVT + PLACED ( 3000 8016 ) N ; - - U0_UART_RX/U0_deserializer/U18 OR2X1_RVT + PLACED ( 4976 16376 ) S ; - - U0_UART_RX/U0_deserializer/U19 AO21X1_RVT + PLACED ( 8776 16376 ) FS ; - - U0_UART_RX/U0_deserializer/U28 OR2X1_RVT + PLACED ( 3152 14704 ) FN ; - - U0_UART_RX/U0_deserializer/U29 AO21X1_RVT + PLACED ( 5128 14704 ) N ; - - U0_UART_RX/U0_deserializer/U30 NOR2X0_RVT + PLACED ( 3000 13032 ) FS ; - - U0_UART_RX/U0_deserializer/U31 AO21X1_RVT + PLACED ( 5280 13032 ) FS ; - - U0_UART_RX/U0_deserializer/U32 XNOR2X1_RVT + PLACED ( 3000 11360 ) N ; - - U0_UART_RX/U0_deserializer/U33 NAND2X0_RVT + PLACED ( 5584 11360 ) N ; - - U0_UART_RX/U0_deserializer/U34 XNOR2X1_RVT + PLACED ( 6496 11360 ) N ; - - U0_UART_RX/U0_deserializer/U35 XNOR2X1_RVT + PLACED ( 8016 13032 ) FS ; - - U0_UART_RX/U0_deserializer/U36 XNOR2X1_RVT + PLACED ( 10144 14704 ) N ; - - U0_UART_RX/U0_deserializer/U37 XNOR2X1_RVT + PLACED ( 9080 11360 ) N ; - - U0_UART_RX/U0_deserializer/U38 NAND3X0_RVT + PLACED ( 11664 11360 ) N ; - - U0_UART_RX/U0_deserializer/U39 XOR2X1_RVT + PLACED ( 13184 11360 ) FN ; - - U0_UART_RX/U0_deserializer/U40 NOR2X0_RVT + PLACED ( 12576 18048 ) FN ; - - U0_UART_RX/U0_deserializer/U41 OA22X1_RVT + PLACED ( 11816 16376 ) FS ; - - U0_UART_RX/U0_deserializer/U42 AND2X1_RVT + PLACED ( 15616 18048 ) N ; - - U0_UART_RX/U0_deserializer/U43 OA22X1_RVT + PLACED ( 14096 16376 ) S ; - - U0_UART_RX/U0_deserializer/U44 NOR4X0_RVT + PLACED ( 12728 14704 ) N ; - - U0_UART_RX/U0_strt_chk/strt_glitch_reg SDFFARX1_RVT + PLACED ( 28384 36440 ) FS ; - - U0_UART_RX/U0_strt_chk/U2 AO22X1_RVT + PLACED ( 33552 34768 ) FN ; - - U0_UART_RX/U0_strt_chk/U3 INVX1_RVT + PLACED ( 32792 34768 ) N ; - - U0_UART_RX/U0_par_chk/par_err_reg SDFFARX1_RVT + PLACED ( 40240 29752 ) FS ; - - U0_UART_RX/U0_par_chk/U2 AO22X1_RVT + PLACED ( 39936 28080 ) N ; - - U0_UART_RX/U0_par_chk/U3 XNOR3X1_RVT + PLACED ( 36440 31424 ) N ; - - U0_UART_RX/U0_par_chk/U5 XNOR3X1_RVT + PLACED ( 34464 39784 ) FS ; - - U0_UART_RX/U0_par_chk/U7 XNOR3X1_RVT + PLACED ( 42064 34768 ) FN ; - - U0_UART_RX/U0_par_chk/U4 XNOR2X1_RVT + PLACED ( 42976 33096 ) S ; - - U0_UART_RX/U0_par_chk/U6 XNOR2X1_RVT + PLACED ( 37048 43128 ) S ; - - U0_UART_RX/U0_par_chk/U8 XNOR2X1_RVT + PLACED ( 36896 28080 ) N ; - - U0_UART_RX/U0_par_chk/U9 INVX1_RVT + PLACED ( 39176 26408 ) FS ; - - U0_UART_RX/U0_stp_chk/stp_err_reg SDFFARX1_RVT + PLACED ( 39936 26408 ) FS ; - - U0_UART_RX/U0_stp_chk/U2 OAI22X1_RVT + PLACED ( 39480 24736 ) N ; - - U0_UART_RX/U0_stp_chk/U3 INVX1_RVT + PLACED ( 37504 24736 ) N ; - - optlc_1045 TIEH_RVT + PLACED ( 41152 14704 ) N ; - - optlc_1046 TIEL_RVT + PLACED ( 43432 14704 ) N ; - - U1_mux2X1/IN_0_btd306 NBUFFX2_RVT + PLACED ( 19416 3000 ) S ; - - U0_mux2X1/IN_0_btd307 NBUFFX2_RVT + PLACED ( 3000 24736 ) N ; - - xofiller!SHFILL3_RVT!x30000y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 3000 3000 ) FS ; - - xofiller!SHFILL3_RVT!x34560y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 3456 3000 ) FS ; - - xofiller!SHFILL3_RVT!x39120y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 3912 3000 ) FS ; - - xofiller!SHFILL3_RVT!x43680y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 4368 3000 ) FS ; - - xofiller!SHFILL3_RVT!x48240y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 4824 3000 ) FS ; - - xofiller!SHFILL3_RVT!x52800y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 5280 3000 ) FS ; - - xofiller!SHFILL3_RVT!x64960y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 6496 3000 ) FS ; - - xofiller!SHFILL3_RVT!x69520y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 6952 3000 ) FS ; - - xofiller!SHFILL1_RVT!x74080y30000 SHFILL1_RVT + SOURCE DIST + PLACED ( 7408 3000 ) FS ; - - xofiller!SHFILL3_RVT!x110560y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 11056 3000 ) FS ; - - xofiller!SHFILL3_RVT!x115120y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 11512 3000 ) FS ; - - xofiller!SHFILL3_RVT!x119680y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 11968 3000 ) FS ; - - xofiller!SHFILL3_RVT!x124240y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 12424 3000 ) FS ; - - xofiller!SHFILL3_RVT!x128800y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 12880 3000 ) FS ; - - xofiller!SHFILL3_RVT!x133360y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 13336 3000 ) FS ; - - xofiller!SHFILL1_RVT!x137920y30000 SHFILL1_RVT + SOURCE DIST + PLACED ( 13792 3000 ) FS ; - - xofiller!SHFILL3_RVT!x206320y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 20632 3000 ) FS ; - - xofiller!SHFILL3_RVT!x210880y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 21088 3000 ) FS ; - - xofiller!SHFILL2_RVT!x215440y30000 SHFILL2_RVT + SOURCE DIST + PLACED ( 21544 3000 ) FS ; - - xofiller!SHFILL3_RVT!x247360y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 24736 3000 ) FS ; - - xofiller!SHFILL3_RVT!x251920y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 25192 3000 ) FS ; - - xofiller!SHFILL3_RVT!x256480y30000 SHFILL3_RVT + SOURCE DIST + PLACED ( 25648 3000 ) FS ; - - xofiller!SHFILL3_RVT!x30000y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 3000 4672 ) N ; - - xofiller!SHFILL3_RVT!x34560y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 3456 4672 ) N ; - - xofiller!SHFILL3_RVT!x39120y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 3912 4672 ) N ; - - xofiller!SHFILL3_RVT!x86240y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 8624 4672 ) N ; - - xofiller!SHFILL3_RVT!x171360y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 17136 4672 ) N ; - - xofiller!SHFILL3_RVT!x175920y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 17592 4672 ) N ; - - xofiller!SHFILL3_RVT!x180480y46720 SHFILL3_RVT + SOURCE DIST + PLACED ( 18048 4672 ) N ; - - xofiller!SHFILL1_RVT!x438880y46720 SHFILL1_RVT + SOURCE DIST + PLACED ( 43888 4672 ) N ; - - xofiller!SHFILL3_RVT!x30000y63440 SHFILL3_RVT + SOURCE DIST + PLACED ( 3000 6344 ) FS ; - - xofiller!SHFILL2_RVT!x49760y80160 SHFILL2_RVT + SOURCE DIST + PLACED ( 4976 8016 ) N ; - - xofiller!SHFILL3_RVT!x367440y80160 SHFILL3_RVT + SOURCE DIST + PLACED ( 36744 8016 ) N ; - - xofiller!SHFILL3_RVT!x43680y96880 SHFILL3_RVT + SOURCE DIST + PLACED ( 4368 9688 ) FS ; - - xofiller!SHFILL2_RVT!x48240y96880 SHFILL2_RVT + SOURCE DIST + PLACED ( 4824 9688 ) FS ; - - xofiller!SHFILL2_RVT!x233680y96880 SHFILL2_RVT + SOURCE DIST + PLACED ( 23368 9688 ) FS ; - - xofiller!SHFILL3_RVT!x320320y96880 SHFILL3_RVT + SOURCE DIST + PLACED ( 32032 9688 ) FS ; - - xofiller!SHFILL1_RVT!x455600y113600 SHFILL1_RVT + SOURCE DIST + PLACED ( 45560 11360 ) N ; - - xofiller!SHFILL2_RVT!x168320y130320 SHFILL2_RVT + SOURCE DIST + PLACED ( 16832 13032 ) FS ; - - xofiller!SHFILL2_RVT!x443440y130320 SHFILL2_RVT + SOURCE DIST + PLACED ( 44344 13032 ) FS ; - - xofiller!SHFILL2_RVT!x454080y130320 SHFILL2_RVT + SOURCE DIST + PLACED ( 45408 13032 ) FS ; - - xofiller!SHFILL1_RVT!x30000y147040 SHFILL1_RVT + SOURCE DIST + PLACED ( 3000 14704 ) N ; - - xofiller!SHFILL3_RVT!x311200y147040 SHFILL3_RVT + SOURCE DIST + PLACED ( 31120 14704 ) N ; - - xofiller!SHFILL3_RVT!x203280y163760 SHFILL3_RVT + SOURCE DIST + PLACED ( 20328 16376 ) FS ; - - xofiller!SHFILL2_RVT!x207840y163760 SHFILL2_RVT + SOURCE DIST + PLACED ( 20784 16376 ) FS ; - - xofiller!SHFILL3_RVT!x337040y163760 SHFILL3_RVT + SOURCE DIST + PLACED ( 33704 16376 ) FS ; - - xofiller!SHFILL3_RVT!x341600y163760 SHFILL3_RVT + SOURCE DIST + PLACED ( 34160 16376 ) FS ; - - xofiller!SHFILL3_RVT!x51280y180480 SHFILL3_RVT + SOURCE DIST + PLACED ( 5128 18048 ) N ; - - xofiller!SHFILL2_RVT!x122720y180480 SHFILL2_RVT + SOURCE DIST + PLACED ( 12272 18048 ) N ; - - xofiller!SHFILL3_RVT!x191120y180480 SHFILL3_RVT + SOURCE DIST + PLACED ( 19112 18048 ) N ; - - xofiller!SHFILL3_RVT!x449520y180480 SHFILL3_RVT + SOURCE DIST + PLACED ( 44952 18048 ) N ; - - xofiller!SHFILL2_RVT!x454080y180480 SHFILL2_RVT + SOURCE DIST + PLACED ( 45408 18048 ) N ; - - xofiller!SHFILL3_RVT!x30000y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 3000 19720 ) FS ; - - xofiller!SHFILL3_RVT!x156160y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 15616 19720 ) FS ; - - xofiller!SHFILL3_RVT!x160720y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 16072 19720 ) FS ; - - xofiller!SHFILL3_RVT!x165280y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 16528 19720 ) FS ; - - xofiller!SHFILL3_RVT!x169840y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 16984 19720 ) FS ; - - xofiller!SHFILL3_RVT!x174400y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 17440 19720 ) FS ; - - xofiller!SHFILL3_RVT!x178960y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 17896 19720 ) FS ; - - xofiller!SHFILL2_RVT!x183520y197200 SHFILL2_RVT + SOURCE DIST + PLACED ( 18352 19720 ) FS ; - - xofiller!SHFILL3_RVT!x244320y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 24432 19720 ) FS ; - - xofiller!SHFILL3_RVT!x248880y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 24888 19720 ) FS ; - - xofiller!SHFILL3_RVT!x253440y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 25344 19720 ) FS ; - - xofiller!SHFILL3_RVT!x258000y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 25800 19720 ) FS ; - - xofiller!SHFILL3_RVT!x262560y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 26256 19720 ) FS ; - - xofiller!SHFILL3_RVT!x335520y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 33552 19720 ) FS ; - - xofiller!SHFILL3_RVT!x340080y197200 SHFILL3_RVT + SOURCE DIST + PLACED ( 34008 19720 ) FS ; - - xofiller!SHFILL3_RVT!x92320y213920 SHFILL3_RVT + SOURCE DIST + PLACED ( 9232 21392 ) N ; - - xofiller!SHFILL3_RVT!x96880y213920 SHFILL3_RVT + SOURCE DIST + PLACED ( 9688 21392 ) N ; - - xofiller!SHFILL1_RVT!x101440y213920 SHFILL1_RVT + SOURCE DIST + PLACED ( 10144 21392 ) N ; - - xofiller!SHFILL3_RVT!x335520y213920 SHFILL3_RVT + SOURCE DIST + PLACED ( 33552 21392 ) N ; - - xofiller!SHFILL3_RVT!x340080y213920 SHFILL3_RVT + SOURCE DIST + PLACED ( 34008 21392 ) N ; - - xofiller!SHFILL3_RVT!x373520y213920 SHFILL3_RVT + SOURCE DIST + PLACED ( 37352 21392 ) N ; - - xofiller!SHFILL1_RVT!x183520y247360 SHFILL1_RVT + SOURCE DIST + PLACED ( 18352 24736 ) N ; - - xofiller!SHFILL3_RVT!x241280y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 24128 24736 ) N ; - - xofiller!SHFILL3_RVT!x245840y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 24584 24736 ) N ; - - xofiller!SHFILL3_RVT!x422160y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 42216 24736 ) N ; - - xofiller!SHFILL3_RVT!x426720y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 42672 24736 ) N ; - - xofiller!SHFILL3_RVT!x431280y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 43128 24736 ) N ; - - xofiller!SHFILL3_RVT!x435840y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 43584 24736 ) N ; - - xofiller!SHFILL3_RVT!x440400y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 44040 24736 ) N ; - - xofiller!SHFILL3_RVT!x444960y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 44496 24736 ) N ; - - xofiller!SHFILL3_RVT!x449520y247360 SHFILL3_RVT + SOURCE DIST + PLACED ( 44952 24736 ) N ; - - xofiller!SHFILL2_RVT!x454080y247360 SHFILL2_RVT + SOURCE DIST + PLACED ( 45408 24736 ) N ; - - xofiller!SHFILL3_RVT!x98400y264080 SHFILL3_RVT + SOURCE DIST + PLACED ( 9840 26408 ) FS ; - - xofiller!SHFILL3_RVT!x102960y264080 SHFILL3_RVT + SOURCE DIST + PLACED ( 10296 26408 ) FS ; - - xofiller!SHFILL3_RVT!x115120y264080 SHFILL3_RVT + SOURCE DIST + PLACED ( 11512 26408 ) FS ; - - xofiller!SHFILL3_RVT!x119680y264080 SHFILL3_RVT + SOURCE DIST + PLACED ( 11968 26408 ) FS ; - - xofiller!SHFILL2_RVT!x124240y264080 SHFILL2_RVT + SOURCE DIST + PLACED ( 12424 26408 ) FS ; - - xofiller!SHFILL3_RVT!x245840y264080 SHFILL3_RVT + SOURCE DIST + PLACED ( 24584 26408 ) FS ; - - xofiller!SHFILL2_RVT!x454080y264080 SHFILL2_RVT + SOURCE DIST + PLACED ( 45408 26408 ) FS ; - - xofiller!SHFILL1_RVT!x52800y280800 SHFILL1_RVT + SOURCE DIST + PLACED ( 5280 28080 ) N ; - - xofiller!SHFILL3_RVT!x140960y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 14096 28080 ) N ; - - xofiller!SHFILL3_RVT!x145520y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 14552 28080 ) N ; - - xofiller!SHFILL3_RVT!x150080y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 15008 28080 ) N ; - - xofiller!SHFILL3_RVT!x154640y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 15464 28080 ) N ; - - xofiller!SHFILL3_RVT!x159200y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 15920 28080 ) N ; - - xofiller!SHFILL3_RVT!x186560y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 18656 28080 ) N ; - - xofiller!SHFILL3_RVT!x428240y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 42824 28080 ) N ; - - xofiller!SHFILL2_RVT!x432800y280800 SHFILL2_RVT + SOURCE DIST + PLACED ( 43280 28080 ) N ; - - xofiller!SHFILL3_RVT!x452560y280800 SHFILL3_RVT + SOURCE DIST + PLACED ( 45256 28080 ) N ; - - xofiller!SHFILL3_RVT!x57360y297520 SHFILL3_RVT + SOURCE DIST + PLACED ( 5736 29752 ) FS ; - - xofiller!SHFILL3_RVT!x61920y297520 SHFILL3_RVT + SOURCE DIST + PLACED ( 6192 29752 ) FS ; - - xofiller!SHFILL3_RVT!x244320y297520 SHFILL3_RVT + SOURCE DIST + PLACED ( 24432 29752 ) FS ; - - xofiller!SHFILL3_RVT!x248880y297520 SHFILL3_RVT + SOURCE DIST + PLACED ( 24888 29752 ) FS ; - - xofiller!SHFILL3_RVT!x253440y297520 SHFILL3_RVT + SOURCE DIST + PLACED ( 25344 29752 ) FS ; - - xofiller!SHFILL1_RVT!x258000y297520 SHFILL1_RVT + SOURCE DIST + PLACED ( 25800 29752 ) FS ; - - xofiller!SHFILL2_RVT!x302080y297520 SHFILL2_RVT + SOURCE DIST + PLACED ( 30208 29752 ) FS ; - - xofiller!SHFILL3_RVT!x194160y314240 SHFILL3_RVT + SOURCE DIST + PLACED ( 19416 31424 ) N ; - - xofiller!SHFILL3_RVT!x64960y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 6496 33096 ) FS ; - - xofiller!SHFILL2_RVT!x69520y330960 SHFILL2_RVT + SOURCE DIST + PLACED ( 6952 33096 ) FS ; - - xofiller!SHFILL3_RVT!x80160y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 8016 33096 ) FS ; - - xofiller!SHFILL3_RVT!x84720y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 8472 33096 ) FS ; - - xofiller!SHFILL2_RVT!x89280y330960 SHFILL2_RVT + SOURCE DIST + PLACED ( 8928 33096 ) FS ; - - xofiller!SHFILL2_RVT!x144000y330960 SHFILL2_RVT + SOURCE DIST + PLACED ( 14400 33096 ) FS ; - - xofiller!SHFILL1_RVT!x166800y330960 SHFILL1_RVT + SOURCE DIST + PLACED ( 16680 33096 ) FS ; - - xofiller!SHFILL3_RVT!x241280y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 24128 33096 ) FS ; - - xofiller!SHFILL3_RVT!x245840y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 24584 33096 ) FS ; - - xofiller!SHFILL3_RVT!x250400y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 25040 33096 ) FS ; - - xofiller!SHFILL3_RVT!x254960y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 25496 33096 ) FS ; - - xofiller!SHFILL3_RVT!x259520y330960 SHFILL3_RVT + SOURCE DIST + PLACED ( 25952 33096 ) FS ; - - xofiller!SHFILL1_RVT!x455600y330960 SHFILL1_RVT + SOURCE DIST + PLACED ( 45560 33096 ) FS ; - - xofiller!SHFILL3_RVT!x148560y347680 SHFILL3_RVT + SOURCE DIST + PLACED ( 14856 34768 ) N ; - - xofiller!SHFILL3_RVT!x153120y347680 SHFILL3_RVT + SOURCE DIST + PLACED ( 15312 34768 ) N ; - - xofiller!SHFILL3_RVT!x317280y347680 SHFILL3_RVT + SOURCE DIST + PLACED ( 31728 34768 ) N ; - - xofiller!SHFILL1_RVT!x162240y364400 SHFILL1_RVT + SOURCE DIST + PLACED ( 16224 36440 ) FS ; - - xofiller!SHFILL2_RVT!x280800y364400 SHFILL2_RVT + SOURCE DIST + PLACED ( 28080 36440 ) FS ; - - xofiller!SHFILL3_RVT!x137920y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 13792 41456 ) N ; - - xofiller!SHFILL3_RVT!x142480y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 14248 41456 ) N ; - - xofiller!SHFILL3_RVT!x189600y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 18960 41456 ) N ; - - xofiller!SHFILL3_RVT!x194160y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 19416 41456 ) N ; - - xofiller!SHFILL3_RVT!x198720y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 19872 41456 ) N ; - - xofiller!SHFILL3_RVT!x203280y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 20328 41456 ) N ; - - xofiller!SHFILL3_RVT!x207840y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 20784 41456 ) N ; - - xofiller!SHFILL3_RVT!x253440y414560 SHFILL3_RVT + SOURCE DIST + PLACED ( 25344 41456 ) N ; - - xofiller!SHFILL2_RVT!x384160y414560 SHFILL2_RVT + SOURCE DIST + PLACED ( 38416 41456 ) N ; - - xofiller!SHFILL3_RVT!x30000y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 3000 43128 ) FS ; - - xofiller!SHFILL3_RVT!x34560y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 3456 43128 ) FS ; - - xofiller!SHFILL3_RVT!x39120y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 3912 43128 ) FS ; - - xofiller!SHFILL2_RVT!x69520y431280 SHFILL2_RVT + SOURCE DIST + PLACED ( 6952 43128 ) FS ; - - xofiller!SHFILL3_RVT!x127280y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 12728 43128 ) FS ; - - xofiller!SHFILL2_RVT!x131840y431280 SHFILL2_RVT + SOURCE DIST + PLACED ( 13184 43128 ) FS ; - - xofiller!SHFILL3_RVT!x221520y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 22152 43128 ) FS ; - - xofiller!SHFILL3_RVT!x226080y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 22608 43128 ) FS ; - - xofiller!SHFILL1_RVT!x230640y431280 SHFILL1_RVT + SOURCE DIST + PLACED ( 23064 43128 ) FS ; - - xofiller!SHFILL3_RVT!x396320y431280 SHFILL3_RVT + SOURCE DIST + PLACED ( 39632 43128 ) FS ; - - xofiller!SHFILL1_RVT!x400880y431280 SHFILL1_RVT + SOURCE DIST + PLACED ( 40088 43128 ) FS ; -END COMPONENTS -PINS 42 ; - - RST + NET RST + DIRECTION INPUT + USE SIGNAL - + LAYER M6 ( 0 0 ) ( 56 286 ) - + PLACED ( 22428 0 ) N ; - - TX_CLK + NET TX_CLK + DIRECTION INPUT + USE CLOCK - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 20908 0 ) N ; - - RX_CLK + NET RX_CLK + DIRECTION INPUT + USE CLOCK - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 24252 ) N ; - - RX_IN_S + NET RX_IN_S + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 30332 47514 ) N ; - - RX_OUT_P[7] + NET RX_OUT_P[7] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M5 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 35196 ) N ; - - RX_OUT_P[6] + NET RX_OUT_P[6] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 37628 ) N ; - - RX_OUT_P[5] + NET RX_OUT_P[5] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 35500 ) N ; - - RX_OUT_P[4] + NET RX_OUT_P[4] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 39756 ) N ; - - RX_OUT_P[3] + NET RX_OUT_P[3] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 41580 47514 ) N ; - - RX_OUT_P[2] + NET RX_OUT_P[2] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 38844 47514 ) N ; - - RX_OUT_P[1] + NET RX_OUT_P[1] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 36716 47514 ) N ; - - RX_OUT_P[0] + NET RX_OUT_P[0] + DIRECTION OUTPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 34588 47514 ) N ; - - RX_OUT_V + NET RX_OUT_V + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 28812 ) N ; - - TX_IN_P[7] + NET TX_IN_P[7] + DIRECTION INPUT + USE SIGNAL - + LAYER M6 ( 0 0 ) ( 56 286 ) - + PLACED ( 29724 0 ) N ; - - TX_IN_P[6] + NET TX_IN_P[6] + DIRECTION INPUT + USE SIGNAL - + LAYER M6 ( 0 0 ) ( 56 286 ) - + PLACED ( 27292 0 ) N ; - - TX_IN_P[5] + NET TX_IN_P[5] + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 27900 0 ) N ; - - TX_IN_P[4] + NET TX_IN_P[4] + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 25772 0 ) N ; - - TX_IN_P[3] + NET TX_IN_P[3] + DIRECTION INPUT + USE SIGNAL - + LAYER M6 ( 0 0 ) ( 56 286 ) - + PLACED ( 32156 0 ) N ; - - TX_IN_P[2] + NET TX_IN_P[2] + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 18172 ) N ; - - TX_IN_P[1] + NET TX_IN_P[1] + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 30028 0 ) N ; - - TX_IN_P[0] + NET TX_IN_P[0] + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 16652 0 ) N ; - - TX_IN_V + NET TX_IN_V + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 32764 0 ) N ; - - TX_OUT_S + NET TX_OUT_S + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 16044 ) N ; - - TX_OUT_V + NET TX_OUT_V + DIRECTION OUTPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 34892 0 ) N ; - - Prescale[5] + NET Prescale[5] + DIRECTION INPUT + USE SIGNAL - + LAYER M5 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 21820 ) N ; - - Prescale[4] + NET Prescale[4] + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 14828 ) N ; - - Prescale[3] + NET Prescale[3] + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 26380 ) N ; - - Prescale[2] + NET Prescale[2] + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 21516 ) N ; - - Prescale[1] + NET Prescale[1] + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 28508 ) N ; - - Prescale[0] + NET Prescale[0] + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 0 18780 ) N ; - - parity_enable + NET parity_enable + DIRECTION INPUT + USE SIGNAL - + LAYER M5 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 19388 ) N ; - - parity_type + NET parity_type + DIRECTION INPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 21820 ) N ; - - parity_error + NET parity_error + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 30940 ) N ; - - framing_error + NET framing_error + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 26684 ) N ; - - SI + NET SI + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 13612 47514 ) N ; - - SE + NET SE + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 24556 47514 ) N ; - - SO + NET SO + DIRECTION OUTPUT + USE SIGNAL - + LAYER M3 ( 0 0 ) ( 286 56 ) - + PLACED ( 48426 23948 ) N ; - - scan_clk + NET scan_clk + DIRECTION INPUT + USE CLOCK - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 18780 0 ) N ; - - scan_rst + NET scan_rst + DIRECTION INPUT + USE SIGNAL - + LAYER M4 ( 0 0 ) ( 56 286 ) - + PLACED ( 23036 0 ) N ; - - test_mode + NET test_mode + DIRECTION INPUT + USE SIGNAL - + LAYER M6 ( 0 0 ) ( 56 286 ) - + PLACED ( 24860 0 ) N ; - - VDD + NET VDD + SPECIAL + DIRECTION INPUT + USE POWER ; - - VSS + NET VSS + SPECIAL + DIRECTION INPUT + USE GROUND ; -END PINS -PINPROPERTIES 40 ; - - PIN RST - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_CLK - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN RX_CLK - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN RX_IN_S - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN RX_OUT_P[7] - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN RX_OUT_P[6] - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN RX_OUT_P[5] - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN RX_OUT_P[4] - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN RX_OUT_P[3] - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN RX_OUT_P[2] - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN RX_OUT_P[1] - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN RX_OUT_P[0] - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN RX_OUT_V - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN TX_IN_P[7] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_P[6] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_P[5] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_P[4] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_P[3] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_P[2] - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN TX_IN_P[1] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_P[0] - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_IN_V - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN TX_OUT_S - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN TX_OUT_V - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN Prescale[5] - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN Prescale[4] - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN Prescale[3] - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN Prescale[2] - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN Prescale[1] - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN Prescale[0] - + PROPERTY ACCESS_DIRECTION "0 left" ; - - PIN parity_enable - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN parity_type - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN parity_error - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN framing_error - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN SI - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN SE - + PROPERTY ACCESS_DIRECTION "0 top" ; - - PIN SO - + PROPERTY ACCESS_DIRECTION "0 right" ; - - PIN scan_clk - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN scan_rst - + PROPERTY ACCESS_DIRECTION "0 bottom" ; - - PIN test_mode - + PROPERTY ACCESS_DIRECTION "0 bottom" ; -END PINPROPERTIES -SPECIALNETS 248 ; - - RST - + ROUTED M5 60 ( 22274 4064 30 ) ( 22456 * 30 ) - NEW M4 60 ( 22456 3882 30 ) ( * 4064 30 ) - NEW M3 60 ( 22274 4064 30 ) ( 22456 * 30 ) - + USE SIGNAL ; - - TX_CLK - + ROUTED M2 60 ( 20328 3730 30 ) ( * 3912 30 ) - + USE CLOCK ; - - RX_CLK - + ROUTED M2 60 ( 3304 25314 30 ) ( * 25496 30 ) - + USE CLOCK ; - - RX_IN_S - + ROUTED M2 60 ( 27320 30482 30 ) ( * 30664 30 ) - NEW M2 60 ( 29448 30482 30 ) ( * 30664 30 ) - NEW M3 60 ( 27442 37048 30 ) ( 27624 * 30 ) - NEW M2 60 ( 27624 37048 30 ) ( * 37200 30 ) - + USE SIGNAL ; - - RX_OUT_P[7] - + ROUTED M1 60 ( 35984 35376 30 ) ( 36136 * 30 ) - NEW M2 60 ( 44496 34130 30 ) ( * 34160 30 ) - NEW M2 60 ( 44496 34160 30 ) ( * 34312 30 ) - + USE SIGNAL ; - - RX_OUT_P[6] - + ROUTED M3 60 ( 44192 37656 30 ) ( 44344 * 30 ) - NEW M3 60 ( 36896 38568 30 ) ( 37048 * 30 ) - NEW M2 60 ( 44800 33826 30 ) ( * 34008 30 ) - NEW M2 60 ( 36896 38538 30 ) ( * 38568 30 ) - NEW M2 60 ( 36896 38568 30 ) ( * 38720 30 ) - + USE SIGNAL ; - - RX_OUT_P[5] - + ROUTED M2 60 ( 38720 38568 30 ) ( * 38720 30 ) - + USE SIGNAL ; - - RX_OUT_P[4] - + ROUTED M2 60 ( 45408 38994 30 ) ( * 39176 30 ) - NEW M2 60 ( 39024 40666 30 ) ( * 40696 30 ) - NEW M2 60 ( 39024 40696 30 ) ( * 40848 30 ) - + USE SIGNAL ; - - RX_OUT_P[3] - + ROUTED M2 60 ( 38568 44010 30 ) ( * 44040 30 ) - NEW M2 60 ( 38568 44040 30 ) ( * 44192 30 ) - + USE SIGNAL ; - - RX_OUT_P[2] - + ROUTED M2 60 ( 39176 42338 30 ) ( * 42520 30 ) - NEW M2 60 ( 36136 44162 30 ) ( * 44192 30 ) - NEW M2 60 ( 36136 44192 30 ) ( * 44344 30 ) - + USE SIGNAL ; - - RX_OUT_P[1] - + ROUTED M2 60 ( 36288 43554 30 ) ( * 43736 30 ) - + USE SIGNAL ; - - RX_OUT_P[0] - + ROUTED M2 60 ( 33400 40210 30 ) ( * 40392 30 ) - NEW M2 60 ( 33856 42338 30 ) ( * 42520 30 ) - + USE SIGNAL ; - - TX_IN_P[7] - + ROUTED M3 60 ( 25466 11208 30 ) ( 25496 * 30 ) - NEW M3 60 ( 25496 11208 30 ) ( 25648 * 30 ) - + USE SIGNAL ; - - TX_IN_P[6] - + ROUTED M3 60 ( 24250 6344 30 ) ( 24280 * 30 ) - NEW M3 60 ( 24280 6344 30 ) ( 24432 * 30 ) - + USE SIGNAL ; - - TX_IN_P[3] - + ROUTED M2 60 ( 30664 5584 30 ) ( * 5736 30 ) - NEW M4 60 ( 30664 4642 30 ) ( * 4824 30 ) - NEW M3 60 ( 30482 4824 30 ) ( 30664 * 30 ) - + USE SIGNAL ; - - TX_IN_P[2] - + ROUTED M2 60 ( 26712 14674 30 ) ( * 14856 30 ) - + USE SIGNAL ; - - TX_IN_P[1] - + ROUTED M2 60 ( 28232 11330 30 ) ( * 11512 30 ) - + USE SIGNAL ; - - TX_IN_V - + ROUTED M2 60 ( 35832 3476 30 ) ( * 3608 30 ) - NEW M2 60 ( 33552 3476 30 ) ( * 3608 30 ) - + USE SIGNAL ; - - Prescale[5] - + ROUTED M3 60 ( 7256 22456 30 ) ( 7408 * 30 ) - NEW M2 60 ( 6192 10722 30 ) ( * 10752 30 ) - NEW M2 60 ( 6192 10752 30 ) ( * 10904 30 ) - + USE SIGNAL ; - - Prescale[4] - + ROUTED M2 60 ( 5584 8776 30 ) ( * 8928 30 ) - NEW M1 60 ( 3152 18808 30 ) ( 3306 * 30 ) - NEW M2 60 ( 3304 8594 30 ) ( * 8776 30 ) - + USE SIGNAL ; - - Prescale[3] - + ROUTED M2 60 ( 7256 7378 30 ) ( * 7433 30 ) - + USE SIGNAL ; - - Prescale[2] - + ROUTED M2 58 ( 3607 24001 29 ) ( * 24127 29 ) - NEW M1 60 ( 4064 32336 30 ) ( 4216 * 30 ) - NEW M2 60 ( 5736 15586 30 ) ( * 15616 30 ) - NEW M2 60 ( 5736 15616 30 ) ( * 15768 30 ) - NEW M2 60 ( 8320 15586 30 ) ( * 15616 30 ) - NEW M2 60 ( 8320 15616 30 ) ( * 15768 30 ) - + USE SIGNAL ; - - Prescale[1] - + ROUTED M2 60 ( 6952 16984 30 ) ( * 17136 30 ) - NEW M2 60 ( 7864 20602 30 ) ( * 20632 30 ) - NEW M2 60 ( 7864 20632 30 ) ( * 20784 30 ) - NEW M1 60 ( 6648 23824 30 ) ( 6800 * 30 ) - + USE SIGNAL ; - - Prescale[0] - + ROUTED M2 60 ( 6344 23844 30 ) ( * 23976 30 ) - NEW M1 60 ( 15287 18808 30 ) ( 15464 * 30 ) - NEW M2 60 ( 15464 18626 30 ) ( * 18808 30 ) - NEW M2 60 ( 17896 18676 30 ) ( * 18808 30 ) - NEW M2 60 ( 15920 18626 30 ) ( * 18808 30 ) - NEW M1 60 ( 7104 25496 30 ) ( 7256 * 30 ) - + USE SIGNAL ; - - parity_enable - + ROUTED M2 60 ( 40088 18626 30 ) ( * 18808 30 ) - NEW M1 60 ( 39079 15464 30 ) ( 39176 * 30 ) - NEW M1 60 ( 30663 18808 30 ) ( 30816 * 30 ) - NEW M2 60 ( 30816 18626 30 ) ( * 18808 30 ) - + USE SIGNAL ; - - parity_type - + ROUTED M2 60 ( 34616 19386 30 ) ( * 19416 30 ) - NEW M2 60 ( 34616 19416 30 ) ( * 19568 30 ) - + USE SIGNAL ; - - framing_error - + ROUTED M2 60 ( 45104 26834 30 ) ( * 27016 30 ) - + USE SIGNAL ; - - SE - + ROUTED M2 60 ( 27928 34160 30 ) ( * 34312 30 ) - NEW M2 60 ( 34160 27442 30 ) ( * 27472 30 ) - NEW M2 60 ( 34160 27472 30 ) ( * 27624 30 ) - NEW M1 60 ( 22511 32124 30 ) ( 22543 * 30 ) - NEW M1 60 ( 22304 28780 30 ) ( 22456 * 30 ) - NEW M2 60 ( 23672 44040 30 ) ( * 44192 30 ) - NEW M1 60 ( 23271 40756 30 ) ( 23303 * 30 ) - NEW M2 60 ( 35832 37352 30 ) ( * 37504 30 ) - NEW M2 60 ( 30816 38568 30 ) ( * 38720 30 ) - NEW M2 60 ( 40696 30816 30 ) ( * 30968 30 ) - NEW M1 152 ( 23085 40802 76 ) ( 23195 * 76 ) - NEW M2 60 ( 16224 40574 30 ) ( * 40696 30 ) - NEW M3 60 ( 40514 30968 30 ) ( 40696 * 30 ) - NEW M2 60 ( 17288 34130 30 ) ( * 34160 30 ) - NEW M2 60 ( 17288 34160 30 ) ( * 34312 30 ) - NEW M1 60 ( 22217 32124 30 ) ( 22249 * 30 ) - NEW M2 60 ( 40392 27442 30 ) ( * 27472 30 ) - NEW M2 60 ( 40392 27472 30 ) ( * 27624 30 ) - NEW M1 152 ( 22325 32078 76 ) ( 22435 * 76 ) - NEW M1 60 ( 22977 40756 30 ) ( 23009 * 30 ) - + USE SIGNAL ; - - scan_clk - + ROUTED M3 60 ( 30178 15464 30 ) ( 30360 * 30 ) - NEW M2 60 ( 30360 15434 30 ) ( * 15464 30 ) - NEW M2 60 ( 30360 15464 30 ) ( * 15616 30 ) - + USE CLOCK ; - - scan_rst - + ROUTED M3 60 ( 23034 3608 30 ) ( 23064 * 30 ) - NEW M3 60 ( 23064 3608 30 ) ( 23216 * 30 ) - NEW M2 60 ( 23216 3426 30 ) ( * 3608 30 ) - + USE SIGNAL ; - - test_mode - + ROUTED M5 60 ( 24706 3912 30 ) ( 24888 * 30 ) - NEW M4 60 ( 24888 3730 30 ) ( * 3912 30 ) - NEW M2 60 ( 22760 3730 30 ) ( * 3912 30 ) - + USE SIGNAL ; - - UART_RX_SCAN_CLK - + ROUTED M2 60 ( 31576 35346 30 ) ( * 35528 30 ) - NEW M3 60 ( 41882 40088 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41912 40088 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 39906 30 ) ( * 40088 30 ) - NEW M1 110 ( 42064 39956 55 ) ( * 40063 55 ) - NEW M2 60 ( 23672 29418 30 ) ( * 29448 30 ) - NEW M2 60 ( 23672 29448 30 ) ( * 29600 30 ) - NEW M2 60 ( 25040 43128 30 ) ( * 43280 30 ) - NEW M2 60 ( 25040 43098 30 ) ( * 43128 30 ) - NEW M3 60 ( 25010 43128 30 ) ( 25040 * 30 ) - NEW M3 60 ( 25040 43128 30 ) ( 25192 * 30 ) - NEW M2 60 ( 18200 29874 30 ) ( * 29904 30 ) - NEW M2 60 ( 18200 29904 30 ) ( * 30056 30 ) - NEW M3 60 ( 18018 30056 30 ) ( 18200 * 30 ) - NEW M2 60 ( 18200 36410 30 ) ( * 36592 30 ) - NEW M3 60 ( 18018 36592 30 ) ( 18200 * 30 ) - NEW M2 60 ( 23672 32762 30 ) ( * 32944 30 ) - NEW M2 60 ( 24888 23034 30 ) ( * 23216 30 ) - NEW M2 60 ( 32184 39298 30 ) ( * 39480 30 ) - NEW M1 110 ( 32184 39505 55 ) ( * 39612 55 ) - NEW M2 60 ( 24432 39906 30 ) ( * 39936 30 ) - NEW M2 60 ( 24432 39936 30 ) ( * 40088 30 ) - NEW M2 60 ( 30056 39906 30 ) ( * 39936 30 ) - NEW M2 60 ( 30056 39936 30 ) ( * 40088 30 ) - NEW M2 60 ( 18504 43098 30 ) ( * 43128 30 ) - NEW M2 60 ( 18504 43128 30 ) ( * 43280 30 ) - NEW M2 60 ( 41912 32762 30 ) ( * 32944 30 ) - NEW M3 60 ( 41730 32944 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41882 39480 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41912 39480 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 39298 30 ) ( * 39480 30 ) - NEW M1 110 ( 42064 39505 55 ) ( * 39612 55 ) - NEW M3 60 ( 41882 43128 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41912 43128 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 43095 30 ) ( * 43128 30 ) - NEW M2 60 ( 42064 43128 30 ) ( * 43280 30 ) - NEW M3 60 ( 37018 36440 30 ) ( 37048 * 30 ) - NEW M3 60 ( 37048 36440 30 ) ( 37200 * 30 ) - NEW M2 60 ( 37200 36407 30 ) ( * 36440 30 ) - NEW M2 60 ( 37200 36440 30 ) ( * 36592 30 ) - NEW M2 60 ( 30208 36410 30 ) ( * 36440 30 ) - NEW M2 60 ( 30208 36440 30 ) ( * 36592 30 ) - NEW M3 60 ( 30330 43128 30 ) ( 30360 * 30 ) - NEW M3 60 ( 30360 43128 30 ) ( 30512 * 30 ) - NEW M2 60 ( 30512 43095 30 ) ( * 43128 30 ) - NEW M2 60 ( 30512 43128 30 ) ( * 43280 30 ) - NEW M3 60 ( 29114 34616 30 ) ( 29144 * 30 ) - NEW M3 60 ( 29144 34616 30 ) ( 29296 * 30 ) - NEW M2 60 ( 35680 26530 30 ) ( * 26560 30 ) - NEW M2 60 ( 35680 26560 30 ) ( * 26712 30 ) - NEW M3 60 ( 41882 30056 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41912 30056 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 29874 30 ) ( * 30056 30 ) - NEW M1 110 ( 42064 29924 55 ) ( * 30031 55 ) - NEW M2 60 ( 17288 26530 30 ) ( * 26560 30 ) - NEW M2 60 ( 17288 26560 30 ) ( * 26712 30 ) - NEW M2 60 ( 41760 26452 30 ) ( * 26560 30 ) - NEW M2 60 ( 41760 26560 30 ) ( * 26712 30 ) - NEW M3 60 ( 41730 26712 30 ) ( 41760 * 30 ) - NEW M3 60 ( 41760 26712 30 ) ( 41912 * 30 ) - NEW M2 60 ( 24280 22730 30 ) ( * 22760 30 ) - NEW M2 60 ( 24280 22760 30 ) ( * 22912 30 ) - NEW M1 110 ( 18656 33268 55 ) ( * 33375 55 ) - NEW M2 60 ( 18656 33218 30 ) ( * 33400 30 ) - NEW M3 60 ( 18504 33400 30 ) ( 18656 * 30 ) - NEW M3 60 ( 18474 33400 30 ) ( 18504 * 30 ) - NEW M2 60 ( 29296 29418 30 ) ( * 29448 30 ) - NEW M2 60 ( 29296 29448 30 ) ( * 29600 30 ) - NEW M2 60 ( 17592 39754 30 ) ( * 39784 30 ) - NEW M2 60 ( 17592 39784 30 ) ( * 39936 30 ) - NEW M2 60 ( 38416 36106 30 ) ( * 36136 30 ) - NEW M2 60 ( 38416 36136 30 ) ( * 36288 30 ) - + USE CLOCK ; - - UART_TX_SCAN_CLK - + ROUTED M2 60 ( 35984 12546 30 ) ( * 12728 30 ) - NEW M1 110 ( 35984 12753 55 ) ( * 12860 55 ) - NEW M3 60 ( 41882 3304 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41912 3304 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 3152 30 ) ( * 3304 30 ) - NEW M2 60 ( 42064 3044 30 ) ( * 3152 30 ) - NEW M1 110 ( 34920 9860 55 ) ( * 9967 55 ) - NEW M2 60 ( 34920 9810 30 ) ( * 9992 30 ) - NEW M1 110 ( 35072 13204 55 ) ( * 13311 55 ) - NEW M2 60 ( 35072 13154 30 ) ( * 13336 30 ) - NEW M3 60 ( 35042 13336 30 ) ( 35072 * 30 ) - NEW M3 60 ( 35072 13336 30 ) ( 35224 * 30 ) - NEW M2 60 ( 35528 6314 30 ) ( * 6344 30 ) - NEW M2 60 ( 35528 6344 30 ) ( * 6496 30 ) - NEW M3 60 ( 36106 20024 30 ) ( 36136 * 30 ) - NEW M3 60 ( 36136 20024 30 ) ( 36288 * 30 ) - NEW M2 60 ( 36288 19842 30 ) ( * 20024 30 ) - NEW M1 110 ( 36288 19892 55 ) ( * 19999 55 ) - NEW M2 60 ( 16680 6314 30 ) ( * 6344 30 ) - NEW M2 60 ( 16680 6344 30 ) ( * 6496 30 ) - NEW M2 60 ( 19720 16042 30 ) ( * 16072 30 ) - NEW M2 60 ( 19720 16072 30 ) ( * 16224 30 ) - NEW M2 60 ( 37048 23034 30 ) ( * 23064 30 ) - NEW M2 60 ( 37048 23064 30 ) ( * 23216 30 ) - NEW M3 60 ( 29722 19720 30 ) ( 29752 * 30 ) - NEW M3 60 ( 29752 19720 30 ) ( 29904 * 30 ) - NEW M2 60 ( 29904 19687 30 ) ( * 19720 30 ) - NEW M2 60 ( 29904 19720 30 ) ( * 19872 30 ) - NEW M2 60 ( 37048 6010 30 ) ( * 6040 30 ) - NEW M2 60 ( 37048 6040 30 ) ( * 6192 30 ) - NEW M2 60 ( 36592 16498 30 ) ( * 16528 30 ) - NEW M2 60 ( 36592 16528 30 ) ( * 16680 30 ) - NEW M3 60 ( 41912 16680 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 16528 30 ) ( * 16680 30 ) - NEW M2 60 ( 42064 16498 30 ) ( * 16528 30 ) - NEW M2 60 ( 18960 13154 30 ) ( * 13184 30 ) - NEW M2 60 ( 18960 13184 30 ) ( * 13336 30 ) - NEW M1 110 ( 28840 13204 55 ) ( * 13311 55 ) - NEW M2 60 ( 28840 13154 30 ) ( * 13336 30 ) - NEW M1 110 ( 17288 9860 55 ) ( * 9967 55 ) - NEW M2 60 ( 17288 9810 30 ) ( * 9992 30 ) - NEW M3 60 ( 28506 3304 30 ) ( 28536 * 30 ) - NEW M3 60 ( 28536 3304 30 ) ( 28688 * 30 ) - NEW M2 60 ( 28688 3152 30 ) ( * 3304 30 ) - NEW M2 60 ( 28688 3044 30 ) ( * 3152 30 ) - NEW M2 60 ( 29144 16498 30 ) ( * 16528 30 ) - NEW M2 60 ( 29144 16528 30 ) ( * 16680 30 ) - NEW M3 60 ( 41912 6344 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 6311 30 ) ( * 6344 30 ) - NEW M2 60 ( 42064 6344 30 ) ( * 6496 30 ) - NEW M2 60 ( 17592 9202 30 ) ( * 9384 30 ) - NEW M1 110 ( 17592 9409 55 ) ( * 9516 55 ) - NEW M3 60 ( 41882 19720 30 ) ( 41912 * 30 ) - NEW M3 60 ( 41912 19720 30 ) ( 42064 * 30 ) - NEW M2 60 ( 42064 19687 30 ) ( * 19720 30 ) - NEW M2 60 ( 42064 19720 30 ) ( * 19872 30 ) - NEW M2 60 ( 26408 6314 30 ) ( * 6344 30 ) - NEW M2 60 ( 26408 6344 30 ) ( * 6496 30 ) - NEW M2 60 ( 26560 9658 30 ) ( * 9688 30 ) - NEW M2 60 ( 26560 9688 30 ) ( * 9840 30 ) - NEW M2 60 ( 22912 16498 30 ) ( * 16528 30 ) - NEW M2 60 ( 22912 16528 30 ) ( * 16680 30 ) - NEW M3 60 ( 22760 16680 30 ) ( 22912 * 30 ) - NEW M3 60 ( 22652 16680 30 ) ( 22760 * 30 ) - NEW M2 60 ( 15768 3122 30 ) ( * 3152 30 ) - NEW M2 60 ( 15768 3152 30 ) ( * 3304 30 ) - + USE CLOCK ; - - SCAN_RST - + ROUTED M1 60 ( 24888 5432 30 ) ( 25042 * 30 ) - + USE SIGNAL ; - - U0_mux2X1/cts0 - + ROUTED M3 60 ( 29570 32792 30 ) ( 29752 * 30 ) - NEW M4 60 ( 29752 32610 30 ) ( * 32792 30 ) - + USE SIGNAL ; - - U0_UART_TX/seriz_en - + ROUTED M2 60 ( 35832 8948 30 ) ( * 9080 30 ) - NEW M2 60 ( 38872 22304 30 ) ( * 22456 30 ) - NEW M2 60 ( 40696 22274 30 ) ( * 22304 30 ) - NEW M2 60 ( 40696 22304 30 ) ( * 22456 30 ) - NEW M2 60 ( 41912 22274 30 ) ( * 22304 30 ) - NEW M2 60 ( 41912 22304 30 ) ( * 22456 30 ) - + USE SIGNAL ; - - U0_UART_TX/ser_data - + ROUTED M2 60 ( 38416 13640 30 ) ( * 13822 30 ) - NEW M2 60 ( 39632 13458 30 ) ( * 13640 30 ) - + USE SIGNAL ; - - U0_UART_TX/mux_sel[0] - + ROUTED M2 60 ( 44040 13762 30 ) ( * 13944 30 ) - + USE SIGNAL ; - - HFSNET_0 - + ROUTED M1 60 ( 24953 7316 30 ) ( 24985 * 30 ) - NEW M2 60 ( 27168 4034 30 ) ( * 4064 30 ) - NEW M2 60 ( 27168 4064 30 ) ( * 4216 30 ) - NEW M1 60 ( 25247 7316 30 ) ( 25279 * 30 ) - NEW M2 60 ( 35680 5098 30 ) ( * 5128 30 ) - NEW M2 60 ( 35680 5128 30 ) ( * 5280 30 ) - NEW M2 60 ( 18352 15160 30 ) ( * 15312 30 ) - NEW M2 60 ( 21544 17288 30 ) ( * 17440 30 ) - NEW M2 60 ( 15920 10752 30 ) ( * 10904 30 ) - NEW M2 60 ( 27776 17288 30 ) ( * 17440 30 ) - NEW M2 60 ( 27472 14096 30 ) ( * 14248 30 ) - NEW M2 60 ( 35224 17440 30 ) ( * 17592 30 ) - NEW M2 60 ( 28688 20784 30 ) ( * 20936 30 ) - NEW M1 60 ( 28449 20692 30 ) ( 28481 * 30 ) - NEW M1 60 ( 28743 20692 30 ) ( 28775 * 30 ) - NEW M2 60 ( 34616 11786 30 ) ( * 11816 30 ) - NEW M2 60 ( 34616 11816 30 ) ( * 11968 30 ) - NEW M2 60 ( 33552 10722 30 ) ( * 10752 30 ) - NEW M2 60 ( 33552 10752 30 ) ( * 10904 30 ) - NEW M1 152 ( 25061 7362 76 ) ( 25171 * 76 ) - NEW M1 152 ( 28557 20738 76 ) ( 28667 * 76 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/dftopt2_gOb7 - + ROUTED M2 60 ( 40848 11634 30 ) ( * 11816 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/current_state_0_ - + ROUTED M3 60 ( 38386 14856 30 ) ( 38568 * 30 ) - NEW M2 60 ( 45104 4338 30 ) ( * 4368 30 ) - NEW M2 60 ( 45104 4368 30 ) ( * 4520 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/busy_c - + ROUTED M2 60 ( 36136 5250 30 ) ( * 5432 30 ) - NEW M2 60 ( 41720 5250 30 ) ( * 5432 30 ) - NEW M1 80 ( 41735 5442 40 ) ( * 5487 40 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n5 - + ROUTED M2 60 ( 41456 10448 30 ) ( * 10600 30 ) - NEW M2 60 ( 39936 8594 30 ) ( * 8776 30 ) - NEW M2 60 ( 44040 8594 30 ) ( * 8776 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n10 - + ROUTED M2 60 ( 38112 14978 30 ) ( * 15160 30 ) - NEW M1 116 ( 38006 15188 58 ) ( 38079 * 58 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n11 - + ROUTED M2 60 ( 41912 9536 30 ) ( * 9688 30 ) - NEW M1 60 ( 40088 10600 30 ) ( 40240 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n12 - + ROUTED M2 60 ( 41760 9810 30 ) ( * 9844 30 ) - NEW M2 60 ( 41760 9844 30 ) ( * 9992 30 ) - NEW M2 60 ( 44648 9992 30 ) ( * 10144 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n13 - + ROUTED M2 60 ( 37960 9202 30 ) ( * 9384 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n14 - + ROUTED M1 60 ( 38568 4216 30 ) ( 38720 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n15 - + ROUTED M2 60 ( 44192 5280 30 ) ( * 5432 30 ) - NEW M2 60 ( 44192 11026 30 ) ( * 11208 30 ) - NEW M1 60 ( 42520 11968 30 ) ( 42672 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n9 - + ROUTED M1 60 ( 44344 11968 30 ) ( 44441 * 30 ) - NEW M2 60 ( 44344 11938 30 ) ( * 11968 30 ) - NEW M2 60 ( 44344 11968 30 ) ( * 12120 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/dftopt1_gOb4 - + ROUTED M1 60 ( 41304 3304 30 ) ( 41488 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/next_state[2] - + ROUTED M2 60 ( 35072 11938 30 ) ( * 12120 30 ) - + USE SIGNAL ; - - U0_UART_RX/dftopt2 - + ROUTED M2 60 ( 22000 43377 30 ) ( * 43432 30 ) - NEW M2 60 ( 22000 43432 30 ) ( * 43559 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/N23 - + ROUTED M2 60 ( 42064 21362 30 ) ( * 21544 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/N24 - + ROUTED M2 60 ( 36136 23794 30 ) ( * 23976 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/N25 - + ROUTED M2 60 ( 41304 20450 30 ) ( * 20632 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n18 - + ROUTED M2 60 ( 29904 5128 30 ) ( * 5280 30 ) - NEW M2 60 ( 29904 5098 30 ) ( * 5128 30 ) - NEW M2 60 ( 33248 5073 30 ) ( * 5128 30 ) - NEW M2 60 ( 33248 5128 30 ) ( * 5255 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n19 - + ROUTED M2 60 ( 35680 3760 30 ) ( * 3912 30 ) - NEW M1 60 ( 35660 8776 30 ) ( 35832 * 30 ) - NEW M2 60 ( 33856 5402 30 ) ( * 5432 30 ) - NEW M2 60 ( 33856 5432 30 ) ( * 5584 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n20 - + ROUTED M2 60 ( 35984 8290 30 ) ( * 8472 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n21 - + ROUTED M2 60 ( 42520 22578 30 ) ( * 22760 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n26 - + ROUTED M2 60 ( 22304 6770 30 ) ( * 6952 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n27 - + ROUTED M2 60 ( 16680 8594 30 ) ( * 8776 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n30 - + ROUTED M1 60 ( 32638 6800 30 ) ( 32792 * 30 ) - NEW M2 60 ( 34616 7074 30 ) ( * 7256 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n15 - + ROUTED M2 60 ( 30056 8948 30 ) ( * 9080 30 ) - NEW M2 60 ( 24128 8948 30 ) ( * 9080 30 ) - NEW M2 60 ( 31576 6820 30 ) ( * 6952 30 ) - NEW M2 60 ( 32184 8948 30 ) ( * 9080 30 ) - NEW M2 60 ( 22608 8948 30 ) ( * 9080 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n16 - + ROUTED M2 60 ( 24128 5280 30 ) ( * 5432 30 ) - NEW M2 60 ( 23976 8472 30 ) ( * 8624 30 ) - NEW M2 60 ( 30512 5280 30 ) ( * 5432 30 ) - NEW M2 60 ( 31424 7226 30 ) ( * 7256 30 ) - NEW M2 60 ( 31424 7256 30 ) ( * 7408 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n34 - + ROUTED M2 60 ( 20176 6593 30 ) ( * 6648 30 ) - NEW M2 60 ( 20176 6648 30 ) ( * 6775 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/dftopt8_gOb9 - + ROUTED M2 60 ( 29904 6770 30 ) ( * 6800 30 ) - NEW M2 60 ( 29904 6800 30 ) ( * 6952 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/dftopt2_gOb8 - + ROUTED M1 60 ( 34160 9992 30 ) ( 34344 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[6] - + ROUTED M1 88 ( 22839 7237 44 ) ( 22914 * 44 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[5] - + ROUTED M2 60 ( 20973 8948 30 ) ( * 9080 30 ) - NEW M2 60 ( 22152 8644 30 ) ( * 8776 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[2] - + ROUTED M1 88 ( 32030 7237 44 ) ( 32105 * 44 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/ser_count[1] - + ROUTED M2 60 ( 40392 23490 30 ) ( * 23672 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_mux/mux_out - + ROUTED M2 60 ( 44496 15586 30 ) ( * 15768 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n4 - + ROUTED M2 60 ( 43128 15890 30 ) ( * 16072 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n5 - + ROUTED M2 60 ( 42824 13154 30 ) ( * 13336 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n3 - + ROUTED M2 60 ( 42216 14096 30 ) ( * 14248 30 ) - NEW M2 60 ( 43736 14066 30 ) ( * 14137 30 ) - NEW M2 60 ( 43736 14137 30 ) ( * 14248 30 ) - + USE SIGNAL ; - - U0_UART_RX/HFSNET_1 - + ROUTED M2 60 ( 19720 44466 30 ) ( * 44648 30 ) - NEW M2 60 ( 18352 27746 30 ) ( * 27928 30 ) - NEW M2 60 ( 26256 44466 30 ) ( * 44648 30 ) - NEW M2 60 ( 38416 37778 30 ) ( * 37960 30 ) - NEW M2 60 ( 31272 41122 30 ) ( * 41304 30 ) - NEW M2 60 ( 31424 37778 30 ) ( * 37960 30 ) - NEW M2 60 ( 20632 6010 30 ) ( * 6192 30 ) - NEW M3 60 ( 20450 6192 30 ) ( 20632 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n2 - + ROUTED M2 60 ( 32336 18170 30 ) ( * 18200 30 ) - NEW M2 60 ( 32336 18200 30 ) ( * 18352 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n4 - + ROUTED M2 60 ( 26712 18322 30 ) ( * 18504 30 ) - NEW M2 60 ( 32792 18474 30 ) ( * 18504 30 ) - NEW M2 60 ( 32792 18504 30 ) ( * 18656 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n5 - + ROUTED M2 60 ( 25952 18474 30 ) ( * 18504 30 ) - NEW M2 60 ( 25952 18504 30 ) ( * 18656 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n8 - + ROUTED M2 60 ( 28688 11938 30 ) ( * 12120 30 ) - NEW M3 60 ( 26104 17592 30 ) ( 26286 * 30 ) - NEW M2 60 ( 27928 18626 30 ) ( * 18808 30 ) - NEW M1 60 ( 26104 15464 30 ) ( 26256 * 30 ) - NEW M2 60 ( 21088 11938 30 ) ( * 12120 30 ) - NEW M2 60 ( 33400 4338 30 ) ( * 4520 30 ) - NEW M3 60 ( 33218 4520 30 ) ( 33400 * 30 ) - NEW M4 60 ( 29144 11938 30 ) ( * 12120 30 ) - NEW M2 60 ( 25344 13762 30 ) ( * 13944 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n22 - + ROUTED M2 60 ( 20784 11026 30 ) ( * 11181 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n37 - + ROUTED M2 60 ( 16376 10418 30 ) ( * 10600 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n41 - + ROUTED M2 60 ( 23784 15282 30 ) ( * 15464 30 ) - NEW M1 80 ( 23799 15474 40 ) ( * 15529 40 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n43 - + ROUTED M2 60 ( 26256 14370 30 ) ( * 14552 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n1 - + ROUTED M2 60 ( 32184 17714 30 ) ( * 17896 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n6 - + ROUTED M2 60 ( 20936 12242 30 ) ( * 12424 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n7 - + ROUTED M1 60 ( 26033 12424 30 ) ( 26256 * 30 ) - NEW M2 60 ( 26256 12424 30 ) ( * 12606 30 ) - NEW M2 60 ( 29904 10114 30 ) ( * 10296 30 ) - NEW M1 60 ( 28080 13336 30 ) ( 28264 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n10 - + ROUTED M2 60 ( 34616 14978 30 ) ( * 15008 30 ) - NEW M2 60 ( 34616 15008 30 ) ( * 15160 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n13 - + ROUTED M2 60 ( 28151 18980 30 ) ( * 19112 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n14 - + ROUTED M2 60 ( 28536 12242 30 ) ( * 12424 30 ) - NEW M2 60 ( 30816 11938 30 ) ( * 12120 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n15 - + ROUTED M2 60 ( 24280 10570 30 ) ( * 10600 30 ) - NEW M2 60 ( 24280 10600 30 ) ( * 10752 30 ) - NEW M2 60 ( 28536 11786 30 ) ( * 11816 30 ) - NEW M2 60 ( 28536 11816 30 ) ( * 11968 30 ) - NEW M1 60 ( 28384 11968 30 ) ( 28536 * 30 ) - NEW M1 60 ( 25496 14096 30 ) ( 25648 * 30 ) - NEW M2 60 ( 25952 11786 30 ) ( * 11816 30 ) - NEW M2 60 ( 25952 11816 30 ) ( * 11968 30 ) - NEW M2 60 ( 20784 11786 30 ) ( * 11816 30 ) - NEW M2 60 ( 20784 11816 30 ) ( * 11968 30 ) - NEW M2 60 ( 26560 15130 30 ) ( * 15160 30 ) - NEW M2 60 ( 26560 15160 30 ) ( * 15312 30 ) - NEW M3 60 ( 26560 15160 30 ) ( 26712 * 30 ) - NEW M1 60 ( 28080 18656 30 ) ( 28232 * 30 ) - NEW M2 60 ( 24432 15130 30 ) ( * 15160 30 ) - NEW M2 60 ( 24432 15160 30 ) ( * 15312 30 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n28 - + ROUTED M2 60 ( 32366 14066 30 ) ( * 14248 30 ) - + USE SIGNAL ; - - U0_UART_RX/strt_glitch - + ROUTED M2 60 ( 34464 33826 30 ) ( * 34008 30 ) - NEW M2 60 ( 34160 34738 30 ) ( * 34920 30 ) - + USE SIGNAL ; - - U0_UART_RX/strt_chk_en - + ROUTED M2 60 ( 34920 34130 30 ) ( * 34201 30 ) - NEW M2 60 ( 34920 34201 30 ) ( * 34312 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_bit_en - + ROUTED M3 60 ( 26039 30360 30 ) ( 26221 * 30 ) - NEW M4 60 ( 26221 30178 30 ) ( * 30360 30 ) - NEW M2 60 ( 21848 21970 30 ) ( * 22152 30 ) - NEW M3 60 ( 21240 27016 30 ) ( 21392 * 30 ) - NEW M3 60 ( 21058 25800 30 ) ( 21088 * 30 ) - NEW M3 60 ( 21088 25800 30 ) ( 21240 * 30 ) - NEW M2 60 ( 21392 26986 30 ) ( * 27016 30 ) - NEW M2 60 ( 21392 27016 30 ) ( * 27168 30 ) - + USE SIGNAL ; - - U0_UART_RX/deser_en - + ROUTED M2 60 ( 31880 22122 30 ) ( * 22152 30 ) - NEW M2 60 ( 31880 22152 30 ) ( * 22304 30 ) - + USE SIGNAL ; - - U0_UART_RX/par_chk_en - + ROUTED M2 60 ( 40696 28050 30 ) ( * 28232 30 ) - + USE SIGNAL ; - - U0_UART_RX/stp_chk_en - + ROUTED M2 60 ( 32792 23490 30 ) ( * 23672 30 ) - NEW M2 60 ( 37808 25314 30 ) ( * 25496 30 ) - + USE SIGNAL ; - - U0_UART_RX/dat_samp_en - + ROUTED M2 60 ( 25040 37200 30 ) ( * 37352 30 ) - NEW M2 60 ( 25040 38872 30 ) ( * 39024 30 ) - NEW M2 60 ( 27776 37170 30 ) ( * 37352 30 ) - NEW M2 60 ( 24280 37170 30 ) ( * 37200 30 ) - NEW M2 60 ( 24280 37200 30 ) ( * 37352 30 ) - NEW M2 60 ( 28232 38842 30 ) ( * 38872 30 ) - NEW M2 60 ( 28232 38872 30 ) ( * 39024 30 ) - + USE SIGNAL ; - - HFSNET_1 - + ROUTED M2 60 ( 17896 7682 30 ) ( * 7864 30 ) - NEW M2 60 ( 18808 7986 30 ) ( * 8168 30 ) - NEW M2 60 ( 36136 11026 30 ) ( * 11208 30 ) - NEW M2 60 ( 37808 17714 30 ) ( * 17896 30 ) - + USE SIGNAL ; - - U0_UART_RX/n4 - + ROUTED M2 60 ( 33552 36866 30 ) ( * 36896 30 ) - NEW M2 60 ( 33552 36896 30 ) ( * 37048 30 ) - NEW M3 60 ( 33370 37048 30 ) ( 33552 * 30 ) - NEW M4 60 ( 33552 36866 30 ) ( * 37048 30 ) - + USE SIGNAL ; - - U0_UART_RX/bit_count[2] - + ROUTED M2 60 ( 25952 25314 30 ) ( * 25369 30 ) - + USE SIGNAL ; - - U0_UART_RX/bit_count[1] - + ROUTED M2 60 ( 18960 25314 30 ) ( * 25496 30 ) - NEW M2 60 ( 20024 25466 30 ) ( * 25496 30 ) - NEW M2 60 ( 20024 25496 30 ) ( * 25648 30 ) - + USE SIGNAL ; - - U0_UART_RX/bit_count[0] - + ROUTED M1 60 ( 20151 25496 30 ) ( 20328 * 30 ) - NEW M2 60 ( 27016 32306 30 ) ( * 32488 30 ) - NEW M2 60 ( 23976 30178 30 ) ( * 30360 30 ) - NEW M3 60 ( 23976 30360 30 ) ( 24158 * 30 ) - NEW M2 60 ( 29904 22274 30 ) ( * 22456 30 ) - NEW M1 60 ( 28992 25496 30 ) ( 29146 * 30 ) - NEW M2 60 ( 28992 25314 30 ) ( * 25496 30 ) - NEW M3 60 ( 28992 25496 30 ) ( 29144 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[5] - + ROUTED M2 60 ( 14096 43858 30 ) ( * 44040 30 ) - NEW M3 60 ( 14096 44040 30 ) ( 14248 * 30 ) - NEW M2 60 ( 14096 21848 30 ) ( * 22000 30 ) - NEW M2 60 ( 14096 21818 30 ) ( * 21848 30 ) - NEW M3 60 ( 14066 21848 30 ) ( 14096 * 30 ) - NEW M3 60 ( 14096 21848 30 ) ( 14248 * 30 ) - NEW M2 60 ( 15160 11938 30 ) ( * 12120 30 ) - NEW M2 60 ( 13792 8594 30 ) ( * 8624 30 ) - NEW M2 60 ( 13792 8624 30 ) ( * 8776 30 ) - NEW M3 60 ( 14218 13944 30 ) ( 14248 * 30 ) - NEW M3 60 ( 14248 13944 30 ) ( 14400 * 30 ) - NEW M2 60 ( 14400 13762 30 ) ( * 13944 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[4] - + ROUTED M2 60 ( 11360 21848 30 ) ( * 22000 30 ) - NEW M2 60 ( 20936 40210 30 ) ( * 40392 30 ) - NEW M2 60 ( 13792 40514 30 ) ( * 40696 30 ) - NEW M2 60 ( 12880 40514 30 ) ( * 40696 30 ) - NEW M2 60 ( 12880 5098 30 ) ( * 5128 30 ) - NEW M2 60 ( 12880 5128 30 ) ( * 5280 30 ) - NEW M2 60 ( 9840 11938 30 ) ( * 12120 30 ) - NEW M3 60 ( 9810 12120 30 ) ( 9840 * 30 ) - NEW M3 60 ( 9840 12120 30 ) ( 9992 * 30 ) - NEW M3 60 ( 11938 28536 30 ) ( 12120 * 30 ) - NEW M2 60 ( 12120 28506 30 ) ( * 28536 30 ) - NEW M2 60 ( 12120 28536 30 ) ( * 28688 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[3] - + ROUTED M2 60 ( 9232 24098 30 ) ( * 24128 30 ) - NEW M2 60 ( 9232 24128 30 ) ( * 24280 30 ) - NEW M3 60 ( 9202 24280 30 ) ( 9232 * 30 ) - NEW M3 60 ( 9232 24280 30 ) ( 9384 * 30 ) - NEW M2 60 ( 8776 13762 30 ) ( * 13944 30 ) - NEW M2 60 ( 10904 30786 30 ) ( * 30816 30 ) - NEW M2 60 ( 10904 30816 30 ) ( * 30968 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[2] - + ROUTED M2 60 ( 15008 33826 30 ) ( * 34008 30 ) - NEW M2 60 ( 9840 33826 30 ) ( * 34008 30 ) - NEW M3 60 ( 9840 34008 30 ) ( 9992 * 30 ) - NEW M1 60 ( 9383 37352 30 ) ( 9536 * 30 ) - NEW M2 60 ( 9536 37170 30 ) ( * 37352 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[1] - + ROUTED M2 60 ( 20176 27594 30 ) ( * 27624 30 ) - NEW M2 60 ( 20176 27624 30 ) ( * 27776 30 ) - NEW M2 60 ( 8320 31850 30 ) ( * 31880 30 ) - NEW M2 60 ( 8320 31880 30 ) ( * 32032 30 ) - NEW M3 60 ( 13640 17592 30 ) ( 13792 * 30 ) - NEW M2 60 ( 13792 27442 30 ) ( * 27472 30 ) - NEW M2 60 ( 13792 27472 30 ) ( * 27624 30 ) - NEW M3 60 ( 13640 27624 30 ) ( 13792 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[0] - + ROUTED M2 60 ( 16072 18930 30 ) ( * 18960 30 ) - NEW M2 60 ( 16072 18960 30 ) ( * 19112 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_5_ - + ROUTED M2 60 ( 7560 10241 30 ) ( * 10296 30 ) - NEW M2 60 ( 7560 10296 30 ) ( * 10423 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_4_ - + ROUTED M2 60 ( 12576 5250 30 ) ( * 5432 30 ) - NEW M2 60 ( 6800 5402 30 ) ( * 5432 30 ) - NEW M2 60 ( 6800 5432 30 ) ( * 5584 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_3_ - + ROUTED M2 60 ( 6800 6770 30 ) ( * 6952 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_1_ - + ROUTED M2 60 ( 13488 27138 30 ) ( * 27320 30 ) - NEW M2 60 ( 11360 27290 30 ) ( * 27320 30 ) - NEW M2 60 ( 11360 27320 30 ) ( * 27472 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n1 - + ROUTED M2 60 ( 38872 26834 30 ) ( * 27016 30 ) - NEW M2 60 ( 33248 28810 30 ) ( * 28840 30 ) - NEW M2 60 ( 33248 28840 30 ) ( * 28992 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n2 - + ROUTED M2 60 ( 34768 28962 30 ) ( * 29144 30 ) - NEW M2 60 ( 33552 28962 30 ) ( * 28992 30 ) - NEW M2 60 ( 33552 28992 30 ) ( * 29144 30 ) - NEW M2 60 ( 28992 33218 30 ) ( * 33400 30 ) - NEW M3 60 ( 32488 29144 30 ) ( 32640 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n3 - + ROUTED M2 60 ( 5888 24098 30 ) ( * 24280 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n4 - + ROUTED M1 132 ( 3239 24244 66 ) ( 3263 * 66 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n5 - + ROUTED M2 60 ( 4216 22274 30 ) ( * 22456 30 ) - NEW M2 60 ( 5888 22324 30 ) ( * 22456 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n6 - + ROUTED M2 60 ( 7712 21970 30 ) ( * 22000 30 ) - NEW M2 60 ( 7712 22000 30 ) ( * 22152 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n7 - + ROUTED M1 60 ( 7453 24169 30 ) ( 7712 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n8 - + ROUTED M2 60 ( 5736 24706 30 ) ( * 24888 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n13 - + ROUTED M2 60 ( 33096 31394 30 ) ( * 31576 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n14 - + ROUTED M2 60 ( 31880 30178 30 ) ( * 30360 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n16 - + ROUTED M2 60 ( 34464 25668 30 ) ( * 25800 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n19 - + ROUTED M2 60 ( 34312 25364 30 ) ( * 25496 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n20 - + ROUTED M2 60 ( 17744 25010 30 ) ( * 25192 30 ) - NEW M2 60 ( 30360 25314 30 ) ( * 25496 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n22 - + ROUTED M2 60 ( 32336 22274 30 ) ( * 22456 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n23 - + ROUTED M1 60 ( 29503 25344 30 ) ( 29600 * 30 ) - NEW M2 60 ( 30208 25618 30 ) ( * 25648 30 ) - NEW M2 60 ( 30208 25648 30 ) ( * 25800 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n24 - + ROUTED M1 60 ( 31576 22152 30 ) ( 31753 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n25 - + ROUTED M2 60 ( 35376 30482 30 ) ( * 30664 30 ) - NEW M2 60 ( 33896 30482 30 ) ( * 30664 30 ) - NEW M1 80 ( 33881 30609 40 ) ( * 30654 40 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n27 - + ROUTED M2 60 ( 34312 33370 30 ) ( * 33400 30 ) - NEW M2 60 ( 34312 33400 30 ) ( * 33552 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n28 - + ROUTED M2 60 ( 33400 31090 30 ) ( * 31272 30 ) - NEW M2 60 ( 30208 32306 30 ) ( * 32336 30 ) - NEW M2 60 ( 30208 32336 30 ) ( * 32488 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n29 - + ROUTED M1 90 ( 30948 27188 45 ) ( * 27212 45 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n30 - + ROUTED M2 60 ( 29144 27442 30 ) ( * 27472 30 ) - NEW M2 60 ( 29144 27472 30 ) ( * 27624 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n33 - + ROUTED M1 60 ( 27776 25800 30 ) ( 27948 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n34 - + ROUTED M1 60 ( 27756 25496 30 ) ( 27928 * 30 ) - NEW M2 60 ( 19568 21666 30 ) ( * 21848 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n36 - + ROUTED M2 60 ( 15008 8138 30 ) ( * 8168 30 ) - NEW M2 60 ( 15008 8168 30 ) ( * 8320 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n39 - + ROUTED M2 60 ( 17136 23490 30 ) ( * 23672 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n41 - + ROUTED M2 60 ( 16984 23794 30 ) ( * 23976 30 ) - NEW M2 60 ( 30968 23794 30 ) ( * 23976 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n43 - + ROUTED M2 60 ( 18352 24098 30 ) ( * 24169 30 ) - NEW M2 60 ( 18352 24169 30 ) ( * 24280 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n44 - + ROUTED M2 60 ( 31728 30482 30 ) ( * 30664 30 ) - NEW M2 60 ( 31120 30330 30 ) ( * 30360 30 ) - NEW M2 60 ( 31120 30360 30 ) ( * 30512 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n45 - + ROUTED M2 60 ( 11816 21058 30 ) ( * 21088 30 ) - NEW M2 60 ( 11816 21088 30 ) ( * 21240 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n47 - + ROUTED M1 74 ( 13251 7086 37 ) ( * 7244 37 ) - NEW M1 74 ( 13324 7086 37 ) ( * 7244 37 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n51 - + ROUTED M2 60 ( 16984 25162 30 ) ( * 25192 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n52 - + ROUTED M2 60 ( 13640 24858 30 ) ( * 24888 30 ) - NEW M2 60 ( 13640 24888 30 ) ( * 25040 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n59 - + ROUTED M2 60 ( 33856 28840 30 ) ( * 28992 30 ) - NEW M2 60 ( 43888 28658 30 ) ( * 28840 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[5] - + ROUTED M2 60 ( 13792 21970 30 ) ( * 22152 30 ) - NEW M2 60 ( 9080 22122 30 ) ( * 22152 30 ) - NEW M2 60 ( 9080 22152 30 ) ( * 22304 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[4] - + ROUTED M2 60 ( 5736 21058 30 ) ( * 21088 30 ) - NEW M2 60 ( 5736 21088 30 ) ( * 21240 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[3] - + ROUTED M2 60 ( 5432 23186 30 ) ( * 23368 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[2] - + ROUTED M2 60 ( 6192 25922 30 ) ( * 26104 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[1] - + ROUTED M2 60 ( 8208 25314 30 ) ( * 25496 30 ) - NEW M2 60 ( 12120 25314 30 ) ( * 25496 30 ) - NEW M1 80 ( 8193 25506 40 ) ( * 25551 40 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/sub_40_carry[4] - + ROUTED M2 60 ( 4824 8290 30 ) ( * 8472 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N8 - + ROUTED M2 60 ( 16984 32184 30 ) ( * 32336 30 ) - NEW M2 60 ( 16984 32154 30 ) ( * 32184 30 ) - NEW M2 60 ( 15920 32154 30 ) ( * 32184 30 ) - NEW M2 60 ( 15920 32184 30 ) ( * 32336 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N11 - + ROUTED M1 60 ( 15768 39024 30 ) ( 15945 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N26 - + ROUTED M2 60 ( 11512 19234 30 ) ( * 19416 30 ) - NEW M2 60 ( 19506 17106 30 ) ( * 17288 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N28 - + ROUTED M2 60 ( 9424 7074 30 ) ( * 7256 30 ) - NEW M1 80 ( 9409 7201 40 ) ( * 7246 40 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N31 - + ROUTED M2 60 ( 21088 18930 30 ) ( * 18960 30 ) - NEW M2 60 ( 21088 18960 30 ) ( * 19112 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/dftopt7_gOb13 - + ROUTED M2 60 ( 26864 27138 30 ) ( * 27320 30 ) - NEW M2 60 ( 23976 27290 30 ) ( * 27320 30 ) - NEW M2 60 ( 23976 27320 30 ) ( * 27472 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/dftopt8_gOb14 - + ROUTED M1 60 ( 20759 32184 30 ) ( 20936 * 30 ) - NEW M2 60 ( 27198 31698 30 ) ( * 31880 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n19 - + ROUTED M2 60 ( 20176 21058 30 ) ( * 21240 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n22 - + ROUTED M2 60 ( 21696 20450 30 ) ( * 20480 30 ) - NEW M2 60 ( 21696 20480 30 ) ( * 20632 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n23 - + ROUTED M1 60 ( 21240 20632 30 ) ( 21392 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n24 - + ROUTED M2 60 ( 23672 25618 30 ) ( * 25800 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n25 - + ROUTED M2 60 ( 23368 24706 30 ) ( * 24888 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n26 - + ROUTED M2 60 ( 23520 25344 30 ) ( * 25496 30 ) - NEW M2 60 ( 22608 25314 30 ) ( * 25496 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n28 - + ROUTED M2 60 ( 23672 31090 30 ) ( * 31272 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n1 - + ROUTED M2 60 ( 18960 32154 30 ) ( * 32184 30 ) - NEW M2 60 ( 18960 32184 30 ) ( * 32336 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n17 - + ROUTED M2 60 ( 8472 7074 30 ) ( * 7256 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n33 - + ROUTED M2 60 ( 8320 7378 30 ) ( * 7560 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n34 - + ROUTED M2 60 ( 8624 8442 30 ) ( * 8472 30 ) - NEW M2 60 ( 8624 8472 30 ) ( * 8624 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n35 - + ROUTED M1 60 ( 10904 18200 30 ) ( 11056 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n37 - + ROUTED M2 60 ( 8624 4034 30 ) ( * 4064 30 ) - NEW M2 60 ( 8624 4064 30 ) ( * 4216 30 ) - NEW M2 60 ( 6344 4034 30 ) ( * 4064 30 ) - NEW M2 60 ( 6344 4064 30 ) ( * 4216 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n46 - + ROUTED M1 60 ( 15616 15312 30 ) ( 15713 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n47 - + ROUTED M1 60 ( 17440 17440 30 ) ( 17537 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n48 - + ROUTED M2 60 ( 16680 42034 30 ) ( * 42216 30 ) - NEW M2 60 ( 17440 35346 30 ) ( * 35528 30 ) - NEW M3 60 ( 16984 35528 30 ) ( 17136 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n49 - + ROUTED M1 60 ( 20632 24584 30 ) ( 20784 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n53 - + ROUTED M2 60 ( 21544 36410 30 ) ( * 36440 30 ) - NEW M2 60 ( 21544 36440 30 ) ( * 36592 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/add_31_carry[3] - + ROUTED M1 58 ( 15286 37448 29 ) ( 15384 * 29 ) - NEW M1 58 ( 15286 37505 29 ) ( 15384 * 29 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/N58 - + ROUTED M2 60 ( 28840 38690 30 ) ( * 38720 30 ) - NEW M2 60 ( 28840 38720 30 ) ( * 38872 30 ) - NEW M2 60 ( 31272 38690 30 ) ( * 38872 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n23 - + ROUTED M2 60 ( 20480 39602 30 ) ( * 39632 30 ) - NEW M2 60 ( 20480 39632 30 ) ( * 39784 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n25 - + ROUTED M2 60 ( 21392 34890 30 ) ( * 34920 30 ) - NEW M2 60 ( 21392 34920 30 ) ( * 35072 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n1 - + ROUTED M1 60 ( 23368 37352 30 ) ( 23545 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n2 - + ROUTED M2 60 ( 28080 43604 30 ) ( * 43736 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n3 - + ROUTED M1 60 ( 3912 30664 30 ) ( 4064 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n14 - + ROUTED M2 60 ( 8320 44010 30 ) ( * 44040 30 ) - NEW M2 60 ( 8320 44040 30 ) ( * 44192 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n16 - + ROUTED M1 60 ( 5736 44040 30 ) ( 5913 * 30 ) - NEW M2 60 ( 4976 41882 30 ) ( * 41912 30 ) - NEW M2 60 ( 4976 41912 30 ) ( * 42064 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n17 - + ROUTED M2 60 ( 24584 36562 30 ) ( * 36744 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n18 - + ROUTED M2 60 ( 27016 37474 30 ) ( * 37529 30 ) - NEW M2 60 ( 27016 37529 30 ) ( * 37656 30 ) - NEW M2 60 ( 19168 38538 30 ) ( * 38568 30 ) - NEW M2 60 ( 19168 38568 30 ) ( * 38720 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n22 - + ROUTED M2 60 ( 12728 38082 30 ) ( * 38264 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n27 - + ROUTED M2 60 ( 19720 38690 30 ) ( * 38872 30 ) - NEW M2 60 ( 11208 36866 30 ) ( * 37034 30 ) - NEW M2 60 ( 13032 36866 30 ) ( * 37048 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n28 - + ROUTED M2 60 ( 14552 38538 30 ) ( * 38568 30 ) - NEW M2 60 ( 14552 38568 30 ) ( * 38720 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n30 - + ROUTED M2 60 ( 12880 32052 30 ) ( * 32184 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n33 - + ROUTED M1 60 ( 25167 37352 30 ) ( 25344 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n34 - + ROUTED M2 60 ( 23672 38690 30 ) ( * 38720 30 ) - NEW M2 60 ( 23672 38720 30 ) ( * 38872 30 ) - NEW M2 60 ( 21752 38720 30 ) ( * 38872 30 ) - NEW M2 60 ( 21752 38690 30 ) ( * 38720 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n35 - + ROUTED M2 60 ( 12272 38994 30 ) ( * 39176 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n36 - + ROUTED M2 60 ( 13032 41578 30 ) ( * 41760 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n37 - + ROUTED M1 60 ( 11816 39176 30 ) ( 11993 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n39 - + ROUTED M1 60 ( 8988 35528 30 ) ( 9232 * 30 ) - NEW M2 60 ( 9232 35346 30 ) ( * 35528 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n40 - + ROUTED M1 60 ( 12728 37352 30 ) ( 12905 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n41 - + ROUTED M2 60 ( 13336 34160 30 ) ( * 34312 30 ) - NEW M1 118 ( 13340 34106 59 ) ( * 34131 59 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n43 - + ROUTED M1 118 ( 8316 42093 59 ) ( * 42118 59 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n44 - + ROUTED M1 118 ( 11668 44138 59 ) ( * 44163 59 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n45 - + ROUTED M1 60 ( 8928 37504 30 ) ( 9025 * 30 ) - NEW M2 60 ( 8928 37474 30 ) ( * 37504 30 ) - NEW M2 60 ( 8928 37504 30 ) ( * 37656 30 ) - NEW M2 60 ( 7256 37474 30 ) ( * 37504 30 ) - NEW M2 60 ( 7256 37504 30 ) ( * 37656 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n46 - + ROUTED M2 60 ( 20176 38994 30 ) ( * 39176 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n48 - + ROUTED M2 60 ( 6040 36562 30 ) ( * 36744 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[4] - + ROUTED M2 60 ( 11360 42034 30 ) ( * 42216 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[3] - + ROUTED M2 60 ( 9384 40514 30 ) ( * 40696 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[2] - + ROUTED M2 60 ( 6952 37170 30 ) ( * 37352 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[1] - + ROUTED M2 60 ( 7256 35346 30 ) ( * 35528 30 ) - NEW M2 60 ( 5888 35498 30 ) ( * 35528 30 ) - NEW M2 60 ( 5888 35528 30 ) ( * 35680 30 ) - NEW M2 60 ( 3912 35498 30 ) ( * 35528 30 ) - NEW M2 60 ( 3912 35528 30 ) ( * 35680 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_p1[1] - + ROUTED M2 60 ( 8016 32002 30 ) ( * 32184 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_n1[4] - + ROUTED M2 60 ( 9688 43858 30 ) ( * 43888 30 ) - NEW M2 60 ( 9688 43888 30 ) ( * 44040 30 ) - NEW M2 60 ( 12120 43858 30 ) ( * 44040 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_n1[3] - + ROUTED M2 60 ( 7864 42034 30 ) ( * 42216 30 ) - NEW M2 60 ( 6344 42186 30 ) ( * 42216 30 ) - NEW M2 60 ( 6344 42216 30 ) ( * 42368 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N3 - + ROUTED M1 80 ( 6369 15474 40 ) ( * 15519 40 ) - NEW M2 60 ( 11208 15282 30 ) ( * 15312 30 ) - NEW M2 60 ( 11208 15312 30 ) ( * 15464 30 ) - NEW M2 60 ( 6384 15282 30 ) ( * 15464 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N4 - + ROUTED M2 60 ( 6496 13458 30 ) ( * 13640 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N5 - + ROUTED M2 60 ( 5280 12546 30 ) ( * 12728 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N6 - + ROUTED M1 80 ( 8791 11826 40 ) ( * 11874 40 ) - NEW M1 118 ( 14708 11997 59 ) ( * 12022 59 ) - NEW M2 60 ( 8776 11634 30 ) ( * 11816 30 ) - NEW M2 60 ( 14704 11786 30 ) ( * 11816 30 ) - NEW M2 60 ( 14704 11816 30 ) ( * 11968 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n1 - + ROUTED M2 60 ( 39024 42034 30 ) ( * 42216 30 ) - NEW M2 60 ( 37200 38690 30 ) ( * 38872 30 ) - NEW M3 60 ( 38416 38872 30 ) ( 38568 * 30 ) - NEW M2 60 ( 37504 33826 30 ) ( * 34008 30 ) - NEW M2 60 ( 35680 32002 30 ) ( * 32184 30 ) - NEW M3 60 ( 35498 32184 30 ) ( 35680 * 30 ) - NEW M2 60 ( 35528 22730 30 ) ( * 22912 30 ) - NEW M3 60 ( 35346 22912 30 ) ( 35528 * 30 ) - NEW M2 60 ( 37048 43858 30 ) ( * 44040 30 ) - NEW M3 60 ( 38538 40392 30 ) ( 38568 * 30 ) - NEW M3 60 ( 38568 40392 30 ) ( 38720 * 30 ) - NEW M2 60 ( 38416 38690 30 ) ( * 38872 30 ) - NEW M1 60 ( 34008 42216 30 ) ( 34160 * 30 ) - NEW M2 60 ( 34160 42034 30 ) ( * 42216 30 ) - NEW M2 60 ( 36440 43858 30 ) ( * 44040 30 ) - NEW M3 60 ( 36106 36136 30 ) ( 36136 * 30 ) - NEW M3 60 ( 36136 36136 30 ) ( 36288 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n20 - + ROUTED M2 60 ( 29600 43858 30 ) ( * 44040 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n26 - + ROUTED M2 60 ( 41152 38690 30 ) ( * 38872 30 ) - NEW M2 60 ( 39368 38690 30 ) ( * 38872 30 ) - NEW M1 80 ( 39353 38882 40 ) ( * 38937 40 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n2 - + ROUTED M1 126 ( 4026 15502 63 ) ( * 15608 63 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n3 - + ROUTED M2 60 ( 4824 13762 30 ) ( * 13944 30 ) - NEW M2 60 ( 5584 13762 30 ) ( * 13944 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n4 - + ROUTED M2 60 ( 5888 14552 30 ) ( * 14656 30 ) - NEW M2 60 ( 5888 14448 30 ) ( * 14552 30 ) - NEW M1 60 ( 5888 14552 30 ) ( 6040 * 30 ) - NEW M2 60 ( 6040 12292 30 ) ( * 12424 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n5 - + ROUTED M2 60 ( 7560 11938 30 ) ( * 11968 30 ) - NEW M2 60 ( 7560 11968 30 ) ( * 12120 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n8 - + ROUTED M2 60 ( 4064 11786 30 ) ( * 11816 30 ) - NEW M2 60 ( 4064 11816 30 ) ( * 11968 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n11 - + ROUTED M2 60 ( 10296 13002 30 ) ( * 13032 30 ) - NEW M2 60 ( 10296 13032 30 ) ( * 13184 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n12 - + ROUTED M2 60 ( 12424 16346 30 ) ( * 16528 30 ) - NEW M3 60 ( 12242 16528 30 ) ( 12424 * 30 ) - NEW M2 60 ( 12728 16802 30 ) ( * 16984 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n14 - + ROUTED M1 110 ( 13640 15337 55 ) ( * 15349 55 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n33 - + ROUTED M1 60 ( 12880 15312 30 ) ( 12977 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n34 - + ROUTED M1 60 ( 10047 15312 30 ) ( 10144 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n35 - + ROUTED M2 60 ( 12470 17106 30 ) ( * 17136 30 ) - NEW M2 60 ( 12470 17136 30 ) ( * 17288 30 ) - NEW M2 60 ( 13488 17258 30 ) ( * 17288 30 ) - NEW M2 60 ( 13488 17288 30 ) ( * 17440 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n43 - + ROUTED M2 60 ( 33552 41426 30 ) ( * 41608 30 ) - NEW M2 60 ( 36744 38082 30 ) ( * 38264 30 ) - NEW M3 60 ( 35832 34920 30 ) ( 36014 * 30 ) - NEW M2 60 ( 39480 41426 30 ) ( * 41608 30 ) - NEW M1 60 ( 37656 34160 30 ) ( 37808 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_strt_chk/n3 - + ROUTED M2 60 ( 29296 37170 30 ) ( * 37352 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_strt_chk/n1 - + ROUTED M1 60 ( 33455 35376 30 ) ( 33552 * 30 ) - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n2 - + ROUTED M1 60 ( 39991 31880 30 ) ( 40088 * 30 ) - NEW M1 60 ( 40392 28688 30 ) ( 40544 * 30 ) - + USE SIGNAL ; - - dftopt2 - + ROUTED M1 60 ( 36288 23368 30 ) ( 36472 * 30 ) - + USE SIGNAL ; - - VDD - ( PIN VDD ) - ( * VDD ) - + ROUTED M7 500 + SHAPE STRIPE ( 3000 8000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 16000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 24000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 32000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 40000 ) ( 45712 * ) - NEW M8 500 + SHAPE STRIPE ( 8000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 16000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 24000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 32000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 40000 3000 ) ( * 44800 ) - NEW M7 56 + SHAPE STRIPE ( 8000 8000 ) VIA78LG_C_3_2 DO 1 BY 5 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 16000 8000 ) VIA78LG_C_3_2 DO 1 BY 5 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 24000 8000 ) VIA78LG_C_3_2 DO 1 BY 5 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 32000 8000 ) VIA78LG_C_3_2 DO 1 BY 5 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 40000 8000 ) VIA78LG_C_3_2 DO 1 BY 5 STEP 0 8000 - NEW M1 60 + SHAPE IOWIRE ( 3000 3000 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 6344 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 9688 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 13032 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 16376 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 19720 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 23064 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 26408 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 29752 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 33096 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 36440 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 39784 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 43128 ) ( 45712 * ) - + USE POWER ; - - VSS - ( PIN VSS ) - ( * VSS ) - + ROUTED M7 500 + SHAPE STRIPE ( 3000 4000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 12000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 20000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 28000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 36000 ) ( 45712 * ) - NEW M7 500 + SHAPE STRIPE ( 3000 44000 ) ( 45712 * ) - NEW M8 500 + SHAPE STRIPE ( 4000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 12000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 20000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 28000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 36000 3000 ) ( * 44800 ) - NEW M8 500 + SHAPE STRIPE ( 44000 3000 ) ( * 44800 ) - NEW M7 56 + SHAPE STRIPE ( 4000 4000 ) VIA78LG_C_3_2 DO 1 BY 6 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 12000 4000 ) VIA78LG_C_3_2 DO 1 BY 6 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 20000 4000 ) VIA78LG_C_3_2 DO 1 BY 6 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 28000 4000 ) VIA78LG_C_3_2 DO 1 BY 6 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 36000 4000 ) VIA78LG_C_3_2 DO 1 BY 6 STEP 0 8000 - NEW M7 56 + SHAPE STRIPE ( 44000 4000 ) VIA78LG_C_3_2 DO 1 BY 6 STEP 0 8000 - NEW M1 60 + SHAPE IOWIRE ( 3000 4672 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 8016 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 11360 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 14704 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 18048 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 21392 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 24736 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 28080 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 31424 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 34768 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 38112 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 41456 ) ( 45712 * ) - NEW M1 60 + SHAPE IOWIRE ( 3000 44800 ) ( 45712 * ) - + USE GROUND ; - - U0_UART_RX/dftopt0 - + ROUTED M1 60 ( 28055 42216 30 ) ( 28232 * 30 ) - NEW M2 60 ( 29752 43250 30 ) ( * 43432 30 ) - NEW M1 60 ( 29752 43432 30 ) ( 29936 * 30 ) - NEW M2 60 ( 28384 43432 30 ) ( * 43584 30 ) - + USE SIGNAL ; - - U0_UART_TX/dftopt0 - + ROUTED M2 60 ( 38416 13154 30 ) ( * 13336 30 ) - NEW M1 60 ( 35832 16680 30 ) ( 36016 * 30 ) - + USE SIGNAL ; - - U0_UART_TX/dftopt3 - + ROUTED M1 60 ( 38568 22152 30 ) ( 38745 * 30 ) - NEW M2 60 ( 39784 20146 30 ) ( * 20176 30 ) - NEW M2 60 ( 39784 20176 30 ) ( * 20328 30 ) - + USE SIGNAL ; - - U0_UART_RX/dftopt3 - + ROUTED M2 60 ( 27016 33572 30 ) ( * 33704 30 ) - NEW M2 60 ( 32792 33522 30 ) ( * 33552 30 ) - NEW M2 60 ( 32792 33552 30 ) ( * 33704 30 ) - + USE SIGNAL ; - - dftopt15 - + ROUTED M2 60 ( 26256 16802 30 ) ( * 16984 30 ) - + USE SIGNAL ; - - U0_UART_TX/dftopt5 - + ROUTED M2 60 ( 20632 10114 30 ) ( * 10296 30 ) - NEW M2 60 ( 22152 10114 30 ) ( * 10296 30 ) - NEW M1 60 ( 22152 10296 30 ) ( 22304 * 30 ) - + USE SIGNAL ; - - optlc_net_427 - + ROUTED M2 60 ( 42520 14370 30 ) ( * 14552 30 ) - + USE SIGNAL ; - - U0_UART_RX/dftopt18 - + ROUTED M2 60 ( 22152 34434 30 ) ( * 34589 30 ) - NEW M1 60 ( 23216 36136 30 ) ( 23400 * 30 ) - + USE SIGNAL ; - - dftopt19 - + ROUTED M2 60 ( 20480 26530 30 ) ( * 26712 30 ) - + USE SIGNAL ; -END SPECIALNETS -NETS 439 ; - - RST - ( PIN RST ) - ( U2_mux2X1/U1 A1 ) - + ROUTED M6 ( 22456 258 ) ( * 4064 ) VIA56SQ_C VIA45SQ_C W VIA34SQ_C VIA23SQ_C W - NEW M2 ( 22208 4064 ) ( 22456 * ) - NEW M1 ( 22208 4064 ) VIA12SQ_C - + USE SIGNAL ; - - TX_CLK - ( PIN TX_CLK ) - ( U1_mux2X1/IN_0_btd306 A ) - + ROUTED M4 ( 20936 258 ) ( * 3912 ) VIA34SQ_C - NEW M3 ( 20328 3912 ) ( 20936 * ) - NEW M2 ( 20328 3912 ) VIA23SQ_C W - NEW M1 ( 20328 3912 ) VIA12SQ_C - + USE CLOCK ; - - RX_CLK - ( PIN RX_CLK ) - ( U0_mux2X1/IN_0_btd307 A ) - + ROUTED M3 ( 258 24280 ) ( 872 * ) VIA34SQ_C ( * 25496 ) VIA34SQ_C ( 3304 * ) VIA23SQ_C W VIA12SQ_C - + USE CLOCK ; - - RX_IN_S - ( PIN RX_IN_S ) - ( U0_UART_RX/U0_data_sampling/U61 A1 ) - ( U0_UART_RX/U0_uart_fsm/U79 A2 ) - ( U0_UART_RX/U0_uart_fsm/U71 A ) - + ROUTED M1 ( 27320 30664 ) VIA12SQ_C VIA23SQ_C W ( 27624 * ) - NEW M1 ( 29448 30664 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 27624 30664 ) ( 29448 * ) - NEW M3 ( 27624 30664 ) VIA34SQ_C ( * 37048 ) VIA34SQ_C VIA23SQ_C W - NEW M1 ( 27624 37200 ) VIA12SQ_C - NEW M4 ( 30360 46472 ) ( * 47542 ) - NEW M3 ( 30360 46472 ) VIA34SQ_C - NEW M3 ( 27624 46472 ) ( 30360 * ) - NEW M2 ( 27624 46472 ) VIA23SQ_C W - NEW M2 ( 27624 37200 ) ( * 46472 ) - + USE SIGNAL ; - - RX_OUT_P[7] - ( PIN RX_OUT_P[7] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ Q ) - ( U0_UART_RX/U0_deserializer/U16 A2 ) - ( U0_UART_RX/U0_deserializer/U14 A4 ) - ( U0_UART_RX/U0_par_chk/U4 A1 ) - + ROUTED M5 ( 47384 35224 ) ( 48454 * ) - NEW M4 ( 47384 35224 ) VIA45SQ_C W - NEW M4 ( 47384 34312 ) ( * 35224 ) - NEW M3 ( 47384 34312 ) VIA34SQ_C - NEW M3 ( 45256 34312 ) ( 47384 * ) - NEW M1 ( 45256 32488 ) VIA12SQ_C ( * 34312 ) VIA23SQ_C W - NEW M1 ( 37352 33704 ) ( 37626 * ) - NEW M1 ( 37352 33704 ) VIA12SQ_C ( * 34616 ) VIA23SQ_C W ( 44496 * ) - NEW M3 ( 44496 34312 ) ( * 34616 ) - NEW M3 ( 44496 34312 ) ( 45256 * ) - NEW M1 ( 36136 35376 ) VIA12SQ_C - NEW M2 ( 36136 34616 ) ( * 35376 ) - NEW M2 ( 36136 34616 ) VIA23SQ_C W ( 37352 * ) - NEW M1 ( 44496 34160 ) VIA12SQ_C - NEW M2 ( 44496 34312 ) VIA23SQ_C W - + USE SIGNAL ; - - RX_OUT_P[6] - ( PIN RX_OUT_P[6] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ Q ) - ( U0_UART_RX/U0_deserializer/U14 A2 ) - ( U0_UART_RX/U0_deserializer/U12 A4 ) - ( U0_UART_RX/U0_par_chk/U4 A2 ) - + ROUTED M2 ( 44192 36136 ) ( * 37656 ) VIA23SQ_C W - NEW M1 ( 41797 35832 ) VIA12SQ_C W ( * 36136 ) VIA23SQ_C W ( 44192 * ) VIA23SQ_C W - NEW M3 ( 37048 38568 ) VIA34SQ_C - NEW M4 ( 37048 38264 ) ( * 38568 ) - NEW M4 ( 37048 38264 ) VIA45SQ_C W ( 44344 * ) VIA45SQ_C W - NEW M4 ( 44344 37656 ) ( * 38264 ) - NEW M3 ( 44344 37656 ) VIA34SQ_C - NEW M1 ( 36136 35832 ) VIA12SQ_C ( * 38568 ) VIA23SQ_C W ( 36871 * ) - NEW M1 ( 44800 34008 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 44192 34008 ) ( 44800 * ) - NEW M2 ( 44192 34008 ) VIA23SQ_C W - NEW M2 ( 44192 34008 ) ( * 36136 ) - NEW M3 ( 44344 37656 ) ( 48454 * ) - NEW M2 ( 36896 38568 ) VIA23SQ_C W - NEW M1 ( 36896 38720 ) VIA12SQ_C - + USE SIGNAL ; - - RX_OUT_P[5] - ( PIN RX_OUT_P[5] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ Q ) - ( U0_UART_RX/U0_deserializer/U12 A2 ) - ( U0_UART_RX/U0_deserializer/U10 A4 ) - ( U0_UART_RX/U0_par_chk/U7 A2 ) - + ROUTED M3 ( 44952 35528 ) ( 48454 * ) - NEW M2 ( 44952 35528 ) VIA23SQ_C W - NEW M1 ( 38720 38720 ) VIA12SQ_C - NEW M1 ( 44952 35528 ) VIA12SQ_C - NEW M1 ( 37078 39176 ) ( 37504 * ) VIA12SQ_C - NEW M2 ( 37504 38568 ) ( * 39176 ) - NEW M2 ( 37504 38568 ) VIA23SQ_C W ( 38720 * ) VIA23SQ_C W - NEW M1 ( 41304 37048 ) VIA12SQ_C - NEW M1 ( 41304 37048 ) ( 44952 * ) VIA12SQ_C - NEW M2 ( 44952 35528 ) ( * 37048 ) - NEW M2 ( 38720 37656 ) ( * 38543 ) - NEW M2 ( 38720 37656 ) VIA23SQ_C W ( 41304 * ) VIA23SQ_C W - NEW M2 ( 41304 37048 ) ( * 37656 ) - NEW M2 ( 40544 37048 ) ( 41304 * ) - NEW M1 ( 40544 37048 ) VIA12SQ_C - + USE SIGNAL ; - - RX_OUT_P[4] - ( PIN RX_OUT_P[4] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ Q ) - ( U0_UART_RX/U0_deserializer/U10 A2 ) - ( U0_UART_RX/U0_deserializer/U8 A4 ) - ( U0_UART_RX/U0_par_chk/U7 A1 ) - + ROUTED M3 ( 45104 39784 ) ( 48454 * ) - NEW M2 ( 45104 39784 ) VIA23SQ_C W - NEW M1 ( 45408 39176 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 45104 39176 ) ( 45408 * ) - NEW M2 ( 45104 39176 ) ( * 39784 ) - NEW M2 ( 45104 39176 ) VIA23SQ_C W - NEW M1 ( 44648 36288 ) VIA12SQ_C ( * 39176 ) VIA23SQ_C W ( 45104 * ) - NEW M2 ( 45104 39784 ) ( * 40696 ) VIA23SQ_C W - NEW M3 ( 39024 40696 ) ( 45104 * ) - NEW M2 ( 39024 40696 ) VIA23SQ_C W - NEW M1 ( 39024 40848 ) VIA12SQ_C - NEW M1 ( 38568 39176 ) VIA12SQ_C ( * 40696 ) VIA23SQ_C W ( 39024 * ) - + USE SIGNAL ; - - RX_OUT_P[3] - ( PIN RX_OUT_P[3] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ Q ) - ( U0_UART_RX/U0_deserializer/U8 A2 ) - ( U0_UART_RX/U0_deserializer/U6 A4 ) - ( U0_UART_RX/U0_par_chk/U6 A1 ) - + ROUTED M4 ( 41608 44344 ) ( * 47542 ) - NEW M3 ( 41608 44344 ) VIA34SQ_C - NEW M1 ( 45408 43736 ) VIA12SQ_C ( * 44344 ) VIA23SQ_C W - NEW M3 ( 41608 44344 ) ( 45408 * ) - NEW M1 ( 39328 42064 ) VIA12SQ_C ( * 44040 ) VIA23SQ_C W ( 41608 * ) - NEW M3 ( 41608 44040 ) ( * 44344 ) - NEW M2 ( 39328 40392 ) ( * 42064 ) - NEW M2 ( 39024 40392 ) ( 39328 * ) - NEW M1 ( 39024 40392 ) VIA12SQ_C - NEW M3 ( 38568 44040 ) ( 39328 * ) - NEW M2 ( 38568 44040 ) VIA23SQ_C W - NEW M1 ( 38568 44192 ) VIA12SQ_C - + USE SIGNAL ; - - RX_OUT_P[2] - ( PIN RX_OUT_P[2] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ Q ) - ( U0_UART_RX/U0_deserializer/U6 A2 ) - ( U0_UART_RX/U0_deserializer/U4 A4 ) - ( U0_UART_RX/U0_par_chk/U6 A2 ) - + ROUTED M4 ( 38872 44344 ) ( * 47542 ) - NEW M3 ( 38872 44344 ) VIA34SQ_C - NEW M1 ( 39176 42520 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 38872 44040 ) VIA12SQ_C - NEW M3 ( 38872 42520 ) ( 39176 * ) - NEW M2 ( 38872 42520 ) VIA23SQ_C W - NEW M2 ( 38872 42520 ) ( * 44040 ) - NEW M2 ( 38872 44040 ) ( * 44344 ) VIA23SQ_C W - NEW M1 ( 45408 40392 ) VIA12SQ_C ( * 42520 ) VIA23SQ_C W - NEW M3 ( 39176 42520 ) ( 45408 * ) - NEW M1 ( 36136 44192 ) VIA12SQ_C - NEW M2 ( 36136 44344 ) VIA23SQ_C W ( 38872 * ) - + USE SIGNAL ; - - RX_OUT_P[1] - ( PIN RX_OUT_P[1] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ Q ) - ( U0_UART_RX/U0_deserializer/U4 A2 ) - ( U0_UART_RX/U0_deserializer/U3 A4 ) - ( U0_UART_RX/U0_par_chk/U5 A1 ) - + ROUTED M4 ( 36744 43736 ) ( * 47542 ) - NEW M3 ( 36744 43736 ) VIA34SQ_C - NEW M3 ( 36288 43736 ) ( 36744 * ) - NEW M1 ( 33856 43736 ) VIA12SQ_C - NEW M2 ( 33856 43432 ) ( * 43736 ) - NEW M2 ( 33704 43432 ) ( 33856 * ) - NEW M1 ( 33704 42064 ) VIA12SQ_C ( * 43432 ) - NEW M1 ( 36288 43736 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 35528 39936 ) VIA12SQ_C ( * 43736 ) VIA23SQ_C W ( 36136 * ) - NEW M3 ( 36136 43736 ) ( 36288 * ) - NEW M3 ( 36136 43432 ) ( * 43736 ) - NEW M3 ( 33704 43432 ) ( 36136 * ) - NEW M2 ( 33704 43432 ) VIA23SQ_C W - + USE SIGNAL ; - - RX_OUT_P[0] - ( PIN RX_OUT_P[0] ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ Q ) - ( U0_UART_RX/U0_deserializer/U3 A2 ) - ( U0_UART_RX/U0_par_chk/U5 A2 ) - + ROUTED M4 ( 34616 42520 ) ( * 47542 ) - NEW M3 ( 34616 42520 ) VIA34SQ_C - NEW M3 ( 34312 42520 ) ( 34616 * ) - NEW M1 ( 33400 40392 ) VIA12SQ_C VIA23SQ_C W ( 34312 * ) - NEW M1 ( 33856 42520 ) VIA12SQ_C VIA23SQ_C W ( 34312 * ) - NEW M1 ( 35224 40610 ) VIA12SQ_C - NEW M2 ( 35224 40392 ) ( * 40610 ) - NEW M2 ( 35224 40392 ) VIA23SQ_C W - NEW M3 ( 34312 40392 ) ( 35224 * ) - NEW M2 ( 34312 40392 ) VIA23SQ_C W - NEW M2 ( 34312 40392 ) ( * 42520 ) VIA23SQ_C W - + USE SIGNAL ; - - RX_OUT_V - ( PIN RX_OUT_V ) - ( U0_UART_RX/U0_uart_fsm/U76 Y ) - + ROUTED M3 ( 45104 28840 ) ( 48454 * ) - NEW M2 ( 45104 28840 ) VIA23SQ_C W - NEW M2 ( 45104 28536 ) ( * 28840 ) - NEW M1 ( 45104 28536 ) VIA12SQ_C - + USE SIGNAL ; - - TX_IN_P[7] - ( PIN TX_IN_P[7] ) - ( U0_UART_TX/U0_parity_calc/U23 A3 ) - ( U0_UART_TX/U0_Serializer/U20 A3 ) - + ROUTED M3 ( 25496 5736 ) VIA34SQ_C ( * 11208 ) VIA34SQ_C - NEW M2 ( 25648 11208 ) VIA23SQ_C W - NEW M2 ( 25648 11208 ) ( * 14552 ) - NEW M2 ( 25648 14552 ) ( 25800 * ) VIA12SQ_C - NEW M1 ( 23976 4824 ) VIA12SQ_C ( * 5736 ) VIA23SQ_C W ( 25496 * ) - NEW M6 ( 29752 258 ) ( * 1784 ) VIA56SQ_C - NEW M5 ( 27016 1784 ) ( 29752 * ) - NEW M4 ( 27016 1784 ) VIA45SQ_C W - NEW M4 ( 27016 1784 ) ( * 5736 ) VIA34SQ_C - NEW M3 ( 25496 5736 ) ( 27016 * ) - + USE SIGNAL ; - - TX_IN_P[6] - ( PIN TX_IN_P[6] ) - ( U0_UART_TX/U0_parity_calc/U21 A3 ) - ( U0_UART_TX/U0_Serializer/U21 A1 ) - + ROUTED M2 ( 24432 7104 ) ( * 9232 ) - NEW M2 ( 24128 9232 ) ( 24432 * ) - NEW M2 ( 24128 9232 ) ( * 14856 ) VIA12SQ_C - NEW M1 ( 23704 7104 ) ( 24432 * ) VIA12SQ_C - NEW M6 ( 27320 258 ) ( * 568 ) VIA56SQ_C - NEW M5 ( 24280 568 ) ( 27320 * ) - NEW M4 ( 24280 568 ) VIA45SQ_C W - NEW M4 ( 24280 568 ) ( * 6344 ) VIA34SQ_C - NEW M2 ( 24432 6344 ) VIA23SQ_C W - NEW M2 ( 24432 6344 ) ( * 7104 ) - + USE SIGNAL ; - - TX_IN_P[5] - ( PIN TX_IN_P[5] ) - ( U0_UART_TX/U0_parity_calc/U19 A3 ) - ( U0_UART_TX/U0_Serializer/U22 A1 ) - + ROUTED M1 ( 22760 8928 ) VIA12SQ_C ( * 9384 ) - NEW M4 ( 27928 258 ) ( * 568 ) VIA34SQ_C - NEW M3 ( 22912 568 ) ( 27928 * ) - NEW M2 ( 22912 568 ) VIA23SQ_C W - NEW M2 ( 22912 568 ) ( * 9384 ) - NEW M2 ( 22760 9384 ) ( 22912 * ) - NEW M2 ( 22760 9384 ) ( * 11664 ) - NEW M2 ( 20632 11664 ) ( 22760 * ) - NEW M1 ( 20632 11664 ) VIA12SQ_C - NEW M1 ( 20632 11512 ) ( * 11664 ) - + USE SIGNAL ; - - TX_IN_P[4] - ( PIN TX_IN_P[4] ) - ( U0_UART_TX/U0_parity_calc/U17 A3 ) - ( U0_UART_TX/U0_Serializer/U23 A1 ) - + ROUTED M4 ( 25800 258 ) ( * 2696 ) VIA34SQ_C - NEW M3 ( 23824 2696 ) ( 25800 * ) - NEW M2 ( 23824 2696 ) VIA23SQ_C W - NEW M2 ( 23824 2696 ) ( * 8928 ) VIA12SQ_C - NEW M1 ( 22608 11208 ) VIA12SQ_C ( * 11512 ) VIA23SQ_C W ( 23824 * ) VIA23SQ_C W - NEW M2 ( 23824 8928 ) ( * 11512 ) - + USE SIGNAL ; - - TX_IN_P[3] - ( PIN TX_IN_P[3] ) - ( U0_UART_TX/U0_parity_calc/U15 A3 ) - ( U0_UART_TX/U0_Serializer/U24 A1 ) - + ROUTED M2 ( 30664 5736 ) VIA23SQ_C W - NEW M3 ( 28384 5736 ) ( 30664 * ) - NEW M2 ( 28384 5736 ) VIA23SQ_C W - NEW M2 ( 28384 5736 ) ( * 18200 ) VIA12SQ_C - NEW M6 ( 32184 258 ) ( * 4824 ) VIA56SQ_C - NEW M5 ( 30664 4824 ) ( 32184 * ) - NEW M4 ( 30664 4824 ) VIA45SQ_C W - NEW M3 ( 30664 4824 ) VIA34SQ_C - NEW M2 ( 30664 4824 ) VIA23SQ_C W - NEW M2 ( 30664 4824 ) ( * 5559 ) - NEW M1 ( 30664 5584 ) VIA12SQ_C - + USE SIGNAL ; - - TX_IN_P[2] - ( PIN TX_IN_P[2] ) - ( U0_UART_TX/U0_parity_calc/U13 A3 ) - ( U0_UART_TX/U0_Serializer/U25 A1 ) - + ROUTED M1 ( 31272 7104 ) VIA12SQ_C ( * 14856 ) VIA23SQ_C W - NEW M1 ( 26712 14856 ) VIA12SQ_C VIA23SQ_C W ( 31272 * ) - NEW M3 ( 37960 18200 ) ( 48454 * ) - NEW M3 ( 37960 18200 ) VIA34SQ_C W - NEW M4 ( 37960 14856 ) ( * 18200 ) - NEW M3 ( 37960 14856 ) VIA34SQ_C - NEW M3 ( 31272 14856 ) ( 37960 * ) - + USE SIGNAL ; - - TX_IN_P[1] - ( PIN TX_IN_P[1] ) - ( U0_UART_TX/U0_parity_calc/U11 A3 ) - ( U0_UART_TX/U0_Serializer/U26 A1 ) - + ROUTED M4 ( 30056 258 ) ( * 11512 ) VIA34SQ_C - NEW M1 ( 31880 8928 ) VIA12SQ_C ( * 11512 ) VIA23SQ_C W - NEW M3 ( 30056 11512 ) ( 31880 * ) - NEW M1 ( 28232 11512 ) VIA12SQ_C VIA23SQ_C W ( 30056 * ) - + USE SIGNAL ; - - TX_IN_P[0] - ( PIN TX_IN_P[0] ) - ( U0_UART_TX/U0_parity_calc/U9 A3 ) - ( U0_UART_TX/U0_Serializer/U19 A1 ) - + ROUTED M1 ( 25952 8928 ) ( 29720 * ) - NEW M1 ( 25952 8928 ) VIA12SQ_C - NEW M1 ( 25800 11512 ) VIA12SQ_C - NEW M2 ( 25800 8928 ) ( * 11512 ) - NEW M2 ( 25800 8928 ) ( 25952 * ) - NEW M4 ( 16680 258 ) ( * 1176 ) VIA34SQ_C ( 25952 * ) VIA23SQ_C W ( * 8928 ) - + USE SIGNAL ; - - TX_IN_V - ( PIN TX_IN_V ) - ( U0_UART_TX/U0_parity_calc/U10 A1 ) - ( U0_UART_TX/U0_Serializer/U29 A1 ) - ( U0_UART_TX/U0_fsm/U14 A1 ) - + ROUTED M4 ( 32792 258 ) ( * 3608 ) VIA34SQ_C ( 33552 * ) - NEW M1 ( 35832 3608 ) VIA12SQ_C W VIA23SQ_C W - NEW M1 ( 33552 3608 ) VIA12SQ_C W VIA23SQ_C W ( 35832 * ) - NEW M1 ( 39409 3760 ) VIA12SQ_C W - NEW M2 ( 39409 3608 ) ( * 3760 ) - NEW M2 ( 39409 3608 ) VIA23SQ_C W - NEW M3 ( 35832 3608 ) ( 39409 * ) - + USE SIGNAL ; - - TX_OUT_S - ( PIN TX_OUT_S ) - ( U0_UART_TX/U0_mux/OUT_reg Q ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ SI ) - + ROUTED M3 ( 45408 16072 ) ( 48454 * ) - NEW M2 ( 45408 16072 ) VIA23SQ_C W - NEW M2 ( 45408 16072 ) ( * 16984 ) - NEW M1 ( 41396 20024 ) VIA12SQ_C_1_2 - NEW M2 ( 41456 20024 ) ( * 20328 ) VIA23SQ_C W ( 45256 * ) VIA23SQ_C W - NEW M2 ( 45256 16984 ) ( * 20328 ) - NEW M2 ( 45256 16984 ) ( 45408 * ) VIA12SQ_C - + USE SIGNAL ; - - TX_OUT_V - ( PIN TX_OUT_V ) - ( U0_UART_TX/U0_fsm/busy_reg Q ) - ( U0_UART_TX/U0_parity_calc/U12 A ) - ( U0_UART_TX/U0_Serializer/U16 A ) - + ROUTED M4 ( 34920 258 ) ( * 4216 ) VIA34SQ_C - NEW M1 ( 37504 3912 ) VIA12SQ_C ( * 4216 ) VIA23SQ_C W - NEW M1 ( 34920 3912 ) VIA12SQ_C ( * 4216 ) VIA23SQ_C W ( 37504 * ) - NEW M1 ( 40392 5736 ) VIA12SQ_C - NEW M2 ( 40240 5736 ) ( 40392 * ) - NEW M2 ( 40240 4216 ) ( * 5736 ) - NEW M2 ( 40240 4216 ) VIA23SQ_C W - NEW M3 ( 37504 4216 ) ( 40240 * ) - + USE SIGNAL ; - - Prescale[5] - ( PIN Prescale[5] ) - ( U0_UART_RX/U0_deserializer/U34 A2 ) - ( U0_UART_RX/U0_data_sampling/U18 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U48 A2 ) - ( U0_UART_RX/U0_uart_fsm/U26 A2 ) - ( U0_UART_RX/U0_uart_fsm/U10 A1 ) - + ROUTED M2 ( 7408 22456 ) VIA23SQ_C W - NEW M2 ( 7408 22152 ) ( * 22456 ) - NEW M1 ( 7408 22152 ) VIA12SQ_C - NEW M1 ( 8320 8776 ) VIA12SQ_C ( * 10904 ) VIA23SQ_C W - NEW M3 ( 7256 10904 ) ( 8320 * ) - NEW M2 ( 7256 10904 ) VIA23SQ_C W - NEW M2 ( 7256 10904 ) ( * 12120 ) VIA12SQ_C - NEW M2 ( 7256 12120 ) ( * 12424 ) - NEW M1 ( 7560 27320 ) VIA12SQ_C - NEW M2 ( 7408 27320 ) ( 7560 * ) - NEW M2 ( 7408 22760 ) ( * 27320 ) - NEW M2 ( 7408 22760 ) VIA23SQ_C W - NEW M3 ( 7256 22760 ) ( 7408 * ) - NEW M3 ( 7256 22456 ) ( * 22760 ) - NEW M2 ( 7408 12120 ) ( * 22152 ) - NEW M2 ( 7256 12120 ) ( 7408 * ) - NEW M5 ( 258 21848 ) ( 7256 * ) VIA45SQ_C W ( * 22456 ) VIA34SQ_C - NEW M1 ( 6192 10752 ) VIA12SQ_C - NEW M2 ( 6192 10904 ) VIA23SQ_C W ( 7256 * ) - + USE SIGNAL ; - - Prescale[4] - ( PIN Prescale[4] ) - ( U0_UART_RX/U0_deserializer/U17 A ) - ( U0_UART_RX/U0_data_sampling/U10 A ) - ( U0_UART_RX/U0_edge_bit_counter/U39 A ) - ( U0_UART_RX/U0_uart_fsm/U12 A2 ) - ( U0_UART_RX/U0_uart_fsm/U11 A1 ) - ( U0_UART_RX/U0_uart_fsm/U6 A ) - + ROUTED M3 ( 258 14856 ) ( 3000 * ) VIA23SQ_C W - NEW M1 ( 5584 8928 ) VIA12SQ_C - NEW M2 ( 3152 18504 ) ( * 18808 ) VIA12SQ_C - NEW M2 ( 5584 8776 ) ( 5736 * ) - NEW M2 ( 5736 5432 ) ( * 8776 ) - NEW M1 ( 6344 20632 ) VIA12SQ_C - NEW M2 ( 6344 19720 ) ( * 20632 ) - NEW M2 ( 6344 19720 ) VIA23SQ_C W - NEW M3 ( 3304 19720 ) ( 6344 * ) - NEW M3 ( 3304 19416 ) ( * 19720 ) - NEW M2 ( 3304 19416 ) VIA23SQ_C W - NEW M2 ( 3304 18504 ) ( * 19416 ) - NEW M2 ( 3152 18504 ) ( 3304 * ) - NEW M1 ( 3304 8776 ) VIA12SQ_C VIA23SQ_C W - NEW M2 ( 3000 18504 ) ( 3152 * ) - NEW M2 ( 3000 14856 ) ( * 18504 ) - NEW M2 ( 5584 8776 ) VIA23SQ_C W - NEW M3 ( 3304 8776 ) ( 5584 * ) - NEW M1 ( 6040 3912 ) VIA12SQ_C ( * 5432 ) - NEW M2 ( 5736 5432 ) ( 6040 * ) - NEW M2 ( 3000 8776 ) ( * 14856 ) - NEW M2 ( 3000 8776 ) VIA23SQ_C W ( 3304 * ) - NEW M2 ( 5736 5128 ) ( * 5432 ) - NEW M2 ( 5128 5128 ) ( 5736 * ) - NEW M2 ( 5128 5128 ) ( * 5432 ) VIA12SQ_C - + USE SIGNAL ; - - Prescale[3] - ( PIN Prescale[3] ) - ( U0_UART_RX/U0_deserializer/U31 A1 ) - ( U0_UART_RX/U0_deserializer/U30 A2 ) - ( U0_UART_RX/U0_data_sampling/U15 A1 ) - ( U0_UART_RX/U0_data_sampling/U14 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U45 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U44 A2 ) - ( U0_UART_RX/U0_uart_fsm/U23 A1 ) - ( U0_UART_RX/U0_uart_fsm/U22 A2 ) - ( U0_UART_RX/U0_uart_fsm/U14 A2 ) - ( U0_UART_RX/U0_uart_fsm/U13 A1 ) - + ROUTED M1 ( 4368 23824 ) ( 4763 * ) - NEW M1 ( 4368 23672 ) ( * 23824 ) - NEW M1 ( 4368 23672 ) VIA12SQ_C - NEW M2 ( 3912 23672 ) ( 4368 * ) - NEW M2 ( 4064 7560 ) ( * 8928 ) - NEW M2 ( 4064 7560 ) ( 4216 * ) - NEW M1 ( 4216 7256 ) VIA12SQ_C ( * 7560 ) - NEW M2 ( 3760 22000 ) ( * 23368 ) - NEW M2 ( 3760 23368 ) ( 3912 * ) - NEW M2 ( 3912 23368 ) ( * 23672 ) - NEW M1 ( 3608 14071 ) VIA12BAR_C - NEW M1 ( 3912 28713 ) VIA12BAR_C - NEW M2 ( 3608 14071 ) ( * 14248 ) - NEW M2 ( 3456 14248 ) ( 3608 * ) - NEW M1 ( 5888 13792 ) VIA12SQ_C ( * 14248 ) VIA23SQ_C W - NEW M3 ( 3456 14248 ) ( 5888 * ) - NEW M2 ( 3456 14248 ) VIA23SQ_C W - NEW M2 ( 3912 23672 ) ( * 26408 ) - NEW M1 ( 4064 30512 ) ( 4277 * ) - NEW M1 ( 4064 30512 ) VIA12SQ_C - NEW M2 ( 4064 30360 ) ( * 30512 ) - NEW M2 ( 3912 30360 ) ( 4064 * ) - NEW M2 ( 3912 28713 ) ( * 30360 ) - NEW M3 ( 4216 7560 ) ( 7256 * ) - NEW M2 ( 4216 7560 ) VIA23SQ_C W - NEW M2 ( 3608 9232 ) ( * 14071 ) - NEW M2 ( 3608 9232 ) ( 4064 * ) - NEW M2 ( 4064 8928 ) ( * 9232 ) - NEW M2 ( 3456 14248 ) ( * 17440 ) - NEW M2 ( 3456 17440 ) ( 3912 * ) - NEW M2 ( 3912 17440 ) ( * 21696 ) - NEW M2 ( 3760 21696 ) ( 3912 * ) - NEW M2 ( 3760 21696 ) ( * 22000 ) - NEW M3 ( 7256 7560 ) ( 8016 * ) VIA23SQ_C W - NEW M2 ( 8016 7104 ) ( * 7560 ) - NEW M1 ( 8016 7104 ) VIA12SQ_C - NEW M1 ( 8016 7104 ) ( 8715 * ) - NEW M3 ( 258 26408 ) ( 3912 * ) VIA23SQ_C - NEW M1 ( 7256 7433 ) VIA12BAR_C - NEW M2 ( 7256 7560 ) VIA23SQ_C W - NEW M1 ( 4064 8928 ) VIA12SQ_C - NEW M2 ( 3912 26408 ) ( * 28713 ) - NEW M1 ( 3608 22025 ) VIA12BAR W - NEW M2 ( 3608 22000 ) ( 3760 * ) - + USE SIGNAL ; - - Prescale[2] - ( PIN Prescale[2] ) - ( U0_UART_RX/U0_deserializer/U29 A1 ) - ( U0_UART_RX/U0_deserializer/U28 A2 ) - ( U0_UART_RX/U0_data_sampling/U13 A1 ) - ( U0_UART_RX/U0_data_sampling/U12 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U43 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U42 A2 ) - ( U0_UART_RX/U0_uart_fsm/U21 A1 ) - ( U0_UART_RX/U0_uart_fsm/U20 A2 ) - ( U0_UART_RX/U0_uart_fsm/U16 A2 ) - ( U0_UART_RX/U0_uart_fsm/U15 A1 ) - + ROUTED M1 ( 3608 24001 ) VIA12BAR_C - NEW M1 ( 4672 17136 ) VIA12SQ_C - NEW M1 ( 7560 20632 ) VIA12SQ_C - NEW M2 ( 7560 20024 ) ( * 20632 ) - NEW M2 ( 7560 20024 ) VIA23SQ_C W - NEW M3 ( 4520 20024 ) ( 7560 * ) - NEW M2 ( 3456 24128 ) ( 3607 * ) - NEW M2 ( 3456 21696 ) ( * 24128 ) - NEW M2 ( 3456 21696 ) ( 3608 * ) - NEW M2 ( 3608 21544 ) ( * 21696 ) - NEW M1 ( 4976 25648 ) ( 5493 * ) - NEW M1 ( 4976 25648 ) VIA12SQ_C - NEW M1 ( 7256 15439 ) VIA12BAR_C ( * 15768 ) VIA23SQ_C W - NEW M1 ( 4976 27168 ) VIA12SQ_C - NEW M2 ( 4976 25648 ) ( * 27168 ) - NEW M1 ( 3760 15439 ) VIA12BAR_C ( * 17288 ) VIA23SQ_C W ( 4520 * ) VIA23SQ_C W - NEW M2 ( 3608 21544 ) ( 3760 * ) - NEW M2 ( 3760 20024 ) ( * 21544 ) - NEW M2 ( 3760 20024 ) VIA23SQ_C W ( 4520 * ) - NEW M2 ( 4672 17136 ) ( * 17288 ) - NEW M2 ( 4520 17288 ) ( 4672 * ) - NEW M2 ( 4672 16072 ) ( * 17136 ) - NEW M2 ( 4672 16072 ) VIA23SQ_C W ( 5736 * ) - NEW M3 ( 5736 15768 ) ( * 16072 ) - NEW M2 ( 3608 24128 ) ( * 25192 ) VIA23SQ_C W ( 4216 * ) - NEW M2 ( 4976 25192 ) ( * 25648 ) - NEW M2 ( 4976 25192 ) VIA23SQ_C W - NEW M3 ( 4216 25192 ) ( 4976 * ) - NEW M3 ( 5736 15768 ) ( 7256 * ) - NEW M2 ( 4520 17288 ) ( * 20024 ) VIA23SQ_C W - NEW M3 ( 258 21544 ) ( 3608 * ) VIA23SQ_C W - NEW M1 ( 4216 32336 ) VIA12SQ_C - NEW M2 ( 4216 25192 ) ( * 32336 ) - NEW M2 ( 4216 25192 ) VIA23SQ_C W - NEW M1 ( 5736 15616 ) VIA12SQ_C - NEW M2 ( 5736 15768 ) VIA23SQ_C W - NEW M1 ( 8320 15616 ) VIA12SQ_C - NEW M2 ( 8320 15768 ) VIA23SQ_C W - NEW M3 ( 7256 15768 ) ( 8320 * ) - + USE SIGNAL ; - - Prescale[1] - ( PIN Prescale[1] ) - ( U0_UART_RX/U0_deserializer/U19 A1 ) - ( U0_UART_RX/U0_deserializer/U18 A1 ) - ( U0_UART_RX/U0_data_sampling/U54 A2 ) - ( U0_UART_RX/U0_data_sampling/U34 A2 ) - ( U0_UART_RX/U0_data_sampling/U13 A2 ) - ( U0_UART_RX/U0_data_sampling/U12 A2 ) - ( U0_UART_RX/U0_data_sampling/U11 A ) - ( U0_UART_RX/U0_edge_bit_counter/U41 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U40 A1 ) - ( U0_UART_RX/U0_uart_fsm/U19 A1 ) - ( U0_UART_RX/U0_uart_fsm/U18 A1 ) - ( U0_UART_RX/U0_uart_fsm/U16 A1 ) - ( U0_UART_RX/U0_uart_fsm/U15 A2 ) - ( U0_UART_RX/U0_uart_fsm/U9 A ) - + ROUTED M1 ( 11056 27320 ) VIA12SQ_C - NEW M1 ( 4368 17313 ) VIA12BAR_C - NEW M2 ( 4368 16680 ) ( * 17313 ) - NEW M2 ( 4368 16680 ) VIA23SQ_C W ( 5888 * ) - NEW M3 ( 258 28536 ) ( 4368 * ) VIA23SQ_C W ( * 32488 ) - NEW M2 ( 4064 32488 ) ( 4368 * ) - NEW M1 ( 6952 25648 ) ( 7469 * ) - NEW M1 ( 6952 25648 ) VIA12SQ_C ( * 25800 ) - NEW M1 ( 6952 17136 ) VIA12SQ_C - NEW M1 ( 10296 18960 ) ( 10813 * ) - NEW M1 ( 10296 18960 ) VIA12SQ_C ( * 19416 ) VIA23SQ_C W - NEW M3 ( 9232 19416 ) ( 10296 * ) - NEW M2 ( 9232 19416 ) VIA23SQ_C W - NEW M2 ( 9232 16984 ) ( * 19416 ) - NEW M2 ( 9232 16984 ) VIA23SQ_C W - NEW M3 ( 8624 16984 ) ( 9232 * ) - NEW M2 ( 3304 32488 ) ( 4064 * ) - NEW M2 ( 3304 32488 ) ( * 34008 ) VIA12SQ_C - NEW M2 ( 6800 20632 ) VIA23SQ_C W ( 7864 * ) VIA23SQ_C W - NEW M1 ( 7864 20784 ) VIA12SQ_C - NEW M1 ( 3852 32184 ) ( 4064 * ) VIA12SQ_C ( * 32488 ) - NEW M1 ( 15616 30664 ) VIA12SQ_C ( * 31272 ) VIA23SQ_C W - NEW M3 ( 13792 31272 ) ( 15616 * ) - NEW M1 ( 13792 34008 ) VIA12SQ_C - NEW M2 ( 13792 31272 ) ( * 34008 ) - NEW M2 ( 13792 31272 ) VIA23SQ_C W - NEW M1 ( 5888 17136 ) VIA12SQ_C - NEW M2 ( 5888 16680 ) ( * 17136 ) - NEW M2 ( 5888 16680 ) VIA23SQ_C W - NEW M1 ( 8624 17136 ) ( 9293 * ) - NEW M1 ( 8624 17136 ) VIA12SQ_C W - NEW M2 ( 8624 16984 ) ( * 17136 ) - NEW M2 ( 8624 16984 ) VIA23SQ_C W - NEW M2 ( 6952 25800 ) ( * 26712 ) VIA23SQ_C W - NEW M2 ( 6800 25800 ) ( 6952 * ) - NEW M2 ( 6800 23824 ) ( * 25800 ) - NEW M2 ( 11056 26712 ) ( * 27320 ) - NEW M2 ( 11056 26712 ) VIA23SQ_C W - NEW M3 ( 6952 26712 ) ( 11056 * ) - NEW M3 ( 4368 28536 ) ( 5128 * ) VIA23SQ_C W - NEW M2 ( 5128 27345 ) ( * 28536 ) - NEW M2 ( 5128 26712 ) ( * 27345 ) - NEW M2 ( 5128 26712 ) VIA23SQ_C W ( 6952 * ) - NEW M2 ( 6800 16984 ) ( * 20632 ) - NEW M2 ( 6800 16984 ) ( 6952 * ) - NEW M1 ( 6800 23824 ) VIA12SQ_C - NEW M3 ( 5888 16680 ) ( 6952 * ) - NEW M3 ( 6952 16680 ) ( * 16984 ) - NEW M3 ( 6952 16984 ) ( 8624 * ) - NEW M2 ( 6952 16984 ) VIA23SQ_C W - NEW M2 ( 6800 20632 ) ( * 23824 ) - NEW M1 ( 5128 27345 ) VIA12BAR_C - NEW M2 ( 11056 27320 ) ( * 31272 ) VIA23SQ_C W ( 13792 * ) - + USE SIGNAL ; - - Prescale[0] - ( PIN Prescale[0] ) - ( U0_UART_RX/U0_deserializer/U42 A2 ) - ( U0_UART_RX/U0_deserializer/U40 A1 ) - ( U0_UART_RX/U0_deserializer/U19 A2 ) - ( U0_UART_RX/U0_deserializer/U18 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U57 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U55 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U41 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U40 A2 ) - ( U0_UART_RX/U0_uart_fsm/U42 A2 ) - ( U0_UART_RX/U0_uart_fsm/U19 A2 ) - ( U0_UART_RX/U0_uart_fsm/U18 A2 ) - ( U0_UART_RX/U0_uart_fsm/U17 A ) - + ROUTED M3 ( 5584 17288 ) ( 7104 * ) - NEW M2 ( 5584 17288 ) VIA23SQ_C W - NEW M1 ( 13336 20632 ) VIA12SQ_C - NEW M2 ( 13336 18808 ) ( * 20632 ) - NEW M2 ( 13336 18808 ) VIA23SQ_C W - NEW M2 ( 7104 23976 ) VIA23SQ_C W - NEW M3 ( 6344 23976 ) ( 7104 * ) - NEW M2 ( 6344 23976 ) VIA23SQ_C W - NEW M1 ( 6344 24001 ) VIA12BAR_C - NEW M1 ( 15464 18808 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 16528 22152 ) VIA12SQ_C - NEW M2 ( 16376 22152 ) ( 16528 * ) - NEW M2 ( 16376 18808 ) ( * 22152 ) - NEW M2 ( 16376 18808 ) VIA23SQ_C W - NEW M2 ( 7104 17288 ) ( 7256 * ) - NEW M1 ( 7256 17313 ) VIA12BAR_C - NEW M2 ( 7104 17288 ) ( * 23976 ) - NEW M1 ( 17896 18833 ) VIA12BAR_C - NEW M2 ( 17896 18808 ) VIA23SQ_C W - NEW M3 ( 16376 18808 ) ( 17896 * ) - NEW M1 ( 9080 17288 ) VIA12SQ_C - NEW M1 ( 13852 18808 ) VIA12SQ_C_1_2 - NEW M2 ( 13792 18808 ) VIA23SQ_C W - NEW M1 ( 15920 18808 ) VIA12SQ_C VIA23SQ_C W ( 16376 * ) - NEW M2 ( 7104 23976 ) ( * 25496 ) VIA12SQ_C - NEW M3 ( 13336 18808 ) ( 13792 * ) - NEW M2 ( 9080 17288 ) ( * 18200 ) VIA23SQ_C W ( 10600 * ) VIA23SQ_C W ( * 18808 ) VIA23SQ_C W ( 13336 * ) - NEW M3 ( 7104 17288 ) ( 9080 * ) VIA23SQ_C W - NEW M3 ( 13792 18808 ) ( 15464 * ) - NEW M3 ( 15464 18808 ) ( 15920 * ) - NEW M3 ( 258 18808 ) ( 5584 * ) VIA23SQ_C W - NEW M2 ( 5584 17313 ) ( * 18808 ) - NEW M2 ( 7104 17288 ) VIA23SQ_C W - NEW M1 ( 10600 18808 ) VIA12SQ_C - NEW M1 ( 5584 17313 ) VIA12BAR_C - + USE SIGNAL ; - - parity_enable - ( PIN parity_enable ) - ( U0_UART_RX/U0_uart_fsm/U53 A ) - ( U0_UART_TX/U0_parity_calc/U14 A ) - ( U0_UART_TX/U0_parity_calc/U2 A3 ) - ( U0_UART_TX/U0_fsm/U10 A1 ) - + ROUTED M4 ( 48600 19416 ) VIA45SQ_C W - NEW M4 ( 48600 18808 ) ( * 19416 ) - NEW M3 ( 48600 18808 ) VIA34SQ_C - NEW M3 ( 40088 18808 ) ( 48600 * ) - NEW M3 ( 39176 18808 ) ( 40088 * ) - NEW M1 ( 37656 18200 ) VIA12SQ_C ( * 18808 ) VIA23SQ_C W - NEW M1 ( 40088 18808 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 37656 18808 ) ( 39176 * ) - NEW M1 ( 39176 15464 ) VIA12SQ_C ( * 18808 ) VIA23SQ_C W - NEW M1 ( 30816 18808 ) VIA12SQ_C VIA23SQ_C W ( 37656 * ) - + USE SIGNAL ; - - parity_type - ( PIN parity_type ) - ( U0_UART_RX/U0_par_chk/U8 A2 ) - ( U0_UART_TX/U0_parity_calc/U3 A1 ) - + ROUTED M1 ( 37656 28840 ) VIA12SQ_C - NEW M2 ( 37656 21848 ) ( * 28840 ) - NEW M3 ( 37656 21848 ) ( 48454 * ) - NEW M2 ( 37656 21848 ) VIA23SQ_C W - NEW M2 ( 37656 19416 ) ( * 21848 ) - NEW M2 ( 37656 19416 ) VIA23SQ_C W - NEW M3 ( 34616 19416 ) ( 37656 * ) - NEW M2 ( 34616 19416 ) VIA23SQ_C W - NEW M1 ( 34616 19568 ) VIA12SQ_C - + USE SIGNAL ; - - parity_error - ( PIN parity_error ) - ( U0_UART_RX/U0_par_chk/par_err_reg Q ) - ( U0_UART_RX/U0_par_chk/U2 A1 ) - ( U0_UART_RX/U0_uart_fsm/U76 A3 ) - + ROUTED M3 ( 45408 30968 ) ( 48454 * ) - NEW M2 ( 45408 30968 ) VIA23SQ_C W - NEW M2 ( 45408 30360 ) ( * 30968 ) - NEW M1 ( 44344 28688 ) VIA12SQ_C ( * 29448 ) VIA23SQ_C W - NEW M1 ( 45408 30360 ) VIA12SQ_C - NEW M1 ( 40315 28840 ) ( 40544 * ) VIA12SQ_C ( * 29448 ) VIA23SQ_C W ( 44344 * ) - NEW M3 ( 44344 29448 ) ( * 29752 ) - NEW M3 ( 44344 29752 ) ( 45408 * ) VIA23SQ_C W ( * 30360 ) - + USE SIGNAL ; - - framing_error - ( PIN framing_error ) - ( U0_UART_RX/U0_stp_chk/stp_err_reg Q ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ SI ) - ( U0_UART_RX/U0_uart_fsm/U76 A2 ) - + ROUTED M3 ( 45408 26712 ) ( 48454 * ) - NEW M3 ( 45408 26712 ) ( * 27016 ) - NEW M3 ( 45104 27016 ) ( 45408 * ) - NEW M1 ( 44040 28536 ) VIA12SQ_C - NEW M2 ( 44040 27928 ) ( * 28536 ) - NEW M1 ( 45104 27016 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 44040 27016 ) ( 45104 * ) - NEW M2 ( 44040 27016 ) VIA23SQ_C W - NEW M2 ( 44040 27016 ) ( * 27928 ) - NEW M1 ( 34860 26712 ) VIA12SQ_C_1_2 - NEW M2 ( 34920 26712 ) ( * 27928 ) VIA23SQ_C W ( 44040 * ) VIA23SQ_C W - + USE SIGNAL ; - - SI - ( PIN SI ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ SI ) - + ROUTED M4 ( 13640 44344 ) ( * 47542 ) - NEW M3 ( 13640 44344 ) VIA34SQ_C - NEW M3 ( 13640 44344 ) ( 17896 * ) VIA23SQ_C W - NEW M2 ( 17896 43432 ) ( * 44344 ) - NEW M1 ( 17836 43432 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - SE - ( PIN SE ) - ( HFSBUF_156_0 A ) - ( U0_UART_RX/U0_stp_chk/stp_err_reg SE ) - ( U0_UART_RX/U0_par_chk/par_err_reg SE ) - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ SE ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ SE ) - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg SE ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ SE ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ SE ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ SE ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ SE ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ SE ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ SE ) - + ROUTED M4 ( 24584 44040 ) ( * 47542 ) - NEW M3 ( 24584 44040 ) VIA34SQ_C - NEW M1 ( 23216 42216 ) VIA12SQ_C - NEW M1 ( 22456 32032 ) VIA12SQ_C - NEW M1 ( 27928 28780 ) VIA12SQ_C ( * 34135 ) - NEW M1 ( 16832 30816 ) VIA12SQ_C - NEW M1 ( 17136 44100 ) VIA12SQ_C - NEW M2 ( 17136 40696 ) ( * 44100 ) - NEW M2 ( 16832 40696 ) ( 17136 * ) - NEW M1 ( 23216 40848 ) VIA12SQ_C ( * 42216 ) - NEW M3 ( 24584 44040 ) ( 28688 * ) VIA23SQ_C W - NEW M1 ( 34160 27472 ) VIA12SQ_C - NEW M2 ( 34160 27624 ) VIA23SQ_C W ( 40392 * ) - NEW M2 ( 16832 34312 ) ( * 37504 ) - NEW M1 ( 22456 28780 ) VIA12SQ_C ( * 32032 ) - NEW M1 ( 22608 35376 ) VIA12SQ_C - NEW M2 ( 22608 34312 ) ( * 35376 ) - NEW M1 ( 23672 44192 ) VIA12SQ_C - NEW M3 ( 35832 37352 ) ( 36896 * ) - NEW M2 ( 35832 37352 ) VIA23SQ_C W - NEW M1 ( 40544 32032 ) VIA12SQ_C - NEW M1 ( 37048 35468 ) VIA12SQ_C - NEW M2 ( 36896 35468 ) ( 37048 * ) - NEW M2 ( 36896 35468 ) ( * 37352 ) VIA23SQ_C W - NEW M2 ( 35832 37504 ) ( * 38568 ) VIA23SQ_C W - NEW M3 ( 30816 38568 ) ( 35832 * ) - NEW M2 ( 30816 38568 ) VIA23SQ_C W - NEW M1 ( 40696 38720 ) VIA12SQ_C - NEW M1 ( 40696 44100 ) VIA12SQ_C - NEW M2 ( 40696 40848 ) ( * 44100 ) - NEW M1 ( 40696 40848 ) VIA12SQ_C - NEW M1 ( 29144 44192 ) VIA12SQ_C - NEW M2 ( 29144 44040 ) ( * 44192 ) - NEW M2 ( 28688 44040 ) ( 29144 * ) - NEW M1 ( 28688 40848 ) VIA12SQ_C - NEW M1 ( 28840 37504 ) VIA12SQ_C ( * 37656 ) - NEW M2 ( 28688 37656 ) ( 28840 * ) - NEW M1 ( 40696 30816 ) VIA12SQ_C - NEW M2 ( 27928 37656 ) ( 28688 * ) - NEW M2 ( 27928 34312 ) ( * 37656 ) - NEW M2 ( 16832 37504 ) ( * 40696 ) - NEW M2 ( 23216 42216 ) ( * 44040 ) - NEW M2 ( 23216 44040 ) ( 23672 * ) - NEW M1 ( 27928 34160 ) VIA12SQ_C - NEW M2 ( 16832 30816 ) ( * 34312 ) - NEW M3 ( 23672 44040 ) ( 24584 * ) - NEW M2 ( 23672 44040 ) VIA23SQ_C W - NEW M3 ( 16832 34312 ) ( 17288 * ) - NEW M2 ( 16832 34312 ) VIA23SQ_C W - NEW M3 ( 17288 34312 ) ( 22608 * ) - NEW M2 ( 22456 32032 ) ( * 34312 ) - NEW M2 ( 22456 34312 ) ( 22608 * ) - NEW M3 ( 36896 37352 ) ( 40392 * ) VIA23SQ_C W - NEW M2 ( 27928 34312 ) VIA23SQ_C W - NEW M3 ( 22608 34312 ) ( 27928 * ) - NEW M2 ( 30816 38720 ) ( * 39176 ) VIA23SQ_C W - NEW M3 ( 28688 39176 ) ( 30816 * ) - NEW M2 ( 28688 39176 ) VIA23SQ_C W - NEW M1 ( 30816 38720 ) VIA12SQ_C - NEW M2 ( 40544 31576 ) ( * 32032 ) - NEW M2 ( 40544 31576 ) ( 40696 * ) - NEW M2 ( 40696 30968 ) ( * 31576 ) - NEW M2 ( 40544 32032 ) ( * 36440 ) - NEW M2 ( 40392 36440 ) ( 40544 * ) - NEW M2 ( 40392 36440 ) ( * 37352 ) - NEW M1 ( 35832 37504 ) VIA12SQ_C - NEW M2 ( 28688 39176 ) ( * 40848 ) - NEW M1 ( 15768 27472 ) VIA12SQ_C ( * 27928 ) VIA23SQ_C W ( 16832 * ) VIA23SQ_C W ( * 30816 ) - NEW M2 ( 40696 37352 ) ( * 38720 ) - NEW M2 ( 40392 37352 ) ( 40696 * ) - NEW M2 ( 28688 40848 ) ( * 44040 ) - NEW M1 ( 16224 40756 ) VIA12SQ_C - NEW M2 ( 16224 40696 ) VIA23SQ_C W ( 16832 * ) VIA23SQ_C W - NEW M2 ( 28688 37656 ) ( * 39176 ) - NEW M2 ( 22608 34312 ) VIA23SQ_C W - NEW M2 ( 40696 30968 ) VIA23SQ_C W VIA34SQ_C - NEW M4 ( 40696 27624 ) ( * 30968 ) - NEW M3 ( 40696 27624 ) VIA34SQ_C - NEW M3 ( 40392 27624 ) ( 40696 * ) - NEW M1 ( 16832 37504 ) VIA12SQ_C - NEW M1 ( 17288 34160 ) VIA12SQ_C - NEW M2 ( 17288 34312 ) VIA23SQ_C W - NEW M2 ( 40696 38720 ) ( * 40848 ) - NEW M1 ( 40392 27472 ) VIA12SQ_C - NEW M2 ( 40392 27624 ) VIA23SQ_C W - + USE SIGNAL ; - - scan_clk - ( PIN scan_clk ) - ( U1_mux2X1/U1 A2 ) - ( U0_mux2X1/U1 A2 ) - + NONDEFAULTRULE cts_w2_s2_vlg - + ROUTED M1 ( 30968 35680 ) VIA12SQ_C - NEW M2 TAPER ( 30588 35680 ) ( 30968 * ) - NEW M2 ( 30360 35680 ) ( 30588 * ) - NEW M2 ( 30360 35680 ) VIA23LG_C W VIA34LG_C - NEW M4 ( 30360 15464 ) ( * 35680 ) - NEW M4 TAPER ( 18808 258 ) ( * 611 ) - NEW M4 ( 18808 611 ) ( * 13944 ) VIA45LG_C ( 30360 * ) VIA45LG_C ( * 15464 ) VIA34SQ_C VIA23SQ_C W - NEW M1 ( 30360 15616 ) VIA12SQ_C - + USE CLOCK ; - - scan_rst - ( PIN scan_rst ) - ( U2_mux2X1/U1 A2 ) - + ROUTED M4 ( 23064 258 ) ( * 3608 ) VIA34SQ_C - NEW M2 ( 23216 3608 ) VIA23SQ_C W - NEW M1 ( 23216 3608 ) VIA12SQ_C - + USE SIGNAL ; - - test_mode - ( PIN test_mode ) - ( U2_mux2X1/U1 S0 ) - ( U1_mux2X1/U1 S0 ) - ( U0_mux2X1/U1 S0 ) - + ROUTED M6 ( 24888 258 ) ( * 3912 ) VIA56SQ_C VIA45SQ_C W VIA34SQ_C - NEW M2 ( 30056 14856 ) ( * 35680 ) VIA12SQ_C - NEW M1 ( 22760 3912 ) VIA12SQ_C VIA23SQ_C W ( 24888 * ) - NEW M3 ( 24888 3912 ) ( 30360 * ) VIA23SQ_C W ( * 14856 ) - NEW M2 ( 30056 14856 ) ( 30360 * ) - NEW M2 ( 29904 14856 ) ( 30056 * ) - NEW M2 ( 29904 14856 ) ( * 15464 ) VIA12SQ_C - + USE SIGNAL ; - - UART_RX_SCAN_CLK - ( U0_mux2X1/U1 Y ) - ( U0_UART_RX/U0_stp_chk/stp_err_reg CLK ) - ( U0_UART_RX/U0_par_chk/par_err_reg CLK ) - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ CLK ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ CLK ) - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg CLK ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ CLK ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ CLK ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ CLK ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ CLK ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ CLK ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ CLK ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ CLK ) - + NONDEFAULTRULE cts_w1_s2 - + ROUTED M1 ( 31576 35528 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 41912 40088 ) VIA34SQ_C - NEW M2 ( 42064 40088 ) VIA23SQ_C W - NEW M1 ( 42064 40088 ) VIA12SQ_C - NEW M3 ( 24888 29448 ) ( 29296 * ) - NEW M3 ( 23672 29448 ) ( 24888 * ) - NEW M2 ( 23672 29448 ) VIA23SQ_C W - NEW M1 ( 23672 29600 ) VIA12SQ_C - NEW M1 ( 25040 43280 ) VIA12SQ_C - NEW M2 ( 25040 43128 ) VIA23SQ_C W - NEW M3 ( 25192 43128 ) VIA34SQ_C - NEW M4 ( 25192 40088 ) ( * 43128 ) - NEW M3 ( 25192 40088 ) VIA34SQ_C - NEW M3 ( 41912 35528 ) VIA34SQ_C - NEW M3 ( 39024 35528 ) ( 41912 * ) - NEW M1 ( 18200 29904 ) VIA12SQ_C - NEW M2 ( 18200 30056 ) VIA23SQ_C W VIA34SQ_C - NEW M1 ( 18200 36592 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C ( * 36744 ) - NEW M1 ( 23672 32944 ) VIA12SQ_C VIA23SQ_C W ( 23976 * ) VIA34SQ_C ( * 35832 ) VIA34SQ_C - NEW M3 ( 23796 35832 ) ( 23976 * ) - NEW M3 ( 23672 35832 ) ( 23796 * ) - NEW M3 ( 31576 36440 ) VIA34SQ_C ( * 39480 ) VIA34SQ_C - NEW M1 ( 24888 23216 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 31576 39480 ) ( 32184 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 23976 36288 ) VIA12SQ_C - NEW M2 ( 23976 35224 ) ( * 36288 ) - NEW M1 ( 24432 39936 ) VIA12SQ_C - NEW M2 ( 24432 40088 ) VIA23SQ_C W ( 25192 * ) - NEW M1 ( 30056 39936 ) VIA12SQ_C - NEW M2 ( 30056 40088 ) VIA23SQ_C W - NEW M4 ( 18200 39784 ) ( * 40212 ) - NEW M4 ( 18200 40212 ) ( * 43128 ) VIA34SQ_C ( 18504 * ) VIA23SQ_C W - NEW M1 ( 18504 43280 ) VIA12SQ_C - NEW M1 ( 41912 32944 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C - NEW M3 ( 41912 39480 ) VIA34SQ_C - NEW M2 ( 42064 39480 ) VIA23SQ_C W - NEW M1 ( 42064 39480 ) VIA12SQ_C - NEW M4 ( 41912 40088 ) ( * 43128 ) VIA34SQ_C - NEW M2 ( 42064 43128 ) VIA23SQ_C W - NEW M1 ( 42064 43280 ) VIA12SQ_C - NEW M3 ( 37048 35528 ) VIA34SQ_C ( * 36440 ) VIA34SQ_C - NEW M2 ( 37200 36440 ) VIA23SQ_C W - NEW M1 ( 37200 36592 ) VIA12SQ_C - NEW M3 ( 30208 36440 ) ( 31576 * ) - NEW M2 ( 30208 36440 ) VIA23SQ_C W - NEW M1 ( 30208 36592 ) VIA12SQ_C - NEW M3 ( 30056 40088 ) VIA34SQ_C ( 30360 * ) - NEW M4 ( 30360 40088 ) ( * 43128 ) VIA34SQ_C - NEW M2 ( 30512 43128 ) VIA23SQ_C W - NEW M1 ( 30512 43280 ) VIA12SQ_C - NEW M3 ( 29144 35224 ) VIA34SQ_C - NEW M4 ( 29144 34616 ) ( * 35224 ) - NEW M3 ( 29144 34616 ) VIA34SQ_C - NEW M2 ( 29296 34616 ) VIA23SQ_C W - NEW M2 ( 29296 33248 ) ( * 34616 ) - NEW M1 ( 29296 33248 ) VIA12SQ_C - NEW M1 ( 35680 26560 ) VIA12SQ_C - NEW M2 ( 35680 26712 ) VIA23SQ_C W - NEW M3 ( 32460 26712 ) ( 35680 * ) - NEW M3 ( 31576 26712 ) ( 32460 * ) - NEW M3 ( 31576 26712 ) VIA34SQ_C ( * 29448 ) - NEW M3 ( 41912 30056 ) VIA34SQ_C - NEW M2 ( 42064 30056 ) VIA23SQ_C W - NEW M1 ( 42064 30056 ) VIA12SQ_C - NEW M4 ( 41912 32944 ) ( * 35528 ) - NEW M3 ( 24888 23216 ) ( * 23368 ) VIA34SQ_C ( * 29448 ) VIA34SQ_C - NEW M4 ( 41912 35528 ) ( * 39480 ) - NEW M4 ( 41912 30056 ) ( * 32944 ) - NEW M3 ( 37048 35528 ) ( 39024 * ) - NEW M3 ( 31576 35528 ) ( 37048 * ) - NEW M3 ( 29144 35224 ) ( 31576 * ) - NEW M3 ( 31576 35224 ) ( * 35528 ) - NEW M1 ( 17288 26560 ) VIA12SQ_C - NEW M2 ( 17288 26712 ) VIA23SQ_C W ( 18200 * ) VIA34SQ_C ( * 29020 ) - NEW M4 ( 18200 29020 ) ( * 30056 ) - NEW M4 ( 41912 39480 ) ( * 40088 ) - NEW M4 ( 18504 33400 ) ( * 35832 ) - NEW M4 ( 18200 33400 ) ( 18504 * ) - NEW M4 ( 18200 30056 ) ( * 33400 ) - NEW M4 ( 18504 35832 ) ( * 36744 ) - NEW M4 ( 18200 36744 ) ( 18504 * ) - NEW M3 ( 23976 35224 ) ( 29144 * ) - NEW M2 ( 23976 35224 ) VIA23SQ_C W - NEW M3 ( 29296 29448 ) ( 31576 * ) VIA34SQ_C - NEW M3 ( 31576 35528 ) ( * 36440 ) - NEW M3 ( 18504 35832 ) VIA34SQ_C - NEW M3 ( 18504 35832 ) ( 23672 * ) - NEW M3 ( 31576 39480 ) ( * 40088 ) - NEW M3 ( 30056 40088 ) ( 31576 * ) - NEW M2 ( 23672 35224 ) ( 23976 * ) - NEW M2 ( 23672 35224 ) ( * 35832 ) VIA23SQ_C W - NEW M1 ( 41760 26560 ) VIA12SQ_C - NEW M2 ( 41760 26712 ) VIA23SQ_C W - NEW M3 ( 41912 26712 ) VIA34SQ_C ( * 29780 ) - NEW M4 ( 41912 29780 ) ( * 30056 ) - NEW M4 ( 31576 29448 ) ( * 35528 ) VIA34SQ_C - NEW M4 ( 18200 36744 ) ( * 39784 ) - NEW M3 ( 25192 40088 ) ( 30056 * ) - NEW M3 ( 24888 22760 ) ( * 23216 ) - NEW M3 ( 24280 22760 ) ( 24888 * ) - NEW M2 ( 24280 22760 ) VIA23SQ_C W - NEW M1 ( 24280 22912 ) VIA12SQ_C - NEW M1 ( 18656 33400 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 18504 33400 ) VIA34SQ_C - NEW M2 ( 29296 29448 ) VIA23SQ_C W - NEW M1 ( 29296 29600 ) VIA12SQ_C - NEW M3 ( 18200 39784 ) VIA34SQ_C - NEW M3 ( 17592 39784 ) ( 18200 * ) - NEW M2 ( 17592 39784 ) VIA23SQ_C W - NEW M1 ( 17592 39936 ) VIA12SQ_C - NEW M2 ( 39024 35528 ) VIA23SQ_C W - NEW M2 ( 39024 35528 ) ( * 36136 ) VIA23SQ_C W - NEW M3 ( 38416 36136 ) ( 39024 * ) - NEW M2 ( 38416 36136 ) VIA23SQ_C W - NEW M1 ( 38416 36288 ) VIA12SQ_C - + USE CLOCK ; - - UART_TX_SCAN_CLK - ( U1_mux2X1/U1 Y ) - ( U0_UART_TX/U0_parity_calc/parity_reg CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ CLK ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ CLK ) - ( U0_UART_TX/U0_mux/OUT_reg CLK ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ CLK ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ CLK ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ CLK ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ CLK ) - ( U0_UART_TX/U0_fsm/busy_reg CLK ) - ( U0_UART_TX/U0_fsm/current_state_reg_2_ CLK ) - ( U0_UART_TX/U0_fsm/current_state_reg_1_ CLK ) - ( U0_UART_TX/U0_fsm/current_state_reg_0_ CLK ) - + NONDEFAULTRULE cts_w1_s2 - + ROUTED M1 ( 30968 15464 ) VIA12SQ_C ( * 16072 ) VIA23SQ_C W - NEW M3 ( 35224 12728 ) VIA34SQ_C - NEW M3 ( 35224 12728 ) ( 35984 * ) VIA23SQ_C W VIA12SQ_C - NEW M3 ( 41912 6344 ) VIA34SQ_C - NEW M4 ( 41912 3304 ) ( * 6344 ) - NEW M3 ( 41912 3304 ) VIA34SQ_C - NEW M2 ( 42064 3304 ) VIA23SQ_C W - NEW M1 ( 42064 3152 ) VIA12SQ_C - NEW M1 ( 34920 9992 ) VIA12SQ_C VIA23SQ_C W ( 35224 * ) VIA34SQ_C - NEW M1 ( 35072 13336 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 35224 13336 ) VIA34SQ_C - NEW M2 ( 35528 6344 ) VIA23SQ_C W - NEW M1 ( 35528 6496 ) VIA12SQ_C - NEW M3 ( 36136 20024 ) VIA34SQ_C - NEW M2 ( 36288 20024 ) VIA23SQ_C W - NEW M1 ( 36288 20024 ) VIA12SQ_C - NEW M3 ( 16376 6344 ) VIA34SQ_C - NEW M3 ( 16376 6344 ) ( 16680 * ) VIA23SQ_C W - NEW M1 ( 16680 6496 ) VIA12SQ_C - NEW M2 ( 19720 16072 ) VIA23SQ_C W - NEW M1 ( 19720 16224 ) VIA12SQ_C - NEW M4 ( 28536 9688 ) ( * 13336 ) - NEW M4 ( 36136 20024 ) ( * 20756 ) - NEW M4 ( 36136 20756 ) ( * 23064 ) VIA34SQ_C ( 37048 * ) VIA23SQ_C W - NEW M1 ( 37048 23216 ) VIA12SQ_C - NEW M3 ( 29752 16072 ) VIA34SQ_C ( * 16652 ) - NEW M4 ( 29752 16652 ) ( * 19720 ) VIA34SQ_C - NEW M2 ( 29904 19720 ) VIA23SQ_C W - NEW M1 ( 29904 19872 ) VIA12SQ_C - NEW M3 ( 37048 6040 ) ( * 6344 ) - NEW M2 ( 37048 6040 ) VIA23SQ_C W - NEW M1 ( 37048 6192 ) VIA12SQ_C - NEW M1 ( 36592 16528 ) VIA12SQ_C - NEW M2 ( 36592 16680 ) VIA23SQ_C W - NEW M2 ( 42064 16680 ) VIA23SQ_C W - NEW M1 ( 42064 16528 ) VIA12SQ_C - NEW M1 ( 18960 13184 ) VIA12SQ_C - NEW M2 ( 18960 13336 ) VIA23SQ_C W - NEW M1 ( 28840 13336 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 28536 13336 ) ( 28840 * ) - NEW M3 ( 28536 13336 ) VIA34SQ_C - NEW M1 ( 17288 9992 ) VIA12SQ_C VIA23SQ_C W ( 17592 * ) VIA34SQ_C - NEW M4 ( 28536 3304 ) ( * 6344 ) - NEW M3 ( 28536 3304 ) VIA34SQ_C - NEW M2 ( 28688 3304 ) VIA23SQ_C W - NEW M1 ( 28688 3152 ) VIA12SQ_C - NEW M1 ( 29144 16528 ) VIA12SQ_C - NEW M2 ( 29144 16680 ) VIA23SQ_C W - NEW M3 ( 28536 16680 ) ( 29144 * ) - NEW M3 ( 28536 16072 ) ( * 16680 ) - NEW M2 ( 42064 6344 ) VIA23SQ_C W - NEW M1 ( 42064 6496 ) VIA12SQ_C - NEW M2 ( 17592 9384 ) VIA23SQ_C W - NEW M1 ( 17592 9384 ) VIA12SQ_C - NEW M3 ( 37048 6344 ) ( 41887 * ) - NEW M3 ( 41912 16680 ) VIA34SQ_C ( * 19720 ) VIA34SQ_C - NEW M2 ( 42064 19720 ) VIA23SQ_C W - NEW M1 ( 42064 19872 ) VIA12SQ_C - NEW M4 ( 28536 13336 ) ( * 16072 ) VIA34SQ_C - NEW M4 ( 28536 6344 ) ( * 9688 ) - NEW M3 ( 16376 9384 ) ( 17592 * ) - NEW M3 ( 16376 9384 ) VIA34SQ_C - NEW M4 ( 16376 6344 ) ( * 9384 ) - NEW M3 ( 17592 9384 ) VIA34SQ_C ( * 9992 ) - NEW M4 ( 17592 9992 ) ( * 13336 ) VIA34SQ_C ( 18960 * ) - NEW M3 ( 22760 16072 ) ( 28536 * ) - NEW M3 ( 19720 16072 ) VIA34SQ_C - NEW M4 ( 19720 13336 ) ( * 16072 ) - NEW M3 ( 19720 13336 ) VIA34SQ_C - NEW M3 ( 18960 13336 ) ( 19720 * ) - NEW M3 ( 28536 6344 ) VIA34SQ_C - NEW M3 ( 26408 6344 ) ( 28536 * ) - NEW M2 ( 26408 6344 ) VIA23SQ_C W - NEW M1 ( 26408 6496 ) VIA12SQ_C - NEW M3 ( 36136 16680 ) ( 36592 * ) - NEW M3 ( 28536 9688 ) VIA34SQ_C - NEW M3 ( 26560 9688 ) ( 28536 * ) - NEW M2 ( 26560 9688 ) VIA23SQ_C W - NEW M1 ( 26560 9840 ) VIA12SQ_C - NEW M4 ( 35224 13336 ) ( * 16072 ) VIA34SQ_C - NEW M4 ( 35224 12728 ) ( * 13336 ) - NEW M3 ( 35224 16680 ) ( 36136 * ) - NEW M3 ( 35224 16072 ) ( * 16680 ) - NEW M3 ( 36136 16680 ) VIA34SQ_C ( * 20024 ) - NEW M3 ( 29752 16072 ) ( 30968 * ) - NEW M3 ( 28536 16072 ) ( 29752 * ) - NEW M3 ( 30968 16072 ) ( 35224 * ) - NEW M4 ( 35224 9992 ) ( * 12728 ) - NEW M4 ( 35224 9992 ) ( 35528 * ) - NEW M4 ( 35528 6648 ) ( * 9992 ) - NEW M3 ( 35528 6648 ) VIA34SQ_C - NEW M3 ( 35528 6344 ) ( * 6648 ) - NEW M3 ( 35528 6344 ) ( 37048 * ) - NEW M3 ( 19720 16072 ) ( 22760 * ) - NEW M1 ( 22912 16528 ) VIA12SQ_C - NEW M2 ( 22912 16680 ) VIA23SQ_C W - NEW M3 ( 22760 16680 ) VIA34SQ_C - NEW M4 ( 22760 16072 ) ( * 16680 ) - NEW M3 ( 22760 16072 ) VIA34SQ_C - NEW M1 ( 15768 3152 ) VIA12SQ_C - NEW M2 ( 15768 3304 ) VIA23SQ_C W ( 16376 * ) VIA34SQ_C ( * 5916 ) - NEW M4 ( 16376 5916 ) ( * 6344 ) - NEW M3 ( 36592 16680 ) ( 41887 * ) - + USE CLOCK ; - - SCAN_RST - ( U2_mux2X1/U1 Y ) - ( U0_UART_RX/HFSBUF_432_1 A ) - ( HFSBUF_223_2 A ) - + ROUTED M1 ( 23520 4368 ) ( 23672 * ) VIA12SQ_C ( * 4824 ) VIA23SQ_C W ( 24888 * ) VIA23SQ_C W ( * 5432 ) VIA12SQ_C - NEW M1 ( 22000 5432 ) VIA12SQ_C - NEW M2 ( 22000 4824 ) ( * 5432 ) - NEW M2 ( 22000 4824 ) VIA23SQ_C W ( 23672 * ) - + USE SIGNAL ; - - U1_mux2X1/cts0 - ( U1_mux2X1/IN_0_btd306 Y ) - ( U1_mux2X1/U1 A1 ) - + ROUTED M1 ( 29296 15312 ) VIA12SQ_C - NEW M2 ( 29296 4520 ) ( * 15312 ) - NEW M2 ( 29296 4520 ) VIA23SQ_C W - NEW M3 ( 19568 4520 ) ( 29296 * ) - NEW M2 ( 19568 4520 ) VIA23SQ_C W - NEW M2 ( 19568 4105 ) ( * 4520 ) - NEW M1 ( 19568 4105 ) VIA12SQ_C - + USE SIGNAL ; - - U0_mux2X1/cts0 - ( U0_mux2X1/IN_0_btd307 Y ) - ( U0_mux2X1/U1 A1 ) - + ROUTED M1 ( 29904 35376 ) VIA12SQ_C - NEW M2 ( 29752 35376 ) ( 29904 * ) - NEW M2 ( 29752 32792 ) ( * 35376 ) - NEW M2 ( 29752 32792 ) VIA23SQ_C W VIA34SQ_C VIA45SQ_C W - NEW M5 ( 4216 32792 ) ( 29752 * ) - NEW M4 ( 4216 32792 ) VIA45SQ_C W - NEW M4 ( 4216 28232 ) ( * 32792 ) - NEW M3 ( 4216 28232 ) VIA34SQ_C - NEW M3 ( 3608 28232 ) ( 4216 * ) - NEW M2 ( 3608 28232 ) VIA23SQ_C W - NEW M2 ( 3608 26256 ) ( * 28232 ) - NEW M1 ( 3608 26256 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/seriz_done - ( U0_UART_TX/U0_Serializer/U18 Y ) - ( U0_UART_TX/U0_fsm/U8 A ) - + ROUTED M1 ( 40544 15464 ) VIA12SQ_C ( * 18200 ) VIA12SQ_C ( 40696 * ) - + USE SIGNAL ; - - U0_UART_TX/seriz_en - ( U0_UART_TX/U0_fsm/U18 Y ) - ( U0_UART_TX/U0_Serializer/U34 A1 ) - ( U0_UART_TX/U0_Serializer/U33 A1 ) - ( U0_UART_TX/U0_Serializer/U32 A1 ) - ( U0_UART_TX/U0_Serializer/U31 A1 ) - ( U0_UART_TX/U0_Serializer/U28 A1 ) - + ROUTED M1 ( 38872 10600 ) ( 39146 * ) - NEW M1 ( 38872 10600 ) VIA12SQ_C - NEW M1 ( 35832 9080 ) VIA12SQ_C W VIA23SQ_C W ( 38872 * ) VIA23SQ_C W ( * 10600 ) - NEW M2 ( 38872 22456 ) VIA23SQ_C W ( 40696 * ) - NEW M1 ( 38598 22304 ) ( 38872 * ) VIA12SQ_C - NEW M3 ( 40696 22456 ) ( 41912 * ) - NEW M1 ( 44952 23672 ) VIA12SQ_C - NEW M2 ( 44952 22456 ) ( * 23672 ) - NEW M2 ( 44952 22456 ) VIA23SQ_C W - NEW M3 ( 41912 22456 ) ( 44952 * ) - NEW M1 ( 40696 22304 ) VIA12SQ_C - NEW M2 ( 40696 22456 ) VIA23SQ_C W - NEW M2 ( 38872 10600 ) ( * 22279 ) - NEW M1 ( 41912 22304 ) VIA12SQ_C - NEW M2 ( 41912 22456 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/ser_data - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ Q ) - ( U0_UART_TX/U0_Serializer/U19 A5 ) - ( U0_UART_TX/U0_mux/U7 A2 ) - + ROUTED M1 ( 38416 13640 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 30489 8771 ) ( 30604 * ) - NEW M1 ( 30489 8814 ) ( 30604 * ) - NEW M1 ( 39632 13640 ) ( 42034 * ) - NEW M1 ( 39632 13640 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 38416 13640 ) ( 39632 * ) - NEW M1 ( 30664 8776 ) VIA12SQ_C ( * 13640 ) VIA23SQ_C W ( 33704 * ) - NEW M3 ( 33704 13640 ) ( * 13944 ) - NEW M3 ( 33704 13944 ) ( 35832 * ) - NEW M3 ( 35832 13640 ) ( * 13944 ) - NEW M3 ( 35832 13640 ) ( 38416 * ) - + USE SIGNAL ; - - U0_UART_TX/parity - ( U0_UART_TX/U0_parity_calc/parity_reg Q ) - ( U0_UART_TX/U0_parity_calc/U2 A1 ) - ( U0_UART_TX/U0_mux/U8 A3 ) - + ROUTED M1 ( 42672 14856 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M3 ( 39936 17592 ) ( 42672 * ) - NEW M1 ( 39936 16984 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M1 ( 38142 18808 ) ( 38568 * ) VIA12SQ_C - NEW M2 ( 38568 17592 ) ( * 18808 ) - NEW M2 ( 38568 17592 ) VIA23SQ_C W ( 39936 * ) - + USE SIGNAL ; - - U0_UART_TX/n3 - ( U0_UART_TX/U0_parity_calc/parity_reg QN ) - ( U0_UART_TX/U0_mux/OUT_reg SI ) - + ROUTED M1 ( 41396 16680 ) VIA12SQ_C_1_2 - NEW M2 ( 41456 16680 ) ( * 17288 ) VIA23SQ_C W - NEW M3 ( 40113 17288 ) ( 41456 * ) - NEW M2 ( 40113 17288 ) VIA23SQ_C W - NEW M2 ( 40113 16832 ) ( * 17288 ) - NEW M1 ( 40113 16832 ) VIA12SQ_C W - + USE SIGNAL ; - - U0_UART_TX/mux_sel[1] - ( U0_UART_TX/U0_fsm/U15 Y ) - ( U0_UART_TX/U0_mux/U5 A ) - ( U0_UART_TX/U0_mux/U6 A1 ) - + ROUTED M1 ( 45408 15464 ) VIA12SQ_C - NEW M2 ( 45408 13944 ) ( * 15464 ) - NEW M2 ( 45256 13944 ) ( 45408 * ) - NEW M1 ( 45104 13944 ) VIA12SQ_C ( 45256 * ) - NEW M1 ( 45256 9536 ) VIA12SQ_C ( * 13944 ) - + USE SIGNAL ; - - U0_UART_TX/mux_sel[0] - ( U0_UART_TX/U0_fsm/U16 Y ) - ( U0_UART_TX/U0_mux/U4 A ) - ( U0_UART_TX/U0_mux/U8 A2 ) - ( U0_UART_TX/U0_mux/U7 A1 ) - + ROUTED M1 ( 41912 12880 ) VIA12SQ_C ( * 13944 ) VIA12SQ_C - NEW M1 ( 41912 15768 ) ( 42338 * ) - NEW M1 ( 41912 15768 ) VIA12SQ_C - NEW M2 ( 41912 13944 ) ( * 15768 ) - NEW M1 ( 44040 13944 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 41912 13944 ) ( 44040 * ) - NEW M2 ( 41912 13944 ) VIA23SQ_C W - + USE SIGNAL ; - - HFSNET_0 - ( HFSBUF_156_0 Y ) - ( U0_UART_TX/U0_parity_calc/parity_reg SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ SE ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ SE ) - ( U0_UART_TX/U0_mux/OUT_reg SE ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ SE ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ SE ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ SE ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ SE ) - ( U0_UART_TX/U0_fsm/busy_reg SE ) - ( U0_UART_TX/U0_fsm/current_state_reg_2_ SE ) - ( U0_UART_TX/U0_fsm/current_state_reg_1_ SE ) - ( U0_UART_TX/U0_fsm/current_state_reg_0_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ SE ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ SE ) - + ROUTED M2 ( 35224 19720 ) VIA23SQ_C W ( 40696 * ) VIA23SQ_C W - NEW M1 ( 40696 4064 ) VIA12SQ_C ( * 5128 ) - NEW M1 ( 40696 7316 ) VIA12SQ_C - NEW M2 ( 40696 5128 ) ( * 7316 ) - NEW M2 ( 25192 10752 ) ( * 14248 ) VIA23SQ_C W ( 27472 * ) VIA23SQ_C W - NEW M1 ( 14400 4064 ) VIA12SQ_C ( * 6952 ) VIA23SQ_C W ( 15312 * ) VIA23SQ_C W ( * 7408 ) VIA12SQ_C - NEW M2 ( 35224 17592 ) ( * 19720 ) - NEW M1 ( 27168 4064 ) VIA12SQ_C - NEW M2 ( 27168 4216 ) VIA23SQ_C W - NEW M3 ( 25192 4216 ) ( 27168 * ) - NEW M2 ( 25192 4216 ) VIA23SQ_C W - NEW M2 ( 25192 4216 ) ( * 7408 ) - NEW M1 ( 34160 7408 ) VIA12SQ_C - NEW M1 ( 25192 7408 ) VIA12SQ_C - NEW M1 ( 33704 14096 ) VIA12SQ_C - NEW M1 ( 34920 20784 ) VIA12SQ_C ( * 20936 ) - NEW M2 ( 34920 20936 ) ( 35224 * ) - NEW M2 ( 35680 5128 ) VIA23SQ_C W - NEW M1 ( 35680 5280 ) VIA12SQ_C - NEW M1 ( 40696 20784 ) VIA12SQ_C - NEW M2 ( 40696 19720 ) ( * 20759 ) - NEW M2 ( 17592 14552 ) ( * 15160 ) VIA23SQ_C W ( 18352 * ) VIA23SQ_C W - NEW M2 ( 21544 17288 ) VIA23SQ_C W - NEW M1 ( 17592 14096 ) VIA12SQ_C ( * 14552 ) - NEW M1 ( 15920 10752 ) VIA12SQ_C - NEW M1 ( 22760 41608 ) VIA12SQ_C ( 23064 * ) - NEW M2 ( 23064 24128 ) ( * 41608 ) - NEW M1 ( 27776 17440 ) VIA12SQ_C - NEW M1 ( 27472 14096 ) VIA12SQ_C - NEW M1 ( 25192 10752 ) VIA12SQ_C - NEW M1 ( 35224 17440 ) VIA12SQ_C - NEW M1 ( 28688 20784 ) VIA12SQ_C - NEW M1 ( 22912 22000 ) VIA12SQ_C - NEW M2 ( 33856 10904 ) ( * 11816 ) - NEW M2 ( 33856 11816 ) ( * 12424 ) - NEW M2 ( 33704 12424 ) ( 33856 * ) - NEW M2 ( 33704 12424 ) ( * 14096 ) - NEW M3 ( 34160 5128 ) ( 35680 * ) - NEW M2 ( 34160 5128 ) VIA23SQ_C W - NEW M2 ( 34160 5128 ) ( * 7408 ) - NEW M2 ( 21544 17440 ) ( * 21544 ) VIA23SQ_C W ( 22912 * ) VIA23SQ_C W ( * 22000 ) - NEW M2 ( 15920 10904 ) ( * 14552 ) VIA23SQ_C W ( 17592 * ) VIA23SQ_C W - NEW M2 ( 25192 7408 ) ( * 10752 ) - NEW M2 ( 34008 7408 ) ( 34160 * ) - NEW M2 ( 34008 7408 ) ( * 9688 ) - NEW M2 ( 33856 9688 ) ( 34008 * ) - NEW M2 ( 33856 9688 ) ( * 10904 ) - NEW M2 ( 35224 19720 ) ( * 20936 ) VIA23SQ_C W - NEW M2 ( 28688 20936 ) VIA23SQ_C W ( 35224 * ) - NEW M2 ( 33704 14096 ) ( * 17592 ) VIA23SQ_C W ( 35224 * ) VIA23SQ_C W - NEW M2 ( 27776 14248 ) ( * 17263 ) - NEW M2 ( 27472 14248 ) ( 27776 * ) - NEW M2 ( 27776 17288 ) VIA23SQ_C W - NEW M3 ( 21544 17288 ) ( 27776 * ) - NEW M2 ( 18352 15312 ) ( * 16984 ) VIA23SQ_C W ( 21544 * ) - NEW M3 ( 21544 16984 ) ( * 17288 ) - NEW M1 ( 18352 15312 ) VIA12SQ_C - NEW M3 ( 35224 20936 ) ( 35680 * ) VIA23SQ_C W ( * 24036 ) VIA12SQ_C - NEW M3 ( 35680 5128 ) ( 40696 * ) VIA23SQ_C W - NEW M1 ( 40696 17440 ) VIA12SQ_C ( * 19720 ) - NEW M3 ( 27776 17288 ) ( 28688 * ) VIA23SQ_C W ( * 20784 ) - NEW M2 ( 15312 8776 ) ( * 10904 ) VIA23SQ_C W ( 15920 * ) VIA23SQ_C W - NEW M1 ( 21544 17440 ) VIA12SQ_C - NEW M2 ( 15312 7408 ) ( * 8776 ) - NEW M2 ( 33856 11816 ) VIA23SQ_C W ( 34616 * ) VIA23SQ_C W - NEW M1 ( 34616 11968 ) VIA12SQ_C - NEW M1 ( 16224 8776 ) VIA12SQ_C - NEW M2 ( 15312 8776 ) ( 16224 * ) - NEW M1 ( 33552 10752 ) VIA12SQ_C - NEW M2 ( 33552 10904 ) VIA23SQ_C W ( 33856 * ) VIA23SQ_C W - NEW M2 ( 23064 22152 ) ( * 24128 ) - NEW M2 ( 22912 22152 ) ( 23064 * ) - NEW M2 ( 22912 22000 ) ( * 22152 ) - NEW M2 ( 23064 24128 ) ( 23520 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/dftopt2_gOb7 - ( U0_UART_TX/U0_fsm/current_state_reg_2_ Q ) - ( U0_UART_TX/U0_fsm/busy_reg SI ) - ( U0_UART_TX/U0_fsm/U16 A3 ) - ( U0_UART_TX/U0_fsm/U9 A2 ) - + ROUTED M1 ( 39328 12424 ) VIA12SQ_C - NEW M2 ( 39328 11816 ) ( * 12424 ) - NEW M1 ( 36380 6040 ) VIA12SQ_C_1_2 - NEW M2 ( 36440 4824 ) ( * 6040 ) - NEW M2 ( 36440 4824 ) VIA23SQ_C W ( 39328 * ) VIA23SQ_C W ( * 11816 ) - NEW M1 ( 40848 11816 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 39328 11816 ) ( 40848 * ) - NEW M2 ( 39328 11816 ) VIA23SQ_C W - NEW M1 ( 42368 11512 ) VIA12SQ_C ( * 11816 ) VIA23SQ_C W - NEW M3 ( 40848 11816 ) ( 42368 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/current_state_1_ - ( U0_UART_TX/U0_fsm/current_state_reg_1_ Q ) - ( U0_UART_TX/U0_fsm/U21 A1 ) - + ROUTED M1 ( 45408 6952 ) VIA12SQ_C - NEW M2 ( 45408 5584 ) ( * 6952 ) - NEW M1 ( 45408 5584 ) VIA12SQ_C - NEW M1 ( 44830 5584 ) ( 45408 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/current_state_0_ - ( U0_UART_TX/U0_fsm/current_state_reg_0_ Q ) - ( U0_UART_TX/U0_fsm/U20 A1 ) - ( U0_UART_TX/U0_fsm/U19 A2 ) - ( U0_UART_TX/U0_fsm/U17 A1 ) - ( U0_UART_TX/U0_fsm/U14 A2 ) - ( U0_UART_TX/U0_fsm/U13 A1 ) - ( U0_UART_TX/U0_fsm/U10 A3 ) - + ROUTED M1 ( 38568 15616 ) VIA12SQ_C - NEW M2 ( 38568 14856 ) ( * 15616 ) - NEW M2 ( 38568 14856 ) VIA23SQ_C W VIA34SQ_C - NEW M4 ( 38568 8472 ) ( * 14856 ) - NEW M3 ( 38568 8472 ) VIA34SQ_C - NEW M3 ( 38568 8472 ) ( 38872 * ) - NEW M1 ( 38872 8776 ) VIA12SQ_C - NEW M2 ( 38872 8472 ) ( * 8776 ) - NEW M2 ( 38872 8472 ) VIA23SQ_C W - NEW M1 ( 42459 5584 ) ( 42976 * ) VIA12SQ_C - NEW M1 ( 43888 10448 ) VIA12SQ_C - NEW M2 ( 43888 8776 ) ( * 10448 ) - NEW M1 ( 43888 8776 ) VIA12SQ_C W - NEW M1 ( 43128 8776 ) ( 43888 * ) - NEW M2 ( 42976 4520 ) VIA23SQ_C W - NEW M2 ( 42976 4520 ) ( * 5584 ) - NEW M1 ( 45104 4368 ) VIA12SQ_C - NEW M2 ( 45104 4520 ) VIA23SQ_C W - NEW M3 ( 42976 4520 ) ( 45104 * ) - NEW M2 ( 42976 5584 ) ( * 8472 ) - NEW M1 ( 43128 8776 ) VIA12SQ_C - NEW M2 ( 43128 8472 ) ( * 8776 ) - NEW M2 ( 42976 8472 ) ( 43128 * ) - NEW M1 ( 39176 3937 ) VIA12BAR_C ( * 4520 ) VIA23SQ_C W ( 42976 * ) - NEW M3 ( 38872 8472 ) ( 42976 * ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/busy_c - ( U0_UART_TX/U0_fsm/U17 Y ) - ( U0_UART_TX/U0_fsm/busy_reg D ) - + ROUTED M1 ( 36136 5432 ) VIA12SQ_C VIA23SQ_C W ( 41720 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n5 - ( U0_UART_TX/U0_fsm/current_state_reg_2_ QN ) - ( U0_UART_TX/U0_fsm/U18 A1 ) - ( U0_UART_TX/U0_fsm/U17 A2 ) - ( U0_UART_TX/U0_fsm/U16 A2 ) - ( U0_UART_TX/U0_fsm/U15 A2 ) - ( U0_UART_TX/U0_fsm/U12 A2 ) - ( U0_UART_TX/U0_fsm/U11 A3 ) - + ROUTED M2 ( 39784 10600 ) VIA23SQ_C W ( 41456 * ) - NEW M1 ( 41456 10448 ) VIA12SQ_C - NEW M1 ( 39936 8776 ) VIA12SQ_C VIA23SQ_C W ( 41304 * ) - NEW M1 ( 44040 8776 ) ( 44314 * ) - NEW M1 ( 44040 8776 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 42672 8776 ) ( 44040 * ) - NEW M1 ( 42672 5432 ) VIA12SQ_C ( * 8776 ) VIA23SQ_C W - NEW M1 ( 39784 10600 ) VIA12SQ_C - NEW M2 ( 41304 8776 ) VIA23SQ_C W - NEW M2 ( 41304 8776 ) ( * 10600 ) - NEW M2 ( 41304 10600 ) ( 41456 * ) - NEW M3 ( 41304 8776 ) ( 42672 * ) - NEW M2 ( 41456 10600 ) VIA23SQ_C W - NEW M1 ( 39510 11539 ) ( 39634 * ) - NEW M1 ( 39510 11544 ) ( 39634 * ) - NEW M1 ( 39632 11539 ) VIA12SQ_C - NEW M2 ( 39632 10600 ) ( * 11539 ) - NEW M2 ( 39632 10600 ) ( 39784 * ) - NEW M3 ( 41456 10600 ) ( 42520 * ) VIA23SQ_C W ( * 12424 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n8 - ( U0_UART_TX/U0_fsm/current_state_reg_0_ QN ) - ( U0_UART_TX/U0_fsm/current_state_reg_1_ SI ) - ( U0_UART_TX/U0_fsm/U21 A2 ) - ( U0_UART_TX/U0_fsm/U15 A1 ) - + ROUTED M1 ( 45560 3456 ) VIA12SQ_C - NEW M2 ( 44952 3456 ) ( 45560 * ) - NEW M2 ( 44952 3456 ) ( * 5432 ) - NEW M1 ( 44344 8928 ) ( 44557 * ) - NEW M1 ( 44344 8928 ) VIA12SQ_C - NEW M2 ( 44344 7560 ) ( * 8928 ) - NEW M2 ( 44344 7560 ) VIA23SQ_C W - NEW M1 ( 44952 5432 ) VIA12SQ_C - NEW M1 ( 41396 6648 ) VIA12SQ_C_1_2 - NEW M2 ( 41456 6648 ) ( * 7560 ) VIA23SQ_C W ( 44344 * ) - NEW M3 ( 44344 7560 ) ( 44952 * ) VIA23SQ_C W - NEW M2 ( 44952 5432 ) ( * 7560 ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n10 - ( U0_UART_TX/U0_fsm/U10 Y ) - ( U0_UART_TX/U0_fsm/U9 A3 ) - + ROUTED M1 ( 40544 11968 ) VIA12SQ_C ( * 15160 ) VIA23SQ_C W - NEW M3 ( 38112 15160 ) ( 40544 * ) - NEW M2 ( 38112 15160 ) VIA23SQ_C W - NEW M1 ( 38112 15160 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n11 - ( U0_UART_TX/U0_fsm/U19 Y ) - ( U0_UART_TX/U0_fsm/U18 A3 ) - ( U0_UART_TX/U0_fsm/U11 A1 ) - + ROUTED M1 ( 41912 9536 ) ( 42520 * ) - NEW M1 ( 41912 9536 ) VIA12SQ_C - NEW M1 ( 41912 10600 ) VIA12SQ_C - NEW M2 ( 41912 9688 ) ( * 10600 ) - NEW M1 ( 40240 10600 ) VIA12SQ_C - NEW M2 ( 40240 9688 ) ( * 10600 ) - NEW M2 ( 40240 9688 ) VIA23SQ_C W ( 41912 * ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n12 - ( U0_UART_TX/U0_fsm/U20 Y ) - ( U0_UART_TX/U0_fsm/U7 A ) - ( U0_UART_TX/U0_fsm/U11 A2 ) - + ROUTED M1 ( 44800 12120 ) VIA12SQ_C - NEW M2 ( 44648 12120 ) ( 44800 * ) - NEW M2 ( 44648 10144 ) ( * 12120 ) - NEW M1 ( 44648 10144 ) VIA12SQ_C - NEW M1 ( 41760 9844 ) VIA12SQ_C - NEW M2 ( 41760 9992 ) VIA23SQ_C W ( 44648 * ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n13 - ( U0_UART_TX/U0_fsm/U13 Y ) - ( U0_UART_TX/U0_fsm/U12 A1 ) - + ROUTED M1 ( 40088 8928 ) VIA12SQ_C ( * 9384 ) VIA23SQ_C W - NEW M3 ( 37960 9384 ) ( 40088 * ) - NEW M2 ( 37960 9384 ) VIA23SQ_C W - NEW M1 ( 37960 9384 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n14 - ( U0_UART_TX/U0_fsm/U14 Y ) - ( U0_UART_TX/U0_fsm/U13 A3 ) - + ROUTED M1 ( 38416 8168 ) VIA12SQ_C ( 38568 * ) - NEW M2 ( 38568 4216 ) ( * 8168 ) - NEW M1 ( 38568 4216 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n15 - ( U0_UART_TX/U0_fsm/U21 Y ) - ( U0_UART_TX/U0_fsm/U20 A3 ) - ( U0_UART_TX/U0_fsm/U17 A3 ) - ( U0_UART_TX/U0_fsm/U16 A4 ) - ( U0_UART_TX/U0_fsm/U15 A3 ) - + ROUTED M2 ( 44192 5280 ) ( 44496 * ) - NEW M2 ( 44496 5280 ) ( * 8168 ) - NEW M1 ( 44192 5280 ) VIA12SQ_C - NEW M1 ( 42246 4824 ) ( 42520 * ) VIA12SQ_C ( * 5432 ) VIA23SQ_C W ( 44192 * ) VIA23SQ_C W - NEW M1 ( 44192 11208 ) VIA12SQ_C VIA23SQ_C W ( 44496 * ) - NEW M1 ( 42672 11968 ) VIA12SQ_C - NEW M2 ( 42672 11512 ) ( * 11968 ) - NEW M2 ( 42672 11512 ) VIA23SQ_C W ( 44496 * ) - NEW M3 ( 44496 11208 ) ( * 11512 ) - NEW M2 ( 44496 8168 ) ( * 11208 ) VIA23SQ_C W - NEW M1 ( 44496 8168 ) VIA12SQ_C - NEW M1 ( 44496 8168 ) ( 44800 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n6 - ( U0_UART_TX/U0_fsm/U8 Y ) - ( U0_UART_TX/U0_fsm/U18 A2 ) - ( U0_UART_TX/U0_fsm/U13 A2 ) - ( U0_UART_TX/U0_fsm/U10 A2 ) - + ROUTED M1 ( 38720 16224 ) VIA12SQ_C - NEW M2 ( 38720 15768 ) ( * 16224 ) - NEW M2 ( 38720 15768 ) VIA23SQ_C W ( 39936 * ) VIA23SQ_C W - NEW M2 ( 39936 15312 ) ( * 15768 ) - NEW M1 ( 39936 10296 ) VIA12SQ_C - NEW M1 ( 39936 15312 ) ( 40210 * ) - NEW M1 ( 39936 15312 ) VIA12SQ_C - NEW M2 ( 39936 10296 ) ( * 15312 ) - NEW M1 ( 38750 9080 ) ( 39632 * ) VIA12SQ_C ( * 9992 ) VIA23SQ_C W ( 39936 * ) - NEW M3 ( 39936 9992 ) ( * 10296 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/n9 - ( U0_UART_TX/U0_fsm/U7 Y ) - ( U0_UART_TX/U0_fsm/U19 A1 ) - ( U0_UART_TX/U0_fsm/U16 A1 ) - + ROUTED M1 ( 42824 12120 ) VIA12SQ_C ( 42976 * ) - NEW M1 ( 42976 8928 ) VIA12SQ_C ( * 12120 ) - NEW M1 ( 44344 11968 ) VIA12SQ_C - NEW M2 ( 44344 12120 ) VIA23SQ_C W - NEW M3 ( 42976 12120 ) ( 44344 * ) - NEW M2 ( 42976 12120 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/dftopt1_gOb4 - ( U0_UART_TX/U0_fsm/busy_reg QN ) - ( U0_UART_TX/U0_fsm/current_state_reg_0_ SI ) - + ROUTED M1 ( 40574 4851 ) ( 41304 * ) VIA12SQ_C - NEW M2 ( 41304 3304 ) ( * 4851 ) - NEW M1 ( 41304 3304 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/next_state[2] - ( U0_UART_TX/U0_fsm/U9 Y ) - ( U0_UART_TX/U0_fsm/current_state_reg_2_ D ) - + ROUTED M1 ( 35072 12120 ) VIA12SQ_C VIA23SQ_C W ( 39784 * ) VIA23SQ_C W - NEW M2 ( 39784 11816 ) ( * 12120 ) - NEW M1 ( 39784 11816 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/next_state[1] - ( U0_UART_TX/U0_fsm/U11 Y ) - ( U0_UART_TX/U0_fsm/current_state_reg_1_ D ) - + ROUTED M1 ( 41152 7256 ) VIA12SQ_C ( * 9992 ) - NEW M2 ( 41000 9992 ) ( 41152 * ) - NEW M1 ( 41000 9992 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_fsm/next_state[0] - ( U0_UART_TX/U0_fsm/U12 Y ) - ( U0_UART_TX/U0_fsm/current_state_reg_0_ D ) - + ROUTED M1 ( 41152 3912 ) VIA12SQ_C - NEW M2 ( 41000 3912 ) ( 41152 * ) - NEW M2 ( 41000 3912 ) ( * 8168 ) VIA12SQ_C - NEW M1 ( 40544 8168 ) ( 41000 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt2 - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ QN ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ SI ) - + ROUTED M1 ( 24372 43432 ) VIA12SQ_C_1_2 - NEW M2 ( 24432 43432 ) VIA23SQ_C W - NEW M3 ( 22000 43432 ) ( 24432 * ) - NEW M2 ( 22000 43432 ) VIA23SQ_C W - NEW M1 ( 22000 43559 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/N23 - ( U0_UART_TX/U0_Serializer/U34 Y ) - ( U0_UART_TX/U0_Serializer/U32 A3 ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ D ) - + ROUTED M1 ( 35376 20632 ) VIA12SQ_C ( * 21544 ) VIA23SQ_C W ( 37960 * ) - NEW M1 ( 42064 21544 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 37960 21544 ) ( 42064 * ) - NEW M1 ( 37960 22000 ) VIA12SQ_C - NEW M2 ( 37960 21544 ) ( * 22000 ) - NEW M2 ( 37960 21544 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/N24 - ( U0_UART_TX/U0_Serializer/U33 Y ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ D ) - + ROUTED M1 ( 36136 23976 ) VIA12SQ_C VIA23SQ_C W ( 40088 * ) VIA23SQ_C W - NEW M2 ( 40088 22912 ) ( * 23976 ) - NEW M1 ( 40088 22912 ) VIA12SQ_C - NEW M1 ( 40088 22912 ) ( 40240 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/N25 - ( U0_UART_TX/U0_Serializer/U30 Y ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ D ) - + ROUTED M1 ( 41304 20632 ) VIA12SQ_C VIA23SQ_C W ( 43736 * ) VIA23SQ_C W ( * 21696 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n13 - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ QN ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ SI ) - ( U0_UART_TX/U0_Serializer/U17 A1 ) - ( U0_UART_TX/U0_Serializer/U32 A2 ) - + ROUTED M1 ( 41608 22152 ) VIA12SQ_C ( * 23064 ) VIA23SQ_C W - NEW M1 ( 40574 23520 ) ( 41000 * ) VIA12SQ_C - NEW M2 ( 41000 23064 ) ( * 23520 ) - NEW M2 ( 41000 23064 ) VIA23SQ_C W - NEW M1 ( 42976 24128 ) VIA12SQ_C - NEW M2 ( 42976 23064 ) ( * 24128 ) - NEW M2 ( 42976 23064 ) VIA23SQ_C W - NEW M3 ( 41608 23064 ) ( 42976 * ) - NEW M3 ( 41000 23064 ) ( 41608 * ) - NEW M1 ( 35832 20024 ) VIA12SQ_C ( * 21240 ) VIA23SQ_C W ( 37048 * ) - NEW M3 ( 37048 20936 ) ( * 21240 ) - NEW M3 ( 37048 20936 ) ( 38112 * ) - NEW M3 ( 38112 20632 ) ( * 20936 ) - NEW M3 ( 38112 20632 ) ( 40392 * ) VIA23SQ_C W ( * 23064 ) VIA23SQ_C W ( 41000 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n18 - ( U0_UART_TX/U0_Serializer/U27 Y ) - ( U0_UART_TX/U0_Serializer/U26 A5 ) - ( U0_UART_TX/U0_Serializer/U25 A6 ) - ( U0_UART_TX/U0_Serializer/U24 A6 ) - ( U0_UART_TX/U0_Serializer/U23 A6 ) - ( U0_UART_TX/U0_Serializer/U22 A6 ) - ( U0_UART_TX/U0_Serializer/U21 A6 ) - ( U0_UART_TX/U0_Serializer/U20 A2 ) - ( U0_UART_TX/U0_Serializer/U19 A6 ) - + ROUTED M1 ( 30664 8320 ) VIA12SQ_C W ( * 8472 ) VIA23SQ_C W - NEW M1 ( 24280 5736 ) VIA12SQ_C ( * 7560 ) VIA23SQ_C W - NEW M1 ( 22760 7712 ) VIA12SQ_C W - NEW M2 ( 22760 7560 ) ( * 7712 ) - NEW M2 ( 22760 7560 ) VIA23SQ_C W - NEW M2 ( 32184 8472 ) ( 32488 * ) - NEW M2 ( 32184 7712 ) ( * 8472 ) - NEW M1 ( 32184 7712 ) VIA12SQ_C - NEW M3 ( 24736 8472 ) ( 30664 * ) - NEW M1 ( 29752 5275 ) ( 29906 * ) - NEW M1 ( 29752 5280 ) ( 29906 * ) - NEW M1 ( 29904 5280 ) VIA12SQ_C - NEW M2 ( 29904 5128 ) VIA23SQ_C W ( 32488 * ) - NEW M1 ( 32640 8776 ) VIA12SQ_C W - NEW M2 ( 32640 8472 ) ( * 8776 ) - NEW M2 ( 32488 8472 ) ( 32640 * ) - NEW M3 ( 24280 7560 ) ( * 8472 ) - NEW M3 ( 24280 8472 ) ( 24736 * ) - NEW M3 ( 30664 8472 ) ( 32488 * ) VIA23SQ_C W - NEW M1 ( 24736 8320 ) VIA12SQ_C W ( * 8472 ) VIA23SQ_C W - NEW M3 ( 22760 7560 ) ( 24280 * ) - NEW M2 ( 32488 5128 ) ( * 8472 ) - NEW M2 ( 32488 5128 ) VIA23SQ_C W - NEW M1 ( 22000 8320 ) VIA12SQ_C W - NEW M2 ( 22000 7560 ) ( * 8320 ) - NEW M2 ( 22000 7560 ) VIA23SQ_C W ( 22760 * ) - NEW M3 ( 32488 5128 ) ( 33248 * ) VIA23SQ_C W - NEW M1 ( 33248 5255 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n19 - ( U0_UART_TX/U0_Serializer/U29 Y ) - ( U0_UART_TX/U0_Serializer/U15 A ) - ( U0_UART_TX/U0_Serializer/U28 A2 ) - ( U0_UART_TX/U0_Serializer/U27 A1 ) - + ROUTED M1 ( 35680 3760 ) VIA12SQ_C - NEW M2 ( 32640 3912 ) VIA23SQ_C W ( 35680 * ) VIA23SQ_C W - NEW M1 ( 32640 3912 ) VIA12SQ_C - NEW M1 ( 35832 8776 ) VIA12SQ_C - NEW M2 ( 35832 3912 ) ( * 8776 ) - NEW M2 ( 35680 3912 ) ( 35832 * ) - NEW M2 ( 32640 3912 ) ( * 5432 ) VIA23SQ_C W ( 33856 * ) VIA23SQ_C W - NEW M1 ( 33856 5584 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n20 - ( U0_UART_TX/U0_Serializer/U28 Y ) - ( U0_UART_TX/U0_Serializer/U14 A ) - ( U0_UART_TX/U0_Serializer/U27 A2 ) - + ROUTED M1 ( 34038 5432 ) ( 34464 * ) VIA12SQ_C ( * 6648 ) - NEW M1 ( 35984 8472 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 34464 8472 ) ( 35984 * ) - NEW M2 ( 34464 8472 ) VIA23SQ_C W - NEW M2 ( 34464 6648 ) ( * 8472 ) - NEW M1 ( 33400 7256 ) VIA12SQ_C - NEW M2 ( 33400 6648 ) ( * 7256 ) - NEW M2 ( 33400 6648 ) VIA23SQ_C W ( 34464 * ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n21 - ( U0_UART_TX/U0_Serializer/U32 Y ) - ( U0_UART_TX/U0_Serializer/U30 A2 ) - + ROUTED M1 ( 44648 22152 ) VIA12SQ_C ( * 22760 ) VIA23SQ_C W - NEW M3 ( 42520 22760 ) ( 44648 * ) - NEW M2 ( 42520 22760 ) VIA23SQ_C W - NEW M1 ( 42520 22760 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n22 - ( U0_UART_TX/U0_Serializer/U31 Y ) - ( U0_UART_TX/U0_Serializer/U30 A3 ) - + ROUTED M1 ( 44192 21544 ) VIA12SQ_C ( * 23216 ) VIA12SQ_C ( 44496 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n23 - ( U0_UART_TX/U0_Serializer/U17 Y ) - ( U0_UART_TX/U0_Serializer/U33 A2 ) - + ROUTED M1 ( 41304 23824 ) ( 41608 * ) - NEW M1 ( 41304 23824 ) VIA12SQ_C - NEW M2 ( 41304 22152 ) ( * 23824 ) - NEW M1 ( 41304 22152 ) VIA12SQ_C - NEW M1 ( 40848 22152 ) ( 41304 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n24 - ( U0_UART_TX/U0_Serializer/U19 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ D ) - + ROUTED M1 ( 34160 13944 ) VIA12SQ_C - NEW M2 ( 34160 13032 ) ( * 13944 ) - NEW M2 ( 34160 13032 ) VIA23SQ_C W - NEW M3 ( 30968 13032 ) ( 34160 * ) - NEW M2 ( 30968 13032 ) VIA23SQ_C W - NEW M2 ( 30968 9536 ) ( * 13032 ) - NEW M2 ( 30968 9536 ) ( 31120 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n25 - ( U0_UART_TX/U0_Serializer/U20 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ D ) - + ROUTED M1 ( 14856 3912 ) VIA12SQ_C ( * 4216 ) VIA23SQ_C W ( 23520 * ) VIA23SQ_C W ( * 4976 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n26 - ( U0_UART_TX/U0_Serializer/U21 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ D ) - + ROUTED M1 ( 15768 7256 ) VIA12SQ_C - NEW M2 ( 15768 6952 ) ( * 7256 ) - NEW M2 ( 15768 6952 ) VIA23SQ_C W ( 22304 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n27 - ( U0_UART_TX/U0_Serializer/U22 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ D ) - + ROUTED M1 ( 16680 8776 ) VIA12SQ_C VIA23SQ_C W ( 21544 * ) VIA23SQ_C W ( * 9232 ) VIA12SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n28 - ( U0_UART_TX/U0_Serializer/U23 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ D ) - + ROUTED M1 ( 25496 7256 ) VIA12SQ_C ( * 8168 ) VIA12SQ_C - NEW M1 ( 25192 8168 ) ( 25496 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n29 - ( U0_UART_TX/U0_Serializer/U24 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ D ) - + ROUTED M1 ( 27776 5128 ) ( 29296 * ) - NEW M1 ( 27776 5128 ) VIA12SQ_C - NEW M2 ( 27776 3912 ) ( * 5128 ) - NEW M1 ( 27776 3912 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n30 - ( U0_UART_TX/U0_Serializer/U25 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ D ) - + ROUTED M1 ( 32792 6800 ) VIA12SQ_C ( * 7256 ) VIA23SQ_C W ( 34616 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n31 - ( U0_UART_TX/U0_Serializer/U26 Y ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ D ) - + ROUTED M1 ( 34082 10600 ) ( 34312 * ) VIA12SQ_C - NEW M2 ( 34312 9536 ) ( * 10600 ) - NEW M1 ( 34312 9536 ) VIA12SQ_C - NEW M1 ( 33248 9536 ) ( 34312 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n15 - ( U0_UART_TX/U0_Serializer/U14 Y ) - ( U0_UART_TX/U0_Serializer/U26 A4 ) - ( U0_UART_TX/U0_Serializer/U25 A4 ) - ( U0_UART_TX/U0_Serializer/U24 A4 ) - ( U0_UART_TX/U0_Serializer/U23 A4 ) - ( U0_UART_TX/U0_Serializer/U22 A4 ) - ( U0_UART_TX/U0_Serializer/U21 A4 ) - ( U0_UART_TX/U0_Serializer/U19 A4 ) - + ROUTED M1 ( 30056 9080 ) VIA12SQ_C W VIA23SQ_C W - NEW M1 ( 23368 6952 ) VIA12SQ_C W ( * 9080 ) VIA23SQ_C W - NEW M3 ( 24128 9080 ) ( 30056 * ) - NEW M1 ( 24128 9080 ) VIA12SQ_C W VIA23SQ_C W - NEW M1 ( 30392 5736 ) ( 30968 * ) VIA12SQ_C ( * 6952 ) VIA23SQ_C W ( 31576 * ) - NEW M1 ( 31576 6952 ) VIA12SQ_C W VIA23SQ_C W - NEW M1 ( 32184 9080 ) VIA12SQ_C W VIA23SQ_C W - NEW M3 ( 31880 9080 ) ( 32184 * ) - NEW M1 ( 33096 7408 ) VIA12SQ_C - NEW M2 ( 33096 6952 ) ( * 7408 ) - NEW M2 ( 33096 6952 ) VIA23SQ_C W - NEW M3 ( 31880 6952 ) ( 33096 * ) - NEW M3 ( 30056 9080 ) ( 31880 * ) - NEW M3 ( 23368 9080 ) ( 24128 * ) - NEW M3 ( 31880 9080 ) VIA34SQ_C - NEW M4 ( 31880 6952 ) ( * 9080 ) - NEW M3 ( 31880 6952 ) VIA34SQ_C - NEW M3 ( 31576 6952 ) ( 31880 * ) - NEW M1 ( 22608 9080 ) VIA12SQ_C W VIA23SQ_C W ( 23368 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n16 - ( U0_UART_TX/U0_Serializer/U15 Y ) - ( U0_UART_TX/U0_Serializer/U26 A2 ) - ( U0_UART_TX/U0_Serializer/U25 A2 ) - ( U0_UART_TX/U0_Serializer/U24 A2 ) - ( U0_UART_TX/U0_Serializer/U23 A2 ) - ( U0_UART_TX/U0_Serializer/U22 A2 ) - ( U0_UART_TX/U0_Serializer/U21 A2 ) - ( U0_UART_TX/U0_Serializer/U20 A4 ) - ( U0_UART_TX/U0_Serializer/U19 A2 ) - + ROUTED M1 ( 29904 8624 ) VIA12SQ_C - NEW M2 ( 29904 8168 ) ( * 8624 ) - NEW M2 ( 29904 8168 ) VIA23SQ_C W ( 32032 * ) VIA23SQ_C W - NEW M1 ( 24128 5280 ) VIA12SQ_C - NEW M2 ( 23976 7864 ) ( * 8447 ) - NEW M1 ( 23976 8624 ) VIA12SQ_C - NEW M1 ( 30512 5280 ) VIA12SQ_C - NEW M1 ( 23976 7864 ) VIA12SQ_C - NEW M1 ( 23520 7864 ) ( 23976 * ) - NEW M1 ( 23520 7408 ) ( * 7864 ) - NEW M1 ( 32032 8624 ) VIA12SQ_C - NEW M2 ( 32032 8168 ) ( * 8624 ) - NEW M1 ( 32336 4105 ) VIA12SQ_C - NEW M2 ( 32184 4105 ) ( 32336 * ) - NEW M2 ( 32184 4105 ) ( * 7256 ) - NEW M2 ( 32032 7256 ) ( 32184 * ) - NEW M2 ( 30512 5432 ) ( * 7256 ) VIA23SQ_C W ( 31424 * ) - NEW M2 ( 24128 5432 ) ( * 6952 ) - NEW M2 ( 23976 6952 ) ( 24128 * ) - NEW M2 ( 23976 6952 ) ( * 7864 ) - NEW M2 ( 30512 5432 ) VIA23SQ_C W - NEW M3 ( 24128 5432 ) ( 30512 * ) - NEW M2 ( 24128 5432 ) VIA23SQ_C W - NEW M3 ( 31424 7256 ) ( 32032 * ) VIA23SQ_C W ( * 8168 ) - NEW M2 ( 31424 7256 ) VIA23SQ_C W - NEW M1 ( 31424 7408 ) VIA12SQ_C - NEW M1 ( 22760 8168 ) ( * 8624 ) - NEW M1 ( 22760 8168 ) ( 23976 * ) - NEW M1 ( 23976 8168 ) ( * 8624 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n17 - ( U0_UART_TX/U0_Serializer/U16 Y ) - ( U0_UART_TX/U0_Serializer/U29 A2 ) - + ROUTED M1 ( 37200 3912 ) ( * 4064 ) - NEW M1 ( 36009 3912 ) ( 37200 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/dftopt10_gOb12 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ SI ) - + ROUTED M1 ( 19264 4493 ) VIA12SQ_C ( * 7256 ) VIA23SQ_C W - NEW M3 ( 16072 7256 ) ( 19264 * ) - NEW M2 ( 16072 7256 ) VIA23SQ_C W - NEW M2 ( 16072 6648 ) ( * 7256 ) - NEW M1 ( 16012 6648 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n34 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ SI ) - + ROUTED M1 ( 25740 6648 ) VIA12SQ_C_1_2 - NEW M2 ( 25800 6648 ) VIA23SQ_C W - NEW M3 ( 20176 6648 ) ( 25800 * ) - NEW M2 ( 20176 6648 ) VIA23SQ_C W - NEW M1 ( 20176 6775 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n35 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ SI ) - + ROUTED M1 ( 15100 3304 ) VIA12SQ_C_1_2 - NEW M2 ( 15160 3304 ) ( * 3912 ) VIA23SQ_C W ( 19720 * ) VIA23SQ_C W ( * 8195 ) - NEW M2 ( 19720 8195 ) ( 20936 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/dftopt8_gOb9 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ SI ) - + ROUTED M1 ( 29904 6800 ) VIA12SQ_C - NEW M2 ( 29904 6952 ) VIA23SQ_C W - NEW M3 ( 27928 6952 ) ( 29904 * ) - NEW M2 ( 27928 6952 ) VIA23SQ_C W - NEW M2 ( 27928 3304 ) ( * 6952 ) - NEW M1 ( 27868 3304 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n37 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ SI ) - + ROUTED M1 ( 32032 4493 ) VIA12SQ_C ( * 6344 ) VIA23SQ_C W ( 34920 * ) VIA23SQ_C W ( * 6648 ) - NEW M1 ( 34860 6648 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/dftopt2_gOb8 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ SI ) - + ROUTED M1 ( 39024 7837 ) VIA12SQ_C ( * 10904 ) VIA23SQ_C W - NEW M3 ( 34160 10904 ) ( 39024 * ) - NEW M2 ( 34160 10904 ) VIA23SQ_C W - NEW M2 ( 34160 9992 ) ( * 10904 ) - NEW M1 ( 34160 9992 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/n39 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ QN ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ SI ) - + ROUTED M1 ( 38446 11176 ) ( 38570 * ) - NEW M1 ( 38446 11181 ) ( 38570 * ) - NEW M1 ( 38568 11181 ) VIA12SQ_C ( * 14248 ) VIA23SQ_C W - NEW M3 ( 34616 14248 ) ( 38568 * ) - NEW M2 ( 34616 14248 ) VIA23SQ_C W - NEW M2 ( 34616 13336 ) ( * 14248 ) - NEW M1 ( 34616 13336 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[7] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ Q ) - ( U0_UART_TX/U0_Serializer/U21 A3 ) - ( U0_UART_TX/U0_Serializer/U20 A1 ) - + ROUTED M1 ( 24432 5432 ) VIA12SQ_C ( * 6040 ) VIA23SQ_C W - NEW M3 ( 23216 6040 ) ( 24432 * ) - NEW M1 ( 23216 7864 ) VIA12SQ_C - NEW M2 ( 23216 6040 ) ( * 7864 ) - NEW M2 ( 23216 6040 ) VIA23SQ_C W - NEW M1 ( 19112 3608 ) VIA12SQ_C ( * 6040 ) VIA23SQ_C W ( 23216 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[6] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ Q ) - ( U0_UART_TX/U0_Serializer/U22 A3 ) - ( U0_UART_TX/U0_Serializer/U21 A5 ) - + ROUTED M1 ( 20061 6952 ) VIA12SQ_C W ( * 7864 ) VIA23SQ_C W ( 22456 * ) VIA23SQ_C W - NEW M1 ( 22608 7256 ) ( 22820 * ) - NEW M1 ( 22608 7256 ) VIA12SQ_C W ( * 7864 ) - NEW M2 ( 22456 7864 ) ( 22608 * ) - NEW M1 ( 22456 8168 ) VIA12SQ_C - NEW M2 ( 22456 7864 ) ( * 8168 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[5] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ Q ) - ( U0_UART_TX/U0_Serializer/U23 A3 ) - ( U0_UART_TX/U0_Serializer/U22 A5 ) - + ROUTED M1 ( 20973 9080 ) VIA12SQ_C W VIA23SQ_C W ( 22152 * ) - NEW M3 ( 22152 8776 ) ( * 9080 ) - NEW M1 ( 22152 8776 ) VIA12SQ_C W VIA23SQ_C W - NEW M1 ( 24280 8168 ) VIA12SQ_C ( * 8776 ) VIA23SQ_C W - NEW M3 ( 22152 8776 ) ( 24280 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[4] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ Q ) - ( U0_UART_TX/U0_Serializer/U24 A3 ) - ( U0_UART_TX/U0_Serializer/U23 A5 ) - + ROUTED M1 ( 29752 6952 ) VIA12SQ_C - NEW M1 ( 29752 4824 ) ( 30130 * ) - NEW M1 ( 29752 4824 ) VIA12SQ_C ( * 6952 ) - NEW M1 ( 24584 8776 ) VIA12SQ_C W - NEW M2 ( 24584 7256 ) ( * 8776 ) - NEW M2 ( 24584 7256 ) VIA23SQ_C W ( 29752 * ) VIA23SQ_C W - NEW M2 ( 29752 6952 ) ( * 7256 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[3] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ Q ) - ( U0_UART_TX/U0_Serializer/U25 A3 ) - ( U0_UART_TX/U0_Serializer/U24 A5 ) - + ROUTED M1 ( 31880 3608 ) VIA12SQ_C - NEW M2 ( 31728 3608 ) ( 31880 * ) - NEW M2 ( 31728 3608 ) ( * 6344 ) - NEW M1 ( 29904 5432 ) VIA12SQ_C W ( * 6344 ) VIA23SQ_C W ( 31728 * ) VIA23SQ_C W - NEW M1 ( 31728 7864 ) VIA12SQ_C - NEW M2 ( 31728 6344 ) ( * 7864 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[2] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ Q ) - ( U0_UART_TX/U0_Serializer/U26 A3 ) - ( U0_UART_TX/U0_Serializer/U25 A5 ) - + ROUTED M1 ( 38872 6952 ) VIA12SQ_C ( * 7560 ) VIA23SQ_C W - NEW M3 ( 32336 7560 ) ( 38872 * ) - NEW M2 ( 32336 7560 ) VIA23SQ_C W - NEW M1 ( 32336 8168 ) VIA12SQ_C - NEW M2 ( 32336 7560 ) ( * 8168 ) - NEW M1 ( 32124 7256 ) ( 32336 * ) VIA12SQ_C W ( * 7560 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/DATA_V[1] - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ Q ) - ( U0_UART_TX/U0_Serializer/U26 A6 ) - ( U0_UART_TX/U0_Serializer/U19 A3 ) - + ROUTED M1 ( 37960 9840 ) VIA12SQ_C W ( 38112 * ) - NEW M2 ( 38112 8776 ) ( * 9840 ) - NEW M2 ( 38112 8776 ) VIA23SQ_C W - NEW M3 ( 32792 8776 ) ( 38112 * ) - NEW M1 ( 30208 8168 ) VIA12SQ_C ( * 8776 ) VIA23SQ_C W ( 32792 * ) - NEW M1 ( 32792 8320 ) VIA12SQ_C W ( * 8776 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/ser_count[2] - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ Q ) - ( U0_UART_TX/U0_Serializer/U30 A1 ) - ( U0_UART_TX/U0_Serializer/U18 A3 ) - + ROUTED M1 ( 45408 20328 ) VIA12SQ_C ( * 20936 ) VIA23SQ_C W - NEW M3 ( 44496 20936 ) ( 45408 * ) - NEW M2 ( 44496 20936 ) VIA23SQ_C W - NEW M1 ( 41486 18808 ) ( 44192 * ) VIA12SQ_C ( * 20936 ) - NEW M2 ( 44192 20936 ) ( 44496 * ) - NEW M1 ( 44496 22304 ) VIA12SQ_C - NEW M2 ( 44496 20936 ) ( * 22304 ) - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/ser_count[1] - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ Q ) - ( U0_UART_TX/U0_Serializer/U31 A2 ) - ( U0_UART_TX/U0_Serializer/U18 A1 ) - + ROUTED M1 ( 40392 23672 ) VIA12SQ_C VIA23SQ_C W ( 41152 * ) - NEW M1 ( 45104 23976 ) VIA12SQ_C - NEW M2 ( 45104 23672 ) ( * 23976 ) - NEW M2 ( 45104 23672 ) VIA23SQ_C W - NEW M3 ( 41152 23672 ) ( 45104 * ) - NEW M1 ( 41152 18808 ) VIA12SQ_C ( * 23672 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_Serializer/ser_count[0] - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ Q ) - ( U0_UART_TX/U0_Serializer/U17 A2 ) - ( U0_UART_TX/U0_Serializer/U31 A3 ) - ( U0_UART_TX/U0_Serializer/U18 A2 ) - + ROUTED M1 ( 39632 20328 ) VIA12SQ_C - NEW M2 ( 39632 19416 ) ( * 20328 ) - NEW M2 ( 39632 19416 ) VIA23SQ_C W ( 41304 * ) VIA23SQ_C W - NEW M2 ( 41304 19112 ) ( * 19416 ) - NEW M1 ( 41304 19112 ) VIA12SQ_C - NEW M1 ( 45256 23672 ) VIA12SQ_C ( * 23976 ) VIA23SQ_C W - NEW M3 ( 43280 23976 ) ( 45256 * ) - NEW M2 ( 43280 23976 ) VIA23SQ_C W - NEW M1 ( 43280 23976 ) VIA12SQ_C - NEW M1 ( 41304 19112 ) ( 43128 * ) VIA12SQ_C ( * 23976 ) - NEW M2 ( 43128 23976 ) ( 43280 * ) - + USE SIGNAL ; - - optlc_net_426 - ( optlc_1045 Y ) - ( U0_UART_TX/U0_mux/U8 A1 ) - + ROUTED M1 ( 42216 15464 ) ( * 15616 ) - NEW M1 ( 41608 15616 ) ( 42216 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_mux/mux_out - ( U0_UART_TX/U0_mux/U6 Y ) - ( U0_UART_TX/U0_mux/OUT_reg D ) - + ROUTED M1 ( 41152 17288 ) VIA12SQ_C - NEW M2 ( 41152 15768 ) ( * 17288 ) - NEW M2 ( 41152 15768 ) VIA23SQ_C W ( 44496 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n4 - ( U0_UART_TX/U0_mux/U8 Y ) - ( U0_UART_TX/U0_mux/U6 A2 ) - + ROUTED M1 ( 45185 15768 ) VIA12SQ_C W ( * 16072 ) VIA23SQ_C W - NEW M3 ( 43128 16072 ) ( 45185 * ) - NEW M2 ( 43128 16072 ) VIA23SQ_C W - NEW M1 ( 43128 16072 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n5 - ( U0_UART_TX/U0_mux/U7 Y ) - ( U0_UART_TX/U0_mux/U6 A3 ) - + ROUTED M1 ( 44952 14856 ) VIA12SQ_C - NEW M2 ( 44952 13336 ) ( * 14856 ) - NEW M2 ( 44952 13336 ) VIA23SQ_C W - NEW M3 ( 42824 13336 ) ( 44952 * ) - NEW M2 ( 42824 13336 ) VIA23SQ_C W - NEW M1 ( 42824 13336 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n2 - ( U0_UART_TX/U0_mux/U5 Y ) - ( U0_UART_TX/U0_mux/U6 A4 ) - + ROUTED M1 ( 45104 15312 ) VIA12SQ_C - NEW M2 ( 44800 15312 ) ( 45104 * ) - NEW M2 ( 44800 14137 ) ( * 15312 ) - NEW M1 ( 44800 14137 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_mux/n3 - ( U0_UART_TX/U0_mux/U4 Y ) - ( U0_UART_TX/U0_mux/U8 A4 ) - ( U0_UART_TX/U0_mux/U7 A4 ) - + ROUTED M1 ( 42520 15312 ) VIA12SQ_C - NEW M2 ( 42216 15312 ) ( 42520 * ) - NEW M2 ( 42216 14248 ) ( * 15312 ) - NEW M1 ( 42216 14096 ) VIA12SQ_C - NEW M1 ( 43736 14137 ) VIA12SQ_C - NEW M2 ( 43736 14248 ) VIA23SQ_C W - NEW M3 ( 42216 14248 ) ( 43736 * ) - NEW M2 ( 42216 14248 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/HFSNET_1 - ( U0_UART_RX/HFSBUF_432_1 Y ) - ( U0_UART_RX/U0_stp_chk/stp_err_reg RSTB ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ RSTB ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ RSTB ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ RSTB ) - ( U0_UART_RX/U0_par_chk/par_err_reg RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ RSTB ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ RSTB ) - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg RSTB ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ RSTB ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ RSTB ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ RSTB ) - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ RSTB ) - + ROUTED M1 ( 42976 27928 ) VIA12SQ_C ( * 28536 ) - NEW M1 ( 30512 28232 ) VIA12SQ_C ( * 28536 ) - NEW M2 ( 30968 39480 ) ( * 41304 ) VIA23SQ_C W ( 31272 * ) - NEW M1 ( 30512 34616 ) VIA12SQ_C ( 30664 * ) - NEW M2 ( 30664 31880 ) ( * 34616 ) - NEW M2 ( 30512 31880 ) ( 30664 * ) - NEW M2 ( 30512 28536 ) ( * 31880 ) - NEW M1 ( 19416 31272 ) VIA12SQ_C - NEW M1 ( 19720 44648 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 18352 27928 ) VIA12SQ_C VIA23SQ_C W ( 19416 * ) - NEW M1 ( 19872 34616 ) VIA12SQ_C - NEW M2 ( 19872 33704 ) ( * 34616 ) - NEW M2 ( 25648 39480 ) ( * 41304 ) - NEW M1 ( 24888 31576 ) VIA12SQ_C ( 25040 * ) - NEW M1 ( 24888 28232 ) VIA12SQ_C ( 25040 * ) - NEW M2 ( 25040 28232 ) ( * 28536 ) - NEW M1 ( 26256 44648 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 25648 44648 ) ( 26256 * ) - NEW M1 ( 25648 41304 ) VIA12SQ_C - NEW M1 ( 33400 38264 ) VIA12SQ_C - NEW M2 ( 33400 37960 ) ( * 38264 ) - NEW M2 ( 33400 37960 ) VIA23SQ_C W - NEW M1 ( 43128 31576 ) VIA12SQ_C - NEW M1 ( 39632 34920 ) VIA12SQ_C ( * 37960 ) VIA23SQ_C W - NEW M1 ( 38416 37960 ) VIA12SQ_C VIA23SQ_C W ( 38568 * ) - NEW M1 ( 43280 38264 ) VIA12SQ_C - NEW M1 ( 43280 44648 ) VIA12SQ_C - NEW M2 ( 43280 41304 ) ( * 44648 ) - NEW M1 ( 43280 41304 ) VIA12SQ_C - NEW M1 ( 31728 44648 ) VIA12SQ_C - NEW M2 ( 31728 41304 ) ( * 44648 ) - NEW M2 ( 31728 41304 ) VIA23SQ_C W - NEW M3 ( 31272 41304 ) ( 31728 * ) - NEW M1 ( 31272 41304 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 31424 37960 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 43280 31272 ) VIA12SQ_C ( * 31576 ) - NEW M2 ( 18808 41304 ) ( 19264 * ) - NEW M1 ( 18808 41304 ) VIA12SQ_C - NEW M2 ( 25040 31576 ) ( * 33704 ) - NEW M2 ( 25040 28536 ) ( * 31576 ) - NEW M2 ( 43280 31576 ) ( * 37960 ) - NEW M2 ( 43128 31576 ) ( 43280 * ) - NEW M2 ( 30968 37960 ) ( * 39480 ) - NEW M2 ( 30968 37960 ) VIA23SQ_C W ( 31424 * ) - NEW M2 ( 25040 35832 ) ( 25192 * ) - NEW M2 ( 25040 33704 ) ( * 35832 ) - NEW M3 ( 38568 37656 ) ( * 37960 ) - NEW M3 ( 34160 37656 ) ( 38568 * ) - NEW M3 ( 34160 37656 ) ( * 37960 ) - NEW M3 ( 33400 37960 ) ( 34160 * ) - NEW M2 ( 25040 28536 ) VIA23SQ_C W ( 30512 * ) VIA23SQ_C W - NEW M3 ( 19264 44648 ) ( 19720 * ) - NEW M2 ( 19264 44648 ) VIA23SQ_C W - NEW M2 ( 19264 41304 ) ( * 44648 ) - NEW M2 ( 42976 28536 ) VIA23SQ_C W - NEW M3 ( 39328 28536 ) ( 42976 * ) - NEW M3 ( 39328 28232 ) ( * 28536 ) - NEW M3 ( 36744 28232 ) ( 39328 * ) - NEW M2 ( 36744 28232 ) VIA23SQ_C W - NEW M2 ( 36744 27928 ) ( * 28232 ) - NEW M1 ( 36744 27928 ) VIA12SQ_C - NEW M2 ( 25648 38568 ) ( * 39480 ) - NEW M2 ( 25192 38568 ) ( 25648 * ) - NEW M2 ( 25192 35832 ) ( * 38568 ) - NEW M2 ( 25648 41304 ) ( * 44648 ) VIA23SQ_C W - NEW M2 ( 19872 33704 ) VIA23SQ_C W ( 25040 * ) VIA23SQ_C W - NEW M2 ( 42976 31576 ) ( 43128 * ) - NEW M2 ( 42976 28536 ) ( * 31576 ) - NEW M3 ( 39632 37960 ) ( 43280 * ) VIA23SQ_C W ( * 38264 ) - NEW M2 ( 19416 27928 ) ( * 31272 ) - NEW M2 ( 19416 27928 ) VIA23SQ_C W - NEW M3 ( 38568 37960 ) ( 39632 * ) - NEW M3 ( 19720 44648 ) ( 25648 * ) - NEW M3 ( 31424 37960 ) ( 33400 * ) - NEW M2 ( 43280 38264 ) ( * 41304 ) - NEW M2 ( 30968 39480 ) VIA23SQ_C W - NEW M3 ( 25648 39480 ) ( 30968 * ) - NEW M2 ( 25648 39480 ) VIA23SQ_C W - NEW M1 ( 19416 37960 ) VIA12SQ_C ( * 41000 ) - NEW M2 ( 19264 41000 ) ( 19416 * ) - NEW M2 ( 19264 41000 ) ( * 41304 ) - NEW M1 ( 20632 6192 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C ( * 27928 ) VIA34SQ_C - NEW M3 ( 19416 27928 ) ( 20632 * ) - NEW M2 ( 25192 34920 ) ( * 35832 ) - NEW M1 ( 25192 34920 ) VIA12SQ_C - NEW M2 ( 19416 31272 ) ( 19872 * ) - NEW M2 ( 19872 31272 ) ( * 33704 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n2 - ( U0_UART_TX/U0_parity_calc/U3 Y ) - ( U0_UART_TX/U0_parity_calc/U2 A4 ) - + ROUTED M1 ( 37808 18656 ) VIA12SQ_C - NEW M2 ( 37808 18200 ) ( * 18656 ) - NEW M2 ( 37808 18200 ) VIA23SQ_C W - NEW M3 ( 32336 18200 ) ( 37808 * ) - NEW M2 ( 32336 18200 ) VIA23SQ_C W - NEW M1 ( 32336 18352 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n3 - ( U0_UART_TX/U0_parity_calc/U6 Y ) - ( U0_UART_TX/U0_parity_calc/U3 A2 ) - + ROUTED M1 ( 34920 18808 ) VIA12SQ_C - NEW M2 ( 34920 16224 ) ( * 18808 ) - NEW M2 ( 34920 16224 ) ( 35376 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n4 - ( U0_UART_TX/U0_parity_calc/U4 Y ) - ( U0_UART_TX/U0_parity_calc/U3 A3 ) - + ROUTED M1 ( 26712 18504 ) VIA12SQ_C VIA23SQ_C W ( 32792 * ) VIA23SQ_C W - NEW M1 ( 32792 18656 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n5 - ( U0_UART_TX/U0_parity_calc/U8 Y ) - ( U0_UART_TX/U0_parity_calc/U4 A3 ) - + ROUTED M1 ( 25947 18651 ) ( 26181 * ) - NEW M1 ( 25947 18692 ) ( 26181 * ) - NEW M1 ( 24280 12880 ) VIA12SQ_C ( * 18504 ) VIA23SQ_C W ( 25952 * ) VIA23SQ_C W - NEW M1 ( 25952 18656 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n8 - ( U0_UART_TX/U0_parity_calc/U10 Y ) - ( U0_UART_TX/U0_parity_calc/U5 A ) - ( U0_UART_TX/U0_parity_calc/U23 A1 ) - ( U0_UART_TX/U0_parity_calc/U21 A1 ) - ( U0_UART_TX/U0_parity_calc/U19 A1 ) - ( U0_UART_TX/U0_parity_calc/U17 A1 ) - ( U0_UART_TX/U0_parity_calc/U15 A1 ) - ( U0_UART_TX/U0_parity_calc/U13 A1 ) - ( U0_UART_TX/U0_parity_calc/U11 A1 ) - ( U0_UART_TX/U0_parity_calc/U9 A1 ) - + ROUTED M1 ( 26256 12120 ) VIA12SQ_C - NEW M2 ( 26104 12120 ) ( 26256 * ) - NEW M1 ( 28688 12120 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 26104 15464 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W VIA34SQ_C ( * 18808 ) VIA34SQ_C ( 27928 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 22152 10600 ) VIA12SQ_C ( * 10904 ) VIA23SQ_C W - NEW M1 ( 24766 15464 ) ( 26079 * ) - NEW M2 ( 26104 10904 ) ( * 12120 ) - NEW M2 ( 26104 10904 ) VIA23SQ_C W - NEW M3 ( 23976 10904 ) ( 26104 * ) - NEW M1 ( 23976 10600 ) VIA12SQ_C ( * 10904 ) VIA23SQ_C W - NEW M3 ( 26104 12120 ) ( 28688 * ) - NEW M2 ( 26104 12120 ) VIA23SQ_C W - NEW M2 ( 26104 12120 ) ( * 13944 ) - NEW M2 ( 26104 13944 ) ( * 15464 ) - NEW M1 ( 21088 12120 ) VIA12SQ_C VIA23SQ_C W ( 22152 * ) VIA34SQ_C - NEW M4 ( 22152 10904 ) ( * 12120 ) - NEW M3 ( 22152 10904 ) VIA34SQ_C - NEW M1 ( 33400 4520 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C ( * 12120 ) VIA45SQ_C W - NEW M5 ( 29144 12120 ) ( 33400 * ) - NEW M4 ( 29144 12120 ) VIA45SQ_C W - NEW M3 ( 29144 12120 ) VIA34SQ_C - NEW M3 ( 28688 12120 ) ( 29144 * ) - NEW M3 ( 22152 10904 ) ( 23976 * ) - NEW M2 ( 26104 13944 ) VIA23SQ_C W - NEW M3 ( 25344 13944 ) ( 26104 * ) - NEW M2 ( 25344 13944 ) VIA23SQ_C W - NEW M1 ( 25344 13944 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n18 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ QN ) - ( U0_UART_TX/U0_parity_calc/U7 A1 ) - + ROUTED M1 ( 30086 11181 ) ( 31120 * ) VIA12SQ_C ( * 11968 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n20 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ QN ) - ( U0_UART_TX/U0_parity_calc/U6 A2 ) - + ROUTED M1 ( 32488 16528 ) ( 32792 * ) VIA12SQ_C - NEW M2 ( 32792 15550 ) ( * 16528 ) - NEW M1 ( 32792 15550 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n22 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ QN ) - ( U0_UART_TX/U0_parity_calc/U8 A1 ) - + ROUTED M1 ( 20784 11181 ) VIA12SQ_C - NEW M2 ( 20784 11208 ) VIA23SQ_C W ( 22912 * ) VIA23SQ_C W ( * 11968 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n23 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ QN ) - ( U0_UART_TX/U0_parity_calc/U8 A2 ) - + ROUTED M1 ( 22304 13184 ) ( 22608 * ) VIA12SQ_C - NEW M2 ( 22608 12120 ) ( * 13184 ) - NEW M1 ( 22608 12120 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n24 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ QN ) - ( U0_UART_TX/U0_parity_calc/U4 A1 ) - + ROUTED M1 ( 26256 17869 ) VIA12SQ_C ( * 19112 ) VIA23SQ_C W - NEW M3 ( 24280 19112 ) ( 26256 * ) - NEW M2 ( 24280 19112 ) VIA23SQ_C W - NEW M2 ( 24280 19112 ) ( * 19568 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n25 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ QN ) - ( U0_UART_TX/U0_parity_calc/U4 A2 ) - + ROUTED M1 ( 23976 18808 ) VIA12SQ_C - NEW M2 ( 23976 16832 ) ( * 18808 ) - NEW M2 ( 23368 16832 ) ( 23976 * ) - NEW M2 ( 23368 16224 ) ( * 16832 ) - NEW M1 ( 23368 16224 ) VIA12SQ_C - NEW M1 ( 23064 16224 ) ( 23368 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n27 - ( U0_UART_TX/U0_parity_calc/U2 Y ) - ( U0_UART_TX/U0_parity_calc/parity_reg D ) - + ROUTED M1 ( 35832 17288 ) VIA12SQ_C ( * 18504 ) VIA23SQ_C W ( 37200 * ) VIA23SQ_C W ( * 19264 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n29 - ( U0_UART_TX/U0_parity_calc/U9 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ D ) - + ROUTED M1 ( 25648 10600 ) VIA12SQ_C - NEW M2 ( 25496 10600 ) ( 25648 * ) - NEW M2 ( 25496 10600 ) ( * 11664 ) - NEW M2 ( 25344 11664 ) ( 25496 * ) - NEW M1 ( 25344 11664 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n31 - ( U0_UART_TX/U0_parity_calc/U11 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ D ) - + ROUTED M1 ( 27928 13944 ) VIA12SQ_C - NEW M2 ( 27928 12880 ) ( * 13944 ) - NEW M2 ( 27776 12880 ) ( 27928 * ) - NEW M1 ( 27776 12880 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n33 - ( U0_UART_TX/U0_parity_calc/U13 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ D ) - + ROUTED M1 ( 28232 17288 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M3 ( 27168 17592 ) ( 28232 * ) - NEW M2 ( 27168 17592 ) VIA23SQ_C W - NEW M2 ( 27168 16224 ) ( * 17592 ) - NEW M1 ( 27168 16224 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n35 - ( U0_UART_TX/U0_parity_calc/U15 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ D ) - + ROUTED M1 ( 28992 20632 ) VIA12SQ_C - NEW M2 ( 28992 19568 ) ( * 20632 ) - NEW M1 ( 28992 19568 ) VIA12SQ_C - NEW M1 ( 28840 19568 ) ( 28992 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n37 - ( U0_UART_TX/U0_parity_calc/U17 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ D ) - + ROUTED M1 ( 16376 10600 ) VIA12SQ_C VIA23SQ_C W ( 23064 * ) VIA23SQ_C W - NEW M2 ( 23064 10144 ) ( * 10600 ) - NEW M1 ( 23064 10144 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n39 - ( U0_UART_TX/U0_parity_calc/U19 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ D ) - + ROUTED M1 ( 18048 13944 ) VIA12SQ_C - NEW M2 ( 18048 12728 ) ( * 13944 ) - NEW M1 ( 18048 12728 ) VIA12SQ_C - NEW M1 ( 18048 12728 ) ( 20176 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n41 - ( U0_UART_TX/U0_parity_calc/U21 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ D ) - + ROUTED M1 ( 22000 17288 ) VIA12SQ_C - NEW M2 ( 22000 15464 ) ( * 17288 ) - NEW M2 ( 22000 15464 ) VIA23SQ_C W ( 23784 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n43 - ( U0_UART_TX/U0_parity_calc/U23 Y ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ D ) - + ROUTED M1 ( 18960 15464 ) VIA12SQ_C - NEW M2 ( 18960 14552 ) ( * 15464 ) - NEW M2 ( 18960 14552 ) VIA23SQ_C W ( 26256 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n1 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ Q ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ SI ) - ( U0_UART_TX/U0_parity_calc/U13 A2 ) - + ROUTED M1 ( 22244 16680 ) VIA12SQ_C_1_2 - NEW M2 ( 22304 16680 ) ( * 17896 ) VIA23SQ_C W ( 25952 * ) - NEW M3 ( 25952 17896 ) ( 32184 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 25952 15768 ) ( 26378 * ) - NEW M1 ( 25952 15768 ) VIA12SQ_C ( * 17896 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n6 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ Q ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ SI ) - ( U0_UART_TX/U0_parity_calc/U19 A2 ) - + ROUTED M1 ( 22304 13640 ) VIA12SQ_C - NEW M2 ( 22304 12424 ) ( * 13640 ) - NEW M2 ( 22304 12424 ) VIA23SQ_C W - NEW M3 ( 20936 12424 ) ( 22304 * ) - NEW M1 ( 16620 9992 ) VIA12SQ_C_1_2 - NEW M2 ( 16680 9992 ) ( * 11664 ) VIA12SQ_C ( 20024 * ) VIA12SQ_C ( * 12424 ) VIA23SQ_C W ( 20936 * ) - NEW M1 ( 20936 12424 ) VIA12SQ_C VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n7 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ Q ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ SI ) - ( U0_UART_TX/U0_parity_calc/U9 A2 ) - + ROUTED M1 ( 26256 12424 ) VIA12SQ_C VIA23SQ_C W ( 28080 * ) VIA23SQ_C W - NEW M1 ( 29904 10296 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 28080 10296 ) ( 29904 * ) - NEW M2 ( 28080 10296 ) VIA23SQ_C W - NEW M2 ( 28080 10296 ) ( * 12424 ) - NEW M2 ( 28080 12424 ) ( * 13336 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n10 - ( U0_UART_TX/U0_parity_calc/U7 Y ) - ( U0_UART_TX/U0_parity_calc/U6 A3 ) - + ROUTED M1 ( 34627 15003 ) ( * 15079 ) - NEW M1 ( 34646 15003 ) ( * 15079 ) - NEW M1 ( 34616 15008 ) VIA12SQ_C - NEW M2 ( 34616 15160 ) VIA23SQ_C W - NEW M3 ( 32640 15160 ) ( 34616 * ) - NEW M2 ( 32640 15160 ) VIA23SQ_C W - NEW M2 ( 32640 12880 ) ( * 15160 ) - NEW M1 ( 32640 12880 ) VIA12SQ_C - NEW M1 ( 32336 12880 ) ( 32640 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n11 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ Q ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ SI ) - ( U0_UART_TX/U0_parity_calc/U23 A2 ) - + ROUTED M1 ( 22760 15008 ) VIA12SQ_C - NEW M2 ( 22000 15008 ) ( 22760 * ) - NEW M2 ( 22000 14248 ) ( * 15008 ) - NEW M2 ( 22000 14248 ) VIA23SQ_C W - NEW M3 ( 18352 14248 ) ( 22000 * ) - NEW M2 ( 18352 14248 ) VIA23SQ_C W - NEW M2 ( 18352 13336 ) ( * 14248 ) - NEW M1 ( 18292 13336 ) VIA12SQ_C_1_2 - NEW M1 ( 23064 15768 ) VIA12SQ_C - NEW M2 ( 23064 13640 ) ( * 15768 ) - NEW M1 ( 23064 13640 ) VIA12SQ_C - NEW M1 ( 23064 13640 ) ( 25466 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n13 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ Q ) - ( U0_UART_TX/U0_parity_calc/U6 A1 ) - ( U0_UART_TX/U0_parity_calc/U15 A2 ) - + ROUTED M1 ( 33248 20328 ) VIA12SQ_C - NEW M2 ( 33248 19112 ) ( * 20328 ) - NEW M2 ( 33096 19112 ) ( 33248 * ) - NEW M1 ( 28151 19112 ) VIA12SQ_C W VIA23SQ_C W ( 33096 * ) VIA23SQ_C W - NEW M1 ( 33096 16224 ) VIA12SQ_C ( * 19112 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n14 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ Q ) - ( U0_UART_TX/U0_parity_calc/U7 A2 ) - ( U0_UART_TX/U0_parity_calc/U11 A2 ) - + ROUTED M1 ( 32184 13640 ) VIA12SQ_C - NEW M2 ( 32184 12120 ) ( * 13640 ) - NEW M2 ( 32184 12120 ) VIA23SQ_C W - NEW M3 ( 30816 12120 ) ( 32184 * ) - NEW M1 ( 28536 12424 ) VIA12SQ_C VIA23SQ_C W ( 30816 * ) - NEW M3 ( 30816 12120 ) ( * 12424 ) - NEW M1 ( 30816 12120 ) VIA12SQ_C VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n15 - ( U0_UART_TX/U0_parity_calc/U5 Y ) - ( U0_UART_TX/U0_parity_calc/U23 A4 ) - ( U0_UART_TX/U0_parity_calc/U21 A4 ) - ( U0_UART_TX/U0_parity_calc/U19 A4 ) - ( U0_UART_TX/U0_parity_calc/U17 A4 ) - ( U0_UART_TX/U0_parity_calc/U15 A4 ) - ( U0_UART_TX/U0_parity_calc/U13 A4 ) - ( U0_UART_TX/U0_parity_calc/U11 A4 ) - ( U0_UART_TX/U0_parity_calc/U9 A4 ) - + ROUTED M3 ( 23672 10600 ) ( 24280 * ) VIA23SQ_C W - NEW M1 ( 24280 10752 ) VIA12SQ_C - NEW M3 ( 25952 11816 ) ( 28536 * ) VIA23SQ_C W - NEW M1 ( 28536 11968 ) VIA12SQ_C - NEW M3 ( 25496 15160 ) ( 26535 * ) - NEW M1 ( 25496 14096 ) VIA12SQ_C - NEW M2 ( 25952 11816 ) VIA23SQ_C W - NEW M1 ( 25952 11968 ) VIA12SQ_C - NEW M3 ( 20784 11816 ) ( 23672 * ) - NEW M2 ( 20784 11816 ) VIA23SQ_C W - NEW M1 ( 20784 11968 ) VIA12SQ_C - NEW M2 ( 26560 15160 ) VIA23SQ_C W - NEW M1 ( 26560 15312 ) VIA12SQ_C - NEW M3 ( 25496 11816 ) ( 25952 * ) - NEW M3 ( 26712 15160 ) VIA34SQ_C ( * 18200 ) VIA34SQ_C ( 28080 * ) VIA23SQ_C W ( * 18656 ) VIA12SQ_C - NEW M2 ( 23672 10600 ) VIA23SQ_C W - NEW M2 ( 23672 10600 ) ( * 11816 ) VIA23SQ_C W ( 25496 * ) - NEW M2 ( 25496 15160 ) VIA23SQ_C W - NEW M2 ( 25496 14096 ) ( * 15160 ) - NEW M2 ( 25496 11816 ) ( * 14096 ) - NEW M2 ( 25496 11816 ) VIA23SQ_C W - NEW M1 ( 22456 10752 ) VIA12SQ_C - NEW M2 ( 22456 10296 ) ( * 10752 ) - NEW M2 ( 22456 10296 ) VIA23SQ_C W ( 23672 * ) - NEW M3 ( 23672 10296 ) ( * 10600 ) - NEW M3 ( 24432 15160 ) ( 25496 * ) - NEW M2 ( 24432 15160 ) VIA23SQ_C W - NEW M1 ( 24432 15312 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n16 - ( U0_UART_TX/U0_parity_calc/U12 Y ) - ( U0_UART_TX/U0_parity_calc/U10 A2 ) - + ROUTED M1 ( 33704 3942 ) ( * 4064 ) - NEW M1 ( 33704 4064 ) ( 34586 * ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n17 - ( U0_UART_TX/U0_parity_calc/U14 Y ) - ( U0_UART_TX/U0_parity_calc/U2 A2 ) - + ROUTED M1 ( 37990 19112 ) ( 39784 * ) - NEW M1 ( 39784 18686 ) ( * 19112 ) - + USE SIGNAL ; - - U0_UART_TX/U0_parity_calc/n28 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ QN ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ SI ) - + ROUTED M1 ( 28688 16680 ) VIA12SQ_C - NEW M2 ( 28688 14248 ) ( * 16680 ) - NEW M2 ( 28688 14248 ) VIA23SQ_C W ( 32366 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/strt_glitch - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg Q ) - ( U0_UART_RX/U0_strt_chk/U2 A3 ) - ( U0_UART_RX/U0_uart_fsm/U54 A1 ) - ( U0_UART_RX/U0_uart_fsm/U35 A ) - + ROUTED M1 ( 34464 34008 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 33248 34008 ) ( 34464 * ) - NEW M2 ( 33248 34008 ) VIA23SQ_C W - NEW M1 ( 33248 32336 ) VIA12SQ_C W ( * 34008 ) - NEW M1 ( 33248 36592 ) VIA12SQ_C W ( 33400 * ) - NEW M2 ( 33400 34920 ) ( * 36592 ) - NEW M1 ( 34160 34920 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 33400 34920 ) ( 34160 * ) - NEW M2 ( 33400 34920 ) VIA23SQ_C W - NEW M2 ( 33248 34008 ) ( * 34920 ) - NEW M2 ( 33248 34920 ) ( 33400 * ) - + USE SIGNAL ; - - U0_UART_RX/strt_chk_en - ( U0_UART_RX/U0_uart_fsm/U27 Y ) - ( U0_UART_RX/U0_strt_chk/U3 A ) - ( U0_UART_RX/U0_strt_chk/U2 A2 ) - + ROUTED M1 ( 34616 35832 ) VIA12SQ_C ( * 36136 ) VIA23SQ_C W - NEW M3 ( 33096 36136 ) ( 34616 * ) - NEW M2 ( 33096 36136 ) VIA23SQ_C W - NEW M2 ( 33096 35528 ) ( * 36136 ) - NEW M1 ( 33096 35528 ) VIA12SQ_C - NEW M1 ( 34920 34201 ) VIA12SQ_C - NEW M2 ( 34920 34312 ) VIA23SQ_C W - NEW M3 ( 33096 34312 ) ( 34920 * ) - NEW M2 ( 33096 34312 ) VIA23SQ_C W - NEW M2 ( 33096 34312 ) ( * 35528 ) - + USE SIGNAL ; - - U0_UART_RX/edge_bit_en - ( U0_UART_RX/U0_uart_fsm/U73 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U14 A ) - ( U0_UART_RX/U0_edge_bit_counter/U28 A4 ) - ( U0_UART_RX/U0_edge_bit_counter/U27 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U26 A3 ) - ( U0_UART_RX/U0_edge_bit_counter/U24 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U17 A1 ) - + ROUTED M1 ( 26221 30512 ) VIA12SQ_C W - NEW M2 ( 26221 30360 ) ( * 30512 ) - NEW M2 ( 26221 30360 ) VIA23SQ_C W VIA34SQ_C VIA45SQ_C W - NEW M5 ( 23672 30360 ) ( 26221 * ) - NEW M4 ( 23672 30360 ) VIA45SQ_C W - NEW M4 ( 23368 30360 ) ( 23672 * ) - NEW M4 ( 23368 27928 ) ( * 30360 ) - NEW M1 ( 21848 22152 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 21240 22152 ) ( 21848 * ) - NEW M4 ( 21240 25800 ) ( * 27016 ) VIA34SQ_C - NEW M1 ( 23824 30816 ) VIA12SQ_C - NEW M2 ( 23824 30360 ) ( * 30816 ) - NEW M2 ( 23824 30360 ) VIA23SQ_C - NEW M3 ( 23672 30360 ) ( 23824 * ) - NEW M3 ( 23672 30360 ) VIA34SQ_C - NEW M4 ( 23368 27016 ) ( * 27928 ) - NEW M3 ( 23368 27016 ) VIA34SQ_C - NEW M3 ( 21392 27016 ) ( 23368 * ) - NEW M1 ( 26560 27168 ) VIA12SQ_C ( * 27928 ) VIA23SQ_C W - NEW M3 ( 23368 27928 ) ( 26560 * ) - NEW M3 ( 23368 27928 ) VIA34SQ_C - NEW M4 ( 21240 22152 ) ( * 25800 ) - NEW M3 ( 21240 22152 ) VIA34SQ_C - NEW M1 ( 21088 25496 ) VIA12SQ_C ( * 25800 ) VIA23SQ_C W - NEW M3 ( 21240 25800 ) VIA34SQ_C - NEW M2 ( 21392 27016 ) VIA23SQ_C W - NEW M1 ( 21392 27168 ) VIA12SQ_C - NEW M3 ( 20328 22152 ) ( 21240 * ) - NEW M2 ( 20328 22152 ) VIA23SQ_C W - NEW M2 ( 20328 20480 ) ( * 22152 ) - NEW M1 ( 20328 20480 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/deser_en - ( U0_UART_RX/U0_uart_fsm/U75 Y ) - ( U0_UART_RX/U0_uart_fsm/U36 A3 ) - ( U0_UART_RX/U0_uart_fsm/U32 A1 ) - ( U0_UART_RX/U0_deserializer/U9 A2 ) - + ROUTED M1 ( 28840 27928 ) VIA12SQ_C ( 29296 * ) - NEW M2 ( 29296 22152 ) ( * 27928 ) - NEW M2 ( 29296 22152 ) VIA23SQ_C W ( 31880 * ) - NEW M1 ( 35832 28232 ) ( 35984 * ) VIA12SQ_C - NEW M2 ( 35984 22152 ) ( * 28232 ) - NEW M2 ( 35832 22152 ) ( 35984 * ) - NEW M1 ( 35832 22152 ) VIA12SQ_C W - NEW M3 ( 31880 22152 ) ( 35832 * ) VIA23SQ_C W - NEW M2 ( 31880 22152 ) VIA23SQ_C W - NEW M1 ( 31880 22304 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/par_chk_en - ( U0_UART_RX/U0_uart_fsm/U28 Y ) - ( U0_UART_RX/U0_par_chk/U9 A ) - ( U0_UART_RX/U0_par_chk/U2 A3 ) - + ROUTED M1 ( 39480 27320 ) VIA12SQ_C ( * 28232 ) - NEW M1 ( 36774 30816 ) ( 39480 * ) VIA12SQ_C - NEW M2 ( 39480 28232 ) ( * 30816 ) - NEW M2 ( 39480 28232 ) VIA23SQ_C W ( 40696 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/stp_chk_en - ( U0_UART_RX/U0_uart_fsm/U43 Y ) - ( U0_UART_RX/U0_uart_fsm/U40 A2 ) - ( U0_UART_RX/U0_stp_chk/U3 A ) - ( U0_UART_RX/U0_stp_chk/U2 A3 ) - + ROUTED M1 ( 31758 23672 ) ( 32792 * ) VIA12SQ_C VIA23SQ_C W ( 35072 * ) VIA23SQ_C W ( * 24888 ) - NEW M1 ( 35072 25344 ) VIA12SQ_C - NEW M2 ( 35072 24888 ) ( * 25344 ) - NEW M1 ( 37808 25496 ) VIA12SQ_C VIA23SQ_C W ( 37960 * ) - NEW M3 ( 37960 25192 ) ( * 25496 ) - NEW M3 ( 37960 24888 ) ( * 25192 ) - NEW M3 ( 35072 24888 ) ( 37960 * ) - NEW M2 ( 35072 24888 ) VIA23SQ_C W - NEW M1 ( 40316 25496 ) VIA12SQ_C - NEW M2 ( 40316 25192 ) ( * 25496 ) - NEW M2 ( 40316 25192 ) VIA23SQ_C W - NEW M3 ( 37960 25192 ) ( 40316 * ) - + USE SIGNAL ; - - U0_UART_RX/dat_samp_en - ( U0_UART_RX/U0_uart_fsm/U78 Y ) - ( U0_UART_RX/U0_data_sampling/U62 A1 ) - ( U0_UART_RX/U0_data_sampling/U61 A2 ) - ( U0_UART_RX/U0_data_sampling/U60 A1 ) - ( U0_UART_RX/U0_data_sampling/U45 A1 ) - ( U0_UART_RX/U0_data_sampling/U36 A1 ) - + ROUTED M1 ( 27168 34616 ) VIA12SQ_C ( * 37352 ) VIA23SQ_C W - NEW M1 ( 25040 37200 ) VIA12SQ_C - NEW M1 ( 25040 39024 ) VIA12SQ_C - NEW M1 ( 27776 37352 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 27168 37352 ) ( 27776 * ) - NEW M2 ( 25040 37352 ) VIA23SQ_C W - NEW M2 ( 25040 37352 ) ( * 38847 ) - NEW M3 ( 25040 37352 ) ( 27168 * ) - NEW M1 ( 23398 37200 ) ( 24280 * ) VIA12SQ_C - NEW M2 ( 24280 37352 ) VIA23SQ_C W ( 25040 * ) - NEW M2 ( 25040 38872 ) VIA23SQ_C W ( 28232 * ) VIA23SQ_C W - NEW M1 ( 28232 39024 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/sampled_bit - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg Q ) - ( U0_UART_RX/U0_stp_chk/U2 A1 ) - ( U0_UART_RX/U0_par_chk/U8 A1 ) - ( U0_UART_RX/U0_strt_chk/U2 A1 ) - ( U0_UART_RX/U0_deserializer/U16 A3 ) - + ROUTED M1 ( 35528 39176 ) VIA12SQ_C - NEW M2 ( 35528 35528 ) ( * 39176 ) - NEW M1 ( 37960 34616 ) VIA12SQ_C - NEW M2 ( 37960 34312 ) ( * 34616 ) - NEW M2 ( 37960 34312 ) VIA23SQ_C W - NEW M3 ( 35528 34312 ) ( 37960 * ) - NEW M2 ( 35528 34312 ) VIA23SQ_C W - NEW M2 ( 35528 34312 ) ( * 35528 ) - NEW M1 ( 37960 28688 ) VIA12SQ_C ( * 34312 ) - NEW M1 ( 38720 25496 ) ( 39754 * ) - NEW M1 ( 38720 25496 ) VIA12SQ_C ( * 28688 ) VIA23SQ_C W - NEW M3 ( 37960 28688 ) ( 38720 * ) - NEW M2 ( 37960 28688 ) VIA23SQ_C W - NEW M2 ( 35072 35528 ) ( 35528 * ) - NEW M1 ( 35072 35528 ) VIA12SQ_C - NEW M1 ( 34768 35528 ) ( 35072 * ) - + USE SIGNAL ; - - HFSNET_1 - ( HFSBUF_223_2 Y ) - ( U0_UART_TX/U0_fsm/busy_reg RSTB ) - ( U0_UART_TX/U0_fsm/current_state_reg_2_ RSTB ) - ( U0_UART_TX/U0_fsm/current_state_reg_1_ RSTB ) - ( U0_UART_TX/U0_fsm/current_state_reg_0_ RSTB ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ RSTB ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ RSTB ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_1_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_2_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_3_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_4_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_6_ RSTB ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_7_ RSTB ) - ( U0_UART_TX/U0_mux/OUT_reg RSTB ) - ( U0_UART_TX/U0_parity_calc/parity_reg RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ RSTB ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ RSTB ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ RSTB ) - + ROUTED M1 ( 43280 4520 ) VIA12SQ_C ( * 7256 ) - NEW M1 ( 43280 7864 ) VIA12SQ_C - NEW M2 ( 43280 7256 ) ( * 7864 ) - NEW M1 ( 37200 11512 ) VIA12SQ_C - NEW M1 ( 38264 4824 ) VIA12SQ_C ( * 7256 ) VIA23SQ_C W - NEW M1 ( 16984 4520 ) VIA12SQ_C ( * 7864 ) VIA23SQ_C W ( 17896 * ) - NEW M1 ( 17896 7864 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 18808 8168 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 18504 8168 ) ( 18808 * ) - NEW M1 ( 27624 7864 ) VIA12SQ_C - NEW M1 ( 30360 17896 ) VIA12SQ_C ( * 18200 ) - NEW M1 ( 36136 11208 ) VIA12SQ_C VIA23SQ_C W - NEW M2 ( 29752 11208 ) ( * 14552 ) - NEW M2 ( 29752 11208 ) VIA23SQ_C W - NEW M1 ( 37504 21240 ) VIA12SQ_C - NEW M2 ( 20936 14856 ) VIA23SQ_C W ( * 15160 ) VIA23SQ_C W ( * 17592 ) VIA23SQ_C W ( 24128 * ) - NEW M1 ( 43280 21240 ) VIA12SQ_C - NEW M1 ( 43280 17896 ) VIA12SQ_C ( * 21240 ) - NEW M1 ( 29752 4520 ) VIA12SQ_C - NEW M2 ( 29752 4216 ) ( * 4520 ) - NEW M2 ( 29752 4216 ) VIA23SQ_C W - NEW M3 ( 27624 4216 ) ( 29752 * ) - NEW M2 ( 27624 4216 ) VIA23SQ_C W - NEW M2 ( 27624 4216 ) ( * 5280 ) - NEW M1 ( 24128 17896 ) VIA12SQ_C - NEW M2 ( 24128 17592 ) ( * 17896 ) - NEW M2 ( 24128 17592 ) VIA23SQ_C W - NEW M1 ( 38264 24584 ) VIA12SQ_C - NEW M2 ( 38264 21240 ) ( * 24584 ) - NEW M2 ( 38264 21240 ) VIA23SQ_C W - NEW M1 ( 18504 11208 ) VIA12SQ_C - NEW M1 ( 31120 21240 ) VIA12SQ_C - NEW M2 ( 31120 20632 ) ( * 21240 ) - NEW M2 ( 31120 20632 ) VIA23SQ_C W - NEW M3 ( 30360 20632 ) ( 31120 * ) - NEW M1 ( 30056 14552 ) VIA12SQ_C - NEW M2 ( 29752 14552 ) ( 30056 * ) - NEW M1 ( 27776 11208 ) VIA12SQ_C - NEW M1 ( 37808 17896 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 37504 17896 ) ( 37808 * ) - NEW M2 ( 37504 17896 ) VIA23SQ_C W - NEW M1 ( 26894 5280 ) ( 27624 * ) VIA12SQ_C - NEW M2 ( 29752 14552 ) ( * 18200 ) VIA12SQ_C ( 30360 * ) VIA12SQ_C - NEW M1 ( 36288 14552 ) VIA12SQ_C - NEW M2 ( 36288 11512 ) ( * 14552 ) - NEW M2 ( 36288 11512 ) VIA23SQ_C W - NEW M3 ( 37200 7256 ) ( 38264 * ) - NEW M2 ( 37200 7256 ) VIA23SQ_C W - NEW M2 ( 37200 7256 ) ( * 7864 ) - NEW M2 ( 27776 11208 ) VIA23SQ_C W ( 29752 * ) - NEW M3 ( 17896 7864 ) ( 18504 * ) - NEW M3 ( 18504 7864 ) ( * 8168 ) - NEW M2 ( 27624 7864 ) ( * 11208 ) - NEW M2 ( 27624 11208 ) ( 27776 * ) - NEW M2 ( 27624 5280 ) ( * 7864 ) - NEW M2 ( 37200 7864 ) ( * 11512 ) - NEW M3 ( 29752 11208 ) ( 36136 * ) - NEW M3 ( 36136 11208 ) ( 36288 * ) - NEW M3 ( 36288 11208 ) ( * 11512 ) - NEW M2 ( 25496 21544 ) ( 25952 * ) - NEW M1 ( 25496 21544 ) VIA12SQ_C - NEW M3 ( 24128 17592 ) ( 25800 * ) VIA23SQ_C W ( * 20632 ) - NEW M2 ( 25800 20632 ) ( 25952 * ) - NEW M2 ( 37504 17896 ) ( * 21240 ) - NEW M3 ( 25952 20632 ) ( 30360 * ) - NEW M2 ( 25952 20632 ) VIA23SQ_C W - NEW M2 ( 25952 20632 ) ( * 21544 ) - NEW M3 ( 36288 11512 ) ( 37200 * ) VIA23SQ_C W - NEW M3 ( 37504 21240 ) ( 38264 * ) - NEW M2 ( 37504 21240 ) VIA23SQ_C W - NEW M2 ( 30360 18200 ) ( * 20632 ) VIA23SQ_C W - NEW M2 ( 19872 14552 ) ( 20176 * ) - NEW M2 ( 19872 11208 ) ( * 14552 ) - NEW M2 ( 19872 11208 ) VIA23SQ_C W - NEW M3 ( 18504 11208 ) ( 19872 * ) - NEW M2 ( 18504 11208 ) VIA23SQ_C W - NEW M2 ( 43280 21240 ) VIA23SQ_C W - NEW M3 ( 38264 21240 ) ( 43280 * ) - NEW M2 ( 18504 8168 ) ( * 11208 ) - NEW M2 ( 18504 8168 ) VIA23SQ_C W - NEW M2 ( 36744 7864 ) ( 37200 * ) - NEW M1 ( 36744 7864 ) VIA12SQ_C - NEW M1 ( 26104 24584 ) VIA12SQ_C - NEW M2 ( 25952 24584 ) ( 26104 * ) - NEW M2 ( 25952 21544 ) ( * 24584 ) - NEW M3 ( 38264 7256 ) ( 43280 * ) VIA23SQ_C W - NEW M2 ( 37352 17896 ) ( 37504 * ) - NEW M2 ( 37352 11512 ) ( * 17896 ) - NEW M2 ( 37200 11512 ) ( 37352 * ) - NEW M1 ( 20176 14552 ) VIA12SQ_C - NEW M1 ( 20936 14856 ) VIA12SQ_C - NEW M2 ( 20176 14552 ) ( 20936 * ) - NEW M2 ( 20936 14552 ) ( * 14856 ) - + USE SIGNAL ; - - U0_UART_RX/n4 - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg QN ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ SI ) - + ROUTED M1 ( 33552 36896 ) VIA12SQ_C - NEW M2 ( 33552 37048 ) VIA23SQ_C W VIA34SQ_C VIA45SQ_C W - NEW M5 ( 26408 37048 ) ( 33552 * ) - NEW M4 ( 26408 37048 ) VIA45SQ_C W - NEW M4 ( 26408 37048 ) ( * 37960 ) VIA34SQ_C - NEW M3 ( 23824 37960 ) ( 26408 * ) - NEW M2 ( 23824 37960 ) VIA23SQ_C W - NEW M2 ( 23824 37960 ) ( * 40088 ) - NEW M1 ( 23764 40088 ) VIA12SQ_C_1_2 - NEW M1 ( 33552 36866 ) ( 33666 * ) - NEW M1 ( 33552 36901 ) ( 33666 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt9_gOb6 - ( U0_UART_RX/U0_par_chk/par_err_reg QN ) - ( U0_UART_RX/U0_stp_chk/stp_err_reg SI ) - + ROUTED M1 ( 45560 30208 ) VIA12SQ_C ( * 30664 ) VIA23SQ_C W - NEW M3 ( 41304 30664 ) ( 45560 * ) - NEW M2 ( 41304 30664 ) VIA23SQ_C W - NEW M2 ( 41304 26712 ) ( * 30664 ) - NEW M1 ( 41304 26712 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/n7 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ QN ) - ( U0_UART_RX/U0_par_chk/par_err_reg SI ) - + ROUTED M1 ( 45408 31603 ) VIA12SQ_C - NEW M2 ( 45408 31272 ) ( * 31603 ) - NEW M2 ( 45408 31272 ) VIA23SQ_C W - NEW M3 ( 41608 31272 ) ( 45408 * ) - NEW M2 ( 41608 31272 ) VIA23SQ_C W - NEW M2 ( 41608 30056 ) ( * 31272 ) - NEW M1 ( 41608 30056 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/n8 - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ SI ) - + ROUTED M1 ( 35710 38720 ) ( 35984 * ) VIA12SQ_C ( 36440 * ) - NEW M2 ( 36440 36896 ) ( * 38720 ) - NEW M1 ( 36440 36896 ) VIA12SQ_C - NEW M1 ( 36438 36891 ) ( 36592 * ) - NEW M1 ( 36438 36896 ) ( 36592 * ) - + USE SIGNAL ; - - U0_UART_RX/bit_count[3] - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ Q ) - ( U0_UART_RX/U0_uart_fsm/U40 A1 ) - ( U0_UART_RX/U0_uart_fsm/U58 A3 ) - ( U0_UART_RX/U0_uart_fsm/U57 A ) - ( U0_UART_RX/U0_uart_fsm/U30 A1 ) - + ROUTED M1 ( 32488 25496 ) VIA12SQ_C - NEW M2 ( 32488 25192 ) ( * 25496 ) - NEW M2 ( 32488 25192 ) VIA23SQ_C W - NEW M3 ( 31576 25192 ) ( 32488 * ) - NEW M1 ( 31576 23976 ) VIA12SQ_C ( * 25192 ) VIA23SQ_C W - NEW M2 ( 30512 25192 ) ( * 25648 ) VIA12SQ_C - NEW M3 ( 30512 25192 ) ( 31576 * ) - NEW M2 ( 30512 25192 ) VIA23SQ_C W - NEW M1 ( 27661 22456 ) VIA12SQ_C W ( * 22760 ) VIA23SQ_C W ( 30512 * ) VIA23SQ_C W ( * 25192 ) - NEW M1 ( 30512 25496 ) ( * 25648 ) - NEW M1 ( 30512 25496 ) ( 31120 * ) - + USE SIGNAL ; - - U0_UART_RX/bit_count[2] - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U23 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U22 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U20 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U17 A4 ) - ( U0_UART_RX/U0_uart_fsm/U67 A ) - + ROUTED M1 ( 28232 23672 ) VIA12SQ_C ( * 24280 ) VIA23SQ_C W - NEW M3 ( 23824 24280 ) ( 28232 * ) - NEW M2 ( 23824 24280 ) VIA23SQ_C W - NEW M2 ( 20784 23672 ) VIA23SQ_C W - NEW M1 ( 23824 25496 ) VIA12SQ_C - NEW M1 ( 20784 20632 ) VIA12SQ_C ( * 23672 ) - NEW M1 ( 18656 23976 ) VIA12SQ_C - NEW M2 ( 18656 23672 ) ( * 23976 ) - NEW M2 ( 18656 23672 ) VIA23SQ_C W ( 20784 * ) - NEW M1 ( 25952 25369 ) VIA12BAR_C - NEW M2 ( 25952 25496 ) VIA23SQ_C W - NEW M3 ( 23824 25496 ) ( 25952 * ) - NEW M2 ( 23824 25496 ) VIA23SQ_C W - NEW M2 ( 23824 24280 ) ( * 25496 ) - NEW M2 ( 23824 23672 ) ( * 24280 ) - NEW M2 ( 23824 23672 ) VIA23SQ_C W - NEW M3 ( 20784 23672 ) ( 23824 * ) - NEW M2 ( 20784 23672 ) ( * 23976 ) VIA12SQ_C - NEW M1 ( 20390 23976 ) ( 20784 * ) - + USE SIGNAL ; - - U0_UART_RX/bit_count[1] - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U25 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U21 A1 ) - ( U0_UART_RX/U0_uart_fsm/U68 A ) - ( U0_UART_RX/U0_uart_fsm/U52 A1 ) - ( U0_UART_RX/U0_uart_fsm/U41 A1 ) - + ROUTED M3 ( 20024 25496 ) ( 21848 * ) VIA23SQ_C W - NEW M1 ( 18960 25496 ) VIA12SQ_C VIA23SQ_C W ( 20024 * ) - NEW M1 ( 22000 23672 ) VIA12SQ_C W ( * 25496 ) - NEW M2 ( 21848 25496 ) ( 22000 * ) - NEW M1 ( 24280 27320 ) VIA12SQ_C - NEW M2 ( 24280 26712 ) ( * 27320 ) - NEW M2 ( 24280 26712 ) VIA23SQ_C W - NEW M2 ( 27016 26712 ) VIA23SQ_C W - NEW M3 ( 24280 26712 ) ( 27016 * ) - NEW M1 ( 28840 22000 ) VIA12SQ_C ( * 22456 ) VIA23SQ_C W - NEW M3 ( 27016 22456 ) ( 28840 * ) - NEW M2 ( 27016 22456 ) VIA23SQ_C W - NEW M2 ( 27016 22456 ) ( * 26712 ) - NEW M1 ( 27016 29144 ) VIA12SQ_C - NEW M2 ( 27016 26712 ) ( * 29144 ) - NEW M2 ( 21848 25496 ) ( * 26712 ) VIA23SQ_C W ( 24280 * ) - NEW M2 ( 20024 25496 ) VIA23SQ_C W - NEW M1 ( 20024 25648 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/bit_count[0] - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U28 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U26 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U21 A2 ) - ( U0_UART_RX/U0_uart_fsm/U59 A ) - ( U0_UART_RX/U0_uart_fsm/U52 A2 ) - ( U0_UART_RX/U0_uart_fsm/U41 A2 ) - + ROUTED M1 ( 21848 23976 ) VIA12SQ_C W - NEW M2 ( 21392 23976 ) ( 21848 * ) - NEW M2 ( 21392 23976 ) ( * 25496 ) - NEW M3 ( 21392 26104 ) ( 23976 * ) - NEW M1 ( 20328 25496 ) VIA12SQ_C ( * 26104 ) VIA23SQ_C W ( 21392 * ) - NEW M1 ( 27016 32488 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 25192 32488 ) ( 27016 * ) - NEW M3 ( 25192 32488 ) VIA34SQ_C - NEW M4 ( 25192 31576 ) ( * 32488 ) - NEW M4 ( 25192 31576 ) VIA45SQ_C W - NEW M5 ( 23976 31576 ) ( 25192 * ) - NEW M4 ( 23976 31576 ) VIA45SQ_C W - NEW M4 ( 23976 30360 ) ( * 31576 ) - NEW M3 ( 23976 26104 ) ( 29144 * ) - NEW M3 ( 29144 25496 ) ( * 26104 ) - NEW M1 ( 21392 25496 ) VIA12SQ_C - NEW M1 ( 23976 30360 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C - NEW M1 ( 29904 22456 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 29144 22456 ) ( 29904 * ) - NEW M3 ( 29144 22456 ) VIA34SQ_C ( * 25496 ) VIA34SQ_C - NEW M3 ( 23976 26104 ) VIA34SQ_C ( * 30360 ) - NEW M2 ( 21392 26104 ) VIA23SQ_C W - NEW M2 ( 21392 25496 ) ( * 26104 ) - NEW M1 ( 28992 25496 ) VIA12SQ_C VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/edge_count[5] - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U54 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U49 A2 ) - ( U0_UART_RX/U0_deserializer/U39 A2 ) - ( U0_UART_RX/U0_data_sampling/U51 A ) - ( U0_UART_RX/U0_uart_fsm/U69 A1 ) - ( U0_UART_RX/U0_uart_fsm/U51 A1 ) - + ROUTED M1 ( 14096 44040 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 21848 43736 ) VIA12SQ_C ( * 44040 ) VIA23SQ_C W - NEW M3 ( 14248 44040 ) ( 21848 * ) - NEW M1 ( 14096 22000 ) VIA12SQ_C - NEW M2 ( 14096 21848 ) VIA23SQ_C W - NEW M3 ( 14248 21848 ) VIA34SQ_C - NEW M1 ( 14856 38872 ) VIA12SQ_C ( * 39176 ) VIA23SQ_C W - NEW M3 ( 14248 39176 ) ( 14856 * ) - NEW M3 ( 14248 39176 ) VIA34SQ_C - NEW M1 ( 15160 12120 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 14248 12120 ) ( 15160 * ) - NEW M3 ( 14248 12120 ) VIA34SQ_C - NEW M4 ( 14248 13944 ) ( * 21848 ) - NEW M4 ( 14248 21848 ) ( * 39176 ) - NEW M4 ( 14248 12120 ) ( * 13944 ) - NEW M3 ( 14248 44040 ) VIA34SQ_C - NEW M4 ( 14248 39176 ) ( * 44040 ) - NEW M1 ( 13792 8624 ) VIA12SQ_C - NEW M2 ( 13792 8776 ) VIA23SQ_C W ( 14248 * ) VIA34SQ_C ( * 12120 ) - NEW M3 ( 14248 13944 ) VIA34SQ_C - NEW M2 ( 14400 13944 ) VIA23SQ_C W - NEW M1 ( 14400 13944 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/edge_count[4] - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U52 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_4 A0 ) - ( U0_UART_RX/U0_deserializer/U37 A2 ) - ( U0_UART_RX/U0_data_sampling/U59 A ) - ( U0_UART_RX/U0_data_sampling/U33 A1 ) - ( U0_UART_RX/U0_uart_fsm/U63 A1 ) - ( U0_UART_RX/U0_uart_fsm/U49 A1 ) - + ROUTED M4 ( 9992 5128 ) ( * 12120 ) - NEW M3 ( 9992 5128 ) VIA34SQ_C - NEW M1 ( 11360 22000 ) VIA12SQ_C - NEW M1 ( 20936 40392 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 13640 40392 ) ( 20936 * ) - NEW M3 ( 13640 40392 ) ( * 40696 ) - NEW M1 ( 13792 40696 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 13640 40696 ) ( 13792 * ) - NEW M1 ( 9992 5432 ) VIA12SQ_C - NEW M2 ( 9992 5128 ) ( * 5432 ) - NEW M2 ( 9992 5128 ) VIA23SQ_C W - NEW M1 ( 12880 40696 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 9992 5128 ) ( 12880 * ) VIA23SQ_C W - NEW M1 ( 12880 5280 ) VIA12SQ_C - NEW M3 ( 12880 40696 ) ( 13640 * ) - NEW M4 ( 9992 12120 ) ( * 21544 ) VIA34SQ_C ( 11360 * ) VIA23SQ_C W ( * 21823 ) - NEW M4 ( 12120 28536 ) ( * 40696 ) VIA34SQ_C ( 12880 * ) - NEW M4 ( 12120 21848 ) ( * 28536 ) - NEW M3 ( 12120 21848 ) VIA34SQ_C - NEW M3 ( 11360 21848 ) ( 12120 * ) - NEW M2 ( 11360 21848 ) VIA23SQ_C W - NEW M1 ( 9840 12120 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 9992 12120 ) VIA34SQ_C - NEW M3 ( 12120 28536 ) VIA34SQ_C - NEW M2 ( 12120 28536 ) VIA23SQ_C W - NEW M1 ( 12120 28688 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/edge_count[3] - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U50 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_3 A0 ) - ( U0_UART_RX/U0_deserializer/U35 A2 ) - ( U0_UART_RX/U0_data_sampling/U53 A ) - ( U0_UART_RX/U0_data_sampling/U32 A1 ) - ( U0_UART_RX/U0_uart_fsm/U62 A1 ) - ( U0_UART_RX/U0_uart_fsm/U48 A1 ) - + ROUTED M3 ( 9384 8472 ) ( 10904 * ) - NEW M3 ( 9384 8472 ) VIA34SQ_C ( * 13944 ) - NEW M1 ( 21544 37048 ) VIA12SQ_C ( * 37352 ) VIA23SQ_C W - NEW M3 ( 14552 37352 ) ( 21544 * ) - NEW M2 ( 14552 37352 ) VIA23SQ_C W - NEW M1 ( 14552 37352 ) VIA12SQ_C - NEW M1 ( 10904 8776 ) VIA12SQ_C - NEW M2 ( 10904 8472 ) ( * 8776 ) - NEW M2 ( 10904 8472 ) VIA23SQ_C W - NEW M1 ( 9232 24128 ) VIA12SQ_C - NEW M2 ( 9232 24280 ) VIA23SQ_C W - NEW M3 ( 9384 24280 ) VIA34SQ_C - NEW M1 ( 9688 35528 ) VIA12SQ_C - NEW M2 ( 9688 35224 ) ( * 35528 ) - NEW M2 ( 9688 35224 ) VIA23SQ_C W - NEW M1 ( 8776 13944 ) VIA12SQ_C VIA23SQ_C W ( 9384 * ) VIA34SQ_C - NEW M1 ( 11968 7408 ) VIA12SQ_C ( * 8472 ) VIA23SQ_C W - NEW M3 ( 10904 8472 ) ( 11968 * ) - NEW M3 ( 9688 35224 ) ( 14552 * ) VIA23SQ_C W ( * 37352 ) - NEW M4 ( 9384 30968 ) ( * 35224 ) VIA34SQ_C ( 9688 * ) - NEW M4 ( 9384 24280 ) ( * 30968 ) - NEW M4 ( 9384 13944 ) ( * 24280 ) - NEW M1 ( 10904 30816 ) VIA12SQ_C - NEW M2 ( 10904 30968 ) VIA23SQ_C W - NEW M3 ( 9384 30968 ) ( 10904 * ) - NEW M3 ( 9384 30968 ) VIA34SQ_C - + USE SIGNAL ; - - U0_UART_RX/edge_count[2] - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U51 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_2 A0 ) - ( U0_UART_RX/U0_deserializer/U36 A2 ) - ( U0_UART_RX/U0_data_sampling/U50 A ) - ( U0_UART_RX/U0_data_sampling/U29 A2 ) - ( U0_UART_RX/U0_uart_fsm/U70 A1 ) - ( U0_UART_RX/U0_uart_fsm/U50 A1 ) - + ROUTED M1 ( 10600 20784 ) VIA12SQ_C - NEW M1 ( 9840 25344 ) VIA12SQ_C - NEW M2 ( 9840 25192 ) ( * 25344 ) - NEW M2 ( 9840 25192 ) ( 9992 * ) VIA23SQ_C W - NEW M1 ( 22000 33704 ) VIA12SQ_C ( * 34008 ) VIA23SQ_C W - NEW M3 ( 15008 34008 ) ( 22000 * ) - NEW M1 ( 15008 34008 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 11512 13944 ) VIA12SQ_C ( * 15160 ) VIA23SQ_C W - NEW M3 ( 10904 15160 ) ( 11512 * ) - NEW M2 ( 10904 15160 ) VIA23SQ_C W - NEW M1 ( 9840 34008 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 10904 15464 ) VIA12SQ_C - NEW M2 ( 10904 15160 ) ( * 15464 ) - NEW M2 ( 10600 20024 ) ( * 20784 ) - NEW M2 ( 10600 20024 ) ( 10752 * ) - NEW M2 ( 10752 15160 ) ( * 20024 ) - NEW M2 ( 10752 15160 ) ( 10904 * ) - NEW M4 ( 9992 25192 ) ( * 34008 ) - NEW M3 ( 9992 25192 ) VIA34SQ_C - NEW M3 ( 9992 34008 ) VIA34SQ_C - NEW M3 ( 9992 34008 ) ( 15008 * ) - NEW M2 ( 10600 20784 ) ( 10752 * ) - NEW M2 ( 10752 20784 ) ( * 25192 ) VIA23SQ_C W - NEW M3 ( 9992 25192 ) ( 10752 * ) - NEW M1 ( 9536 37352 ) VIA12SQ_C VIA23SQ_C W ( 9992 * ) VIA34SQ_C - NEW M4 ( 9992 34008 ) ( * 37352 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[1] - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U58 A3 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_1 A0 ) - ( U0_UART_RX/U0_deserializer/U43 A3 ) - ( U0_UART_RX/U0_deserializer/U11 A ) - ( U0_UART_RX/U0_data_sampling/U57 A ) - ( U0_UART_RX/U0_data_sampling/U35 A1 ) - ( U0_UART_RX/U0_uart_fsm/U65 A1 ) - ( U0_UART_RX/U0_uart_fsm/U46 A1 ) - + ROUTED M1 ( 12424 25344 ) VIA12SQ_C ( * 27624 ) VIA23SQ_C W ( 13615 * ) - NEW M4 ( 13640 27624 ) VIA45SQ_C W - NEW M5 ( 13640 27320 ) ( * 27624 ) - NEW M5 ( 13640 27320 ) ( 16376 * ) VIA45SQ_C W ( * 27624 ) VIA34SQ_C ( 20176 * ) VIA23SQ_C W - NEW M1 ( 20176 27776 ) VIA12SQ_C - NEW M1 ( 14400 32184 ) VIA12SQ_C - NEW M2 ( 14400 31880 ) ( * 32184 ) - NEW M2 ( 14400 31880 ) VIA23SQ_C W - NEW M3 ( 13640 31880 ) ( 14400 * ) - NEW M1 ( 16528 16984 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M3 ( 14704 17592 ) ( 16528 * ) - NEW M1 ( 7712 34008 ) VIA12SQ_C - NEW M2 ( 7712 31880 ) ( * 34008 ) - NEW M2 ( 7712 31880 ) VIA23SQ_C W ( 8320 * ) VIA23SQ_C W - NEW M1 ( 8320 32032 ) VIA12SQ_C - NEW M1 ( 14704 16984 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M3 ( 8320 31880 ) ( 13640 * ) - NEW M3 ( 13640 27624 ) VIA34SQ_C - NEW M3 ( 13792 17592 ) ( 14704 * ) - NEW M1 ( 13792 17288 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M3 ( 13640 17592 ) VIA34SQ_C ( * 27624 ) - NEW M1 ( 13792 27472 ) VIA12SQ_C - NEW M2 ( 13792 27624 ) VIA23SQ_C W - NEW M3 ( 13640 31880 ) VIA34SQ_C - NEW M4 ( 13640 27624 ) ( * 31880 ) - + USE SIGNAL ; - - U0_UART_RX/edge_count[0] - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ Q ) - ( U0_UART_RX/U0_edge_bit_counter/U57 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U55 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_1 B0 ) - ( U0_UART_RX/U0_deserializer/U42 A1 ) - ( U0_UART_RX/U0_deserializer/U40 A2 ) - ( U0_UART_RX/U0_data_sampling/U55 A ) - ( U0_UART_RX/U0_data_sampling/U34 A1 ) - ( U0_UART_RX/U0_uart_fsm/U64 A1 ) - ( U0_UART_RX/U0_uart_fsm/U42 A1 ) - + ROUTED M1 ( 16832 22000 ) VIA12SQ_C ( * 22456 ) VIA23SQ_C W - NEW M3 ( 14552 22456 ) ( 16832 * ) - NEW M2 ( 14552 22456 ) VIA23SQ_C W - NEW M1 ( 14400 24128 ) VIA12SQ_C - NEW M1 ( 21544 30360 ) VIA12SQ_C ( * 30664 ) VIA23SQ_C W - NEW M3 ( 15160 30664 ) ( 21544 * ) - NEW M1 ( 14856 32032 ) VIA12SQ_C ( 15312 * ) - NEW M2 ( 15312 30816 ) ( * 32032 ) - NEW M1 ( 18200 18631 ) VIA12BAR_C ( * 19112 ) VIA23SQ_C W - NEW M3 ( 16072 19112 ) ( 18200 * ) - NEW M1 ( 16072 18960 ) VIA12SQ_C - NEW M2 ( 16072 19112 ) VIA23SQ_C W - NEW M1 ( 15312 30816 ) VIA12SQ_C - NEW M1 ( 13488 30664 ) VIA12SQ_C - NEW M2 ( 13488 30360 ) ( * 30664 ) - NEW M2 ( 13488 30360 ) VIA23SQ_C W ( 14400 * ) - NEW M2 ( 14552 19112 ) VIA23SQ_C W - NEW M2 ( 14552 19112 ) ( * 22456 ) - NEW M1 ( 13488 18631 ) VIA12BAR_C ( * 19112 ) VIA23SQ_C W ( 14552 * ) - NEW M2 ( 14400 22456 ) ( * 24128 ) - NEW M2 ( 14400 22456 ) ( 14552 * ) - NEW M2 ( 14400 24128 ) ( * 30360 ) VIA23SQ_C W - NEW M1 ( 15190 18960 ) ( 16072 * ) - NEW M3 ( 14552 19112 ) ( 16072 * ) - NEW M2 ( 15312 30664 ) ( * 30816 ) - NEW M2 ( 15160 30664 ) ( 15312 * ) - NEW M2 ( 15160 30664 ) VIA23SQ_C W - NEW M3 ( 14400 30360 ) ( * 30664 ) - NEW M3 ( 14400 30664 ) ( 15160 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_5_ - ( U0_UART_RX/U0_uart_fsm/U10 Y ) - ( U0_UART_RX/U0_uart_fsm/U51 A2 ) - + ROUTED M1 ( 13488 8776 ) VIA12SQ_C ( * 10296 ) VIA23SQ_C W - NEW M3 ( 7560 10296 ) ( 13488 * ) - NEW M2 ( 7560 10296 ) VIA23SQ_C W - NEW M1 ( 7560 10423 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_4_ - ( U0_UART_RX/U0_uart_fsm/U12 Y ) - ( U0_UART_RX/U0_uart_fsm/U49 A2 ) - + ROUTED M1 ( 12576 5432 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 6800 5432 ) ( 12576 * ) - NEW M2 ( 6800 5432 ) VIA23SQ_C W - NEW M1 ( 6800 5584 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_3_ - ( U0_UART_RX/U0_uart_fsm/U14 Y ) - ( U0_UART_RX/U0_uart_fsm/U48 A2 ) - + ROUTED M1 ( 11664 7256 ) VIA12SQ_C W - NEW M2 ( 11512 7256 ) ( 11664 * ) - NEW M2 ( 11512 6952 ) ( * 7256 ) - NEW M2 ( 11512 6952 ) VIA23SQ_C W - NEW M3 ( 6800 6952 ) ( 11512 * ) - NEW M2 ( 6800 6952 ) VIA23SQ_C W - NEW M1 ( 6800 6952 ) VIA12SQ_C - NEW M1 ( 5736 6952 ) ( 6800 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_2_ - ( U0_UART_RX/U0_uart_fsm/U16 Y ) - ( U0_UART_RX/U0_uart_fsm/U50 A2 ) - + ROUTED M1 ( 10296 20632 ) VIA12SQ_C - NEW M2 ( 10296 20480 ) ( * 20632 ) - NEW M2 ( 9688 20480 ) ( 10296 * ) - NEW M1 ( 9688 20480 ) VIA12SQ_C - NEW M1 ( 9232 20480 ) ( 9688 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/error_check_edge_1_ - ( U0_UART_RX/U0_uart_fsm/U9 Y ) - ( U0_UART_RX/U0_uart_fsm/U46 A2 ) - + ROUTED M1 ( 13488 27320 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 11360 27320 ) ( 13488 * ) - NEW M2 ( 11360 27320 ) VIA23SQ_C W - NEW M1 ( 11360 27472 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n18 - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ QN ) - ( U0_UART_RX/U0_uart_fsm/U79 A1 ) - ( U0_UART_RX/U0_uart_fsm/U74 A1 ) - + ROUTED M1 ( 30968 30360 ) VIA12SQ_C W ( * 30968 ) - NEW M1 ( 29296 30512 ) VIA12SQ_C ( * 30968 ) VIA23SQ_C W ( 30968 * ) VIA23SQ_C W ( 32640 * ) - NEW M2 ( 32640 29600 ) ( * 30968 ) - NEW M1 ( 32640 29600 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n1 - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ Q ) - ( U0_UART_RX/U0_uart_fsm/U79 A3 ) - ( U0_UART_RX/U0_uart_fsm/U77 A3 ) - ( U0_UART_RX/U0_uart_fsm/U44 A2 ) - + ROUTED M1 ( 38872 27016 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 37200 27016 ) ( 38872 * ) - NEW M2 ( 37200 27016 ) VIA23SQ_C W - NEW M1 ( 37200 25496 ) VIA12SQ_C W ( * 27016 ) - NEW M1 ( 28992 31272 ) VIA12SQ_C - NEW M2 ( 28992 28840 ) ( * 31272 ) - NEW M2 ( 28992 28840 ) VIA23SQ_C W ( 33248 * ) - NEW M3 ( 33248 28536 ) ( * 28840 ) - NEW M3 ( 33248 28536 ) ( 37200 * ) VIA23SQ_C W - NEW M2 ( 37200 27016 ) ( * 28536 ) - NEW M2 ( 33248 28840 ) VIA23SQ_C W - NEW M1 ( 33248 28992 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n2 - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ Q ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ SI ) - ( U0_UART_RX/U0_uart_fsm/U77 A2 ) - ( U0_UART_RX/U0_uart_fsm/U75 A2 ) - ( U0_UART_RX/U0_uart_fsm/U56 A4 ) - + ROUTED M1 ( 32640 29144 ) VIA12SQ_C - NEW M1 ( 34768 29144 ) ( 35194 * ) - NEW M1 ( 34768 29144 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 33552 29144 ) ( 34768 * ) - NEW M3 ( 32640 29144 ) ( 33552 * ) - NEW M1 ( 32184 27320 ) VIA12SQ_C ( * 28232 ) VIA23SQ_C W ( 32640 * ) VIA23SQ_C W ( * 29144 ) VIA23SQ_C W - NEW M1 ( 33552 28992 ) VIA12SQ_C - NEW M2 ( 33552 29144 ) VIA23SQ_C W - NEW M1 ( 28720 33400 ) ( 28992 * ) VIA12SQ_C VIA23SQ_C W ( 32488 * ) VIA34SQ_C - NEW M4 ( 32488 29144 ) ( * 33400 ) - NEW M3 ( 32488 29144 ) VIA34SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n3 - ( U0_UART_RX/U0_uart_fsm/U18 Y ) - ( U0_UART_RX/U0_uart_fsm/U21 A2 ) - ( U0_UART_RX/U0_uart_fsm/U20 A1 ) - ( U0_UART_RX/U0_uart_fsm/U4 A ) - + ROUTED M1 ( 7256 23976 ) VIA12SQ_C ( * 24280 ) VIA23SQ_C W - NEW M3 ( 5888 24280 ) ( 7256 * ) - NEW M1 ( 5888 24280 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 3942 23824 ) ( 4216 * ) VIA12SQ_C ( * 24280 ) VIA23SQ_C W ( 5432 * ) - NEW M1 ( 5432 25496 ) VIA12SQ_C - NEW M2 ( 5432 24280 ) ( * 25496 ) - NEW M2 ( 5432 24280 ) VIA23SQ_C W ( 5888 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n4 - ( U0_UART_RX/U0_uart_fsm/U20 Y ) - ( U0_UART_RX/U0_uart_fsm/U23 A2 ) - ( U0_UART_RX/U0_uart_fsm/U22 A1 ) - ( U0_UART_RX/U0_uart_fsm/U5 A ) - + ROUTED M1 ( 4520 25496 ) VIA12SQ_C - NEW M2 ( 4520 23976 ) ( * 25496 ) - NEW M1 ( 3304 24280 ) VIA12SQ_C - NEW M2 ( 3304 23976 ) ( * 24280 ) - NEW M2 ( 3304 23976 ) VIA23SQ_C W ( 4520 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 3244 22152 ) VIA12SQ_C_1_2 - NEW M2 ( 3304 22152 ) ( * 23064 ) VIA23SQ_C W ( 4520 * ) VIA23SQ_C W ( * 23976 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n5 - ( U0_UART_RX/U0_uart_fsm/U22 Y ) - ( U0_UART_RX/U0_uart_fsm/U25 A1 ) - ( U0_UART_RX/U0_uart_fsm/U24 A2 ) - ( U0_UART_RX/U0_uart_fsm/U23 A3 ) - + ROUTED M1 ( 4216 21696 ) VIA12SQ_C - NEW M2 ( 4216 20632 ) ( * 21696 ) - NEW M1 ( 4216 20632 ) VIA12SQ_C - NEW M1 ( 4216 22456 ) VIA12SQ_C VIA23SQ_C W ( 4976 * ) - NEW M1 ( 5888 22456 ) VIA12SQ_C W VIA23SQ_C W - NEW M3 ( 4976 22456 ) ( 5888 * ) - NEW M1 ( 4976 24584 ) VIA12SQ_C - NEW M2 ( 4976 22456 ) ( * 24584 ) - NEW M2 ( 4976 22456 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n6 - ( U0_UART_RX/U0_uart_fsm/U25 Y ) - ( U0_UART_RX/U0_uart_fsm/U26 A1 ) - + ROUTED M1 ( 7712 22000 ) VIA12SQ_C - NEW M2 ( 7712 22152 ) VIA23SQ_C W - NEW M3 ( 6075 22152 ) ( 7712 * ) - NEW M2 ( 6075 22152 ) VIA23SQ_C W - NEW M2 ( 6075 22152 ) ( * 22304 ) VIA12SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n7 - ( U0_UART_RX/U0_uart_fsm/U4 Y ) - ( U0_UART_RX/U0_uart_fsm/U19 A3 ) - + ROUTED M1 ( 7712 24169 ) VIA12SQ_C ( * 24888 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n8 - ( U0_UART_RX/U0_uart_fsm/U5 Y ) - ( U0_UART_RX/U0_uart_fsm/U21 A3 ) - + ROUTED M1 ( 4824 25344 ) VIA12SQ_C - NEW M2 ( 4824 24888 ) ( * 25344 ) - NEW M2 ( 4824 24888 ) VIA23SQ_C W ( 5736 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n9 - ( U0_UART_RX/U0_uart_fsm/U6 Y ) - ( U0_UART_RX/U0_uart_fsm/U25 A2 ) - ( U0_UART_RX/U0_uart_fsm/U24 A1 ) - + ROUTED M1 ( 4520 20784 ) VIA12SQ_C - NEW M1 ( 3638 18656 ) ( 4368 * ) VIA12SQ_C ( * 20784 ) - NEW M2 ( 4368 20784 ) ( 4520 * ) - NEW M1 ( 5584 22152 ) ( 5711 * ) - NEW M1 ( 5584 21696 ) ( * 22152 ) - NEW M1 ( 4520 21696 ) ( 5584 * ) - NEW M1 ( 4520 21696 ) VIA12SQ_C - NEW M2 ( 4520 20784 ) ( * 21696 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n13 - ( U0_UART_RX/U0_uart_fsm/U55 Y ) - ( U0_UART_RX/U0_uart_fsm/U54 A3 ) - ( U0_UART_RX/U0_uart_fsm/U27 A ) - + ROUTED M1 ( 35224 34008 ) VIA12SQ_C - NEW M2 ( 35224 31576 ) ( * 34008 ) - NEW M2 ( 35224 31576 ) VIA23SQ_C W - NEW M3 ( 33096 31576 ) ( 35224 * ) - NEW M1 ( 33096 31576 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 30968 31880 ) VIA12SQ_C - NEW M2 ( 30968 31576 ) ( * 31880 ) - NEW M2 ( 30968 31576 ) VIA23SQ_C W ( 33096 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n14 - ( U0_UART_RX/U0_uart_fsm/U45 Y ) - ( U0_UART_RX/U0_uart_fsm/U44 A1 ) - ( U0_UART_RX/U0_uart_fsm/U33 A3 ) - ( U0_UART_RX/U0_uart_fsm/U31 A1 ) - ( U0_UART_RX/U0_uart_fsm/U28 A1 ) - + ROUTED M1 ( 36136 30512 ) VIA12SQ_C - NEW M1 ( 34616 24128 ) VIA12SQ_C ( * 25192 ) VIA23SQ_C W ( 36136 * ) - NEW M1 ( 37048 25800 ) VIA12SQ_C W - NEW M2 ( 37048 25192 ) ( * 25800 ) - NEW M2 ( 37048 25192 ) VIA23SQ_C W - NEW M3 ( 36136 25192 ) ( 37048 * ) - NEW M3 ( 34920 30360 ) ( 36136 * ) - NEW M3 ( 36136 30360 ) ( * 30512 ) VIA23SQ_C W - NEW M2 ( 36136 25192 ) VIA23SQ_C W - NEW M2 ( 36136 25192 ) ( * 30512 ) - NEW M1 ( 31880 30360 ) VIA12SQ_C VIA23SQ_C W ( 34920 * ) VIA23SQ_C W ( * 31272 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n16 - ( U0_UART_RX/U0_uart_fsm/U44 Y ) - ( U0_UART_RX/U0_uart_fsm/U43 A ) - ( U0_UART_RX/U0_uart_fsm/U29 A1 ) - + ROUTED M1 ( 34464 25800 ) VIA12SQ_C W VIA23SQ_C W ( 35376 * ) - NEW M1 ( 35376 25496 ) VIA12SQ_C ( * 25800 ) VIA23SQ_C W - NEW M1 ( 36861 25648 ) VIA12SQ_C W ( * 25800 ) VIA23SQ_C W - NEW M3 ( 35376 25800 ) ( 36861 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n19 - ( U0_UART_RX/U0_uart_fsm/U30 Y ) - ( U0_UART_RX/U0_uart_fsm/U29 A2 ) - + ROUTED M1 ( 34312 25496 ) VIA12SQ_C W VIA23SQ_C W - NEW M3 ( 32792 25496 ) ( 34312 * ) - NEW M2 ( 32792 25496 ) VIA23SQ_C W - NEW M2 ( 32792 25496 ) ( * 25852 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n20 - ( U0_UART_RX/U0_uart_fsm/U60 Y ) - ( U0_UART_RX/U0_uart_fsm/U58 A1 ) - ( U0_UART_RX/U0_uart_fsm/U56 A1 ) - ( U0_UART_RX/U0_uart_fsm/U30 A2 ) - + ROUTED M1 ( 32640 27016 ) VIA12SQ_C - NEW M2 ( 32640 25648 ) ( * 27016 ) - NEW M1 ( 32640 25648 ) VIA12SQ_C - NEW M1 ( 17744 25192 ) VIA12SQ_C VIA23SQ_C W ( 29752 * ) - NEW M3 ( 29752 25192 ) ( * 25496 ) - NEW M3 ( 29752 25496 ) ( 30360 * ) - NEW M2 ( 32336 25648 ) ( 32640 * ) - NEW M2 ( 32336 25496 ) ( * 25648 ) - NEW M2 ( 32336 25496 ) VIA23SQ_C W - NEW M3 ( 30360 25496 ) ( 32336 * ) - NEW M2 ( 30360 25496 ) VIA23SQ_C W - NEW M1 ( 30360 25496 ) VIA12SQ_C - NEW M1 ( 30056 25496 ) ( 30360 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n21 - ( U0_UART_RX/U0_uart_fsm/U31 Y ) - ( U0_UART_RX/U0_uart_fsm/U30 A3 ) - + ROUTED M1 ( 32944 25648 ) VIA12SQ_C - NEW M2 ( 32944 24432 ) ( * 25648 ) - NEW M1 ( 32944 24432 ) VIA12SQ_C - NEW M1 ( 32944 24432 ) ( 33248 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n22 - ( U0_UART_RX/U0_uart_fsm/U32 Y ) - ( U0_UART_RX/U0_uart_fsm/U31 A2 ) - + ROUTED M1 ( 33552 23672 ) VIA12SQ_C - NEW M2 ( 33552 22456 ) ( * 23672 ) - NEW M2 ( 33552 22456 ) VIA23SQ_C W - NEW M3 ( 32336 22456 ) ( 33552 * ) - NEW M2 ( 32336 22456 ) VIA23SQ_C W - NEW M1 ( 32336 22456 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n23 - ( U0_UART_RX/U0_uart_fsm/U59 Y ) - ( U0_UART_RX/U0_uart_fsm/U58 A2 ) - ( U0_UART_RX/U0_uart_fsm/U56 A2 ) - ( U0_UART_RX/U0_uart_fsm/U31 S0 ) - + ROUTED M1 ( 34008 23976 ) VIA12SQ_C ( * 25800 ) VIA23SQ_C W - NEW M3 ( 32488 25800 ) ( 34008 * ) - NEW M1 ( 32488 27320 ) VIA12SQ_C - NEW M2 ( 32488 25800 ) ( * 27320 ) - NEW M2 ( 32488 25800 ) VIA23SQ_C W - NEW M3 ( 30208 25800 ) ( 32488 * ) - NEW M1 ( 29600 25344 ) VIA12SQ_C ( * 25800 ) VIA23SQ_C W ( 30208 * ) - NEW M1 ( 30208 25648 ) VIA12SQ_C - NEW M2 ( 30208 25800 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n24 - ( U0_UART_RX/U0_uart_fsm/U53 Y ) - ( U0_UART_RX/U0_uart_fsm/U52 S0 ) - ( U0_UART_RX/U0_uart_fsm/U32 A2 ) - + ROUTED M1 ( 29473 22152 ) VIA12SQ_C W - NEW M2 ( 29473 21544 ) ( * 22152 ) - NEW M2 ( 29473 21544 ) VIA23SQ_C W ( 30512 * ) - NEW M1 ( 30512 19264 ) VIA12SQ_C ( * 21544 ) VIA23SQ_C W ( 31576 * ) VIA23SQ_C W ( * 22152 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n25 - ( U0_UART_RX/U0_uart_fsm/U34 Y ) - ( U0_UART_RX/U0_uart_fsm/U33 A2 ) - + ROUTED M1 ( 35376 30664 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 33896 30664 ) ( 35376 * ) - NEW M2 ( 33896 30664 ) VIA23SQ_C W - NEW M1 ( 33896 30664 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n26 - ( U0_UART_RX/U0_uart_fsm/U56 Y ) - ( U0_UART_RX/U0_uart_fsm/U54 A2 ) - ( U0_UART_RX/U0_uart_fsm/U34 A1 ) - + ROUTED M1 ( 33248 30512 ) VIA12SQ_C - NEW M1 ( 33248 32184 ) ( 33460 * ) - NEW M1 ( 33248 32184 ) VIA12SQ_C - NEW M2 ( 33248 30512 ) ( * 32184 ) - NEW M1 ( 33096 27928 ) ( 33400 * ) VIA12SQ_C ( * 30056 ) - NEW M2 ( 33248 30056 ) ( 33400 * ) - NEW M2 ( 33248 30056 ) ( * 30512 ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n27 - ( U0_UART_RX/U0_uart_fsm/U35 Y ) - ( U0_UART_RX/U0_uart_fsm/U34 A2 ) - + ROUTED M1 ( 32944 30664 ) VIA12SQ_C ( * 33400 ) VIA23SQ_C W ( 34312 * ) VIA23SQ_C W - NEW M1 ( 34312 33552 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n28 - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ Q ) - ( U0_UART_RX/U0_uart_fsm/U77 A1 ) - ( U0_UART_RX/U0_uart_fsm/U75 A1 ) - ( U0_UART_RX/U0_uart_fsm/U74 A2 ) - ( U0_UART_RX/U0_uart_fsm/U55 A1 ) - ( U0_UART_RX/U0_uart_fsm/U34 A3 ) - + ROUTED M1 ( 32336 33248 ) VIA12SQ_C W ( 32488 * ) - NEW M2 ( 32488 32488 ) ( * 33248 ) - NEW M2 ( 32488 32488 ) VIA23SQ_C W - NEW M3 ( 30816 32488 ) ( 32488 * ) - NEW M1 ( 33400 31272 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 30816 30664 ) VIA12SQ_C W ( * 31272 ) - NEW M1 ( 35376 28840 ) VIA12SQ_C ( * 29448 ) VIA23SQ_C W - NEW M3 ( 34312 29448 ) ( 35376 * ) - NEW M1 ( 33704 28840 ) VIA12SQ_C ( * 29448 ) VIA23SQ_C W ( 34312 * ) - NEW M3 ( 30816 31272 ) ( 33400 * ) - NEW M2 ( 30816 31272 ) VIA23SQ_C W - NEW M3 ( 33400 31272 ) ( 34312 * ) VIA23SQ_C W - NEW M2 ( 34312 29448 ) ( * 31272 ) - NEW M2 ( 34312 29448 ) VIA23SQ_C W - NEW M2 ( 30816 31272 ) ( * 32488 ) VIA23SQ_C W - NEW M1 ( 30208 32336 ) VIA12SQ_C - NEW M2 ( 30208 32488 ) VIA23SQ_C W ( 30816 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n29 - ( U0_UART_RX/U0_uart_fsm/U72 Y ) - ( U0_UART_RX/U0_uart_fsm/U36 A1 ) - + ROUTED M1 ( 29296 27168 ) ( 30948 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n30 - ( U0_UART_RX/U0_uart_fsm/U71 Y ) - ( U0_UART_RX/U0_uart_fsm/U36 A2 ) - + ROUTED M1 ( 29144 27472 ) VIA12SQ_C - NEW M2 ( 29144 27624 ) VIA23SQ_C W - NEW M3 ( 27624 27624 ) ( 29144 * ) - NEW M2 ( 27624 27624 ) VIA23SQ_C W - NEW M2 ( 27624 27624 ) ( * 30208 ) VIA12SQ_C - NEW M1 ( 27472 30208 ) ( 27624 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n31 - ( U0_UART_RX/U0_uart_fsm/U58 Y ) - ( U0_UART_RX/U0_uart_fsm/U36 A4 ) - + ROUTED M1 ( 29022 27016 ) ( 29752 * ) VIA12SQ_C - NEW M2 ( 29752 26256 ) ( * 27016 ) - NEW M1 ( 29752 26256 ) VIA12SQ_C - NEW M1 ( 29752 26256 ) ( 30056 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n32 - ( U0_UART_RX/U0_uart_fsm/U37 Y ) - ( U0_UART_RX/U0_uart_fsm/U36 A5 ) - + ROUTED M1 ( 28536 27320 ) VIA12SQ_C - NEW M2 ( 28536 26256 ) ( * 27320 ) - NEW M1 ( 28536 26256 ) VIA12SQ_C - NEW M1 ( 28080 26256 ) ( 28536 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n33 - ( U0_UART_RX/U0_uart_fsm/U54 Y ) - ( U0_UART_RX/U0_uart_fsm/U37 A1 ) - + ROUTED M1 ( 32184 32640 ) ( 32610 * ) - NEW M1 ( 32184 32640 ) VIA12SQ_C - NEW M2 ( 32184 31880 ) ( * 32640 ) - NEW M2 ( 32184 31880 ) VIA23SQ_C W - NEW M3 ( 27776 31880 ) ( 32184 * ) - NEW M2 ( 27776 31880 ) VIA23SQ_C W - NEW M2 ( 27776 25800 ) ( * 31880 ) - NEW M1 ( 27776 25800 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n34 - ( U0_UART_RX/U0_uart_fsm/U38 Y ) - ( U0_UART_RX/U0_uart_fsm/U37 A2 ) - + ROUTED M1 ( 27928 25496 ) VIA12SQ_C - NEW M2 ( 27928 21848 ) ( * 25496 ) - NEW M2 ( 27928 21848 ) VIA23SQ_C W - NEW M3 ( 19568 21848 ) ( 27928 * ) - NEW M2 ( 19568 21848 ) VIA23SQ_C W - NEW M1 ( 19568 21848 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n35 - ( U0_UART_RX/U0_uart_fsm/U52 Y ) - ( U0_UART_RX/U0_uart_fsm/U40 A3 ) - + ROUTED M1 ( 31880 23976 ) VIA12SQ_C - NEW M2 ( 31880 23368 ) ( * 23976 ) - NEW M2 ( 31880 23368 ) VIA23SQ_C W - NEW M3 ( 30816 23368 ) ( 31880 * ) - NEW M2 ( 30816 23368 ) VIA23SQ_C W - NEW M2 ( 30816 22912 ) ( * 23368 ) - NEW M1 ( 30816 22912 ) VIA12SQ_C - NEW M1 ( 30208 22912 ) ( 30816 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n36 - ( U0_UART_RX/U0_uart_fsm/U51 Y ) - ( U0_UART_RX/U0_uart_fsm/U47 A2 ) - + ROUTED M1 ( 13944 6952 ) VIA12SQ_C ( * 8168 ) VIA23SQ_C W ( 15008 * ) VIA23SQ_C W - NEW M1 ( 15008 8320 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n37 - ( U0_UART_RX/U0_uart_fsm/U47 Y ) - ( U0_UART_RX/U0_uart_fsm/U38 A3 ) - + ROUTED M1 ( 19112 22304 ) VIA12SQ_C - NEW M2 ( 19112 21848 ) ( * 22304 ) - NEW M2 ( 19112 21848 ) VIA23SQ_C W - NEW M3 ( 14856 21848 ) ( 19112 * ) - NEW M2 ( 14856 21848 ) VIA23SQ_C W - NEW M2 ( 14856 7864 ) ( * 21848 ) - NEW M1 ( 14856 7864 ) VIA12SQ_C - NEW M1 ( 14552 7864 ) ( 14856 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n38 - ( U0_UART_RX/U0_uart_fsm/U39 Y ) - ( U0_UART_RX/U0_uart_fsm/U38 A4 ) - + ROUTED M1 ( 18504 22152 ) ( 18930 * ) - NEW M1 ( 18504 22152 ) VIA12SQ_C ( * 23216 ) VIA12SQ_C - NEW M1 ( 17896 23216 ) ( 18504 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n39 - ( U0_UART_RX/U0_uart_fsm/U46 Y ) - ( U0_UART_RX/U0_uart_fsm/U39 A3 ) - + ROUTED M1 ( 17136 23672 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 15160 23672 ) ( 17136 * ) - NEW M2 ( 15160 23672 ) VIA23SQ_C W - NEW M2 ( 15160 23672 ) ( * 26560 ) VIA12SQ_C - NEW M1 ( 15008 26560 ) ( 15160 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n40 - ( U0_UART_RX/U0_uart_fsm/U42 Y ) - ( U0_UART_RX/U0_uart_fsm/U39 A2 ) - + ROUTED M1 ( 17288 23976 ) VIA12SQ_C - NEW M2 ( 17288 22912 ) ( * 23976 ) - NEW M2 ( 17288 22912 ) ( 18048 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n41 - ( U0_UART_RX/U0_uart_fsm/U40 Y ) - ( U0_UART_RX/U0_uart_fsm/U39 A4 ) - + ROUTED M1 ( 16984 23976 ) VIA12SQ_C VIA23SQ_C W ( 30968 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n42 - ( U0_UART_RX/U0_uart_fsm/U41 Y ) - ( U0_UART_RX/U0_uart_fsm/U38 A1 ) - + ROUTED M1 ( 19416 22304 ) VIA12SQ_C ( * 22760 ) VIA23SQ_C W ( 21696 * ) VIA23SQ_C W ( * 23216 ) VIA12SQ_C ( 21848 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n43 - ( U0_UART_RX/U0_uart_fsm/U67 Y ) - ( U0_UART_RX/U0_uart_fsm/U39 A1 ) - ( U0_UART_RX/U0_uart_fsm/U66 A4 ) - + ROUTED M1 ( 17440 23672 ) VIA12SQ_C ( * 24280 ) VIA23SQ_C W - NEW M1 ( 16376 23976 ) VIA12SQ_C ( * 24280 ) VIA23SQ_C W ( 17440 * ) - NEW M1 ( 18352 24169 ) VIA12SQ_C - NEW M2 ( 18352 24280 ) VIA23SQ_C W - NEW M3 ( 17440 24280 ) ( 18352 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n44 - ( U0_UART_RX/U0_uart_fsm/U74 Y ) - ( U0_UART_RX/U0_uart_fsm/U73 A2 ) - ( U0_UART_RX/U0_uart_fsm/U45 A ) - + ROUTED M1 ( 31728 30664 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 31120 30664 ) ( 31728 * ) - NEW M3 ( 31120 30360 ) ( * 30664 ) - NEW M1 ( 26560 30664 ) VIA12SQ_C W - NEW M2 ( 26560 30360 ) ( * 30664 ) - NEW M2 ( 26560 30360 ) VIA23SQ_C W ( 31120 * ) VIA23SQ_C W - NEW M1 ( 31120 30512 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n45 - ( U0_UART_RX/U0_uart_fsm/U50 Y ) - ( U0_UART_RX/U0_uart_fsm/U38 A2 ) - + ROUTED M1 ( 11816 21088 ) VIA12SQ_C - NEW M2 ( 11816 21240 ) VIA23SQ_C W ( 19264 * ) VIA23SQ_C W ( * 22152 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n46 - ( U0_UART_RX/U0_uart_fsm/U49 Y ) - ( U0_UART_RX/U0_uart_fsm/U47 A1 ) - + ROUTED M1 ( 14096 7256 ) VIA12SQ_C - NEW M2 ( 14096 6192 ) ( * 7256 ) - NEW M1 ( 14096 6192 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n47 - ( U0_UART_RX/U0_uart_fsm/U48 Y ) - ( U0_UART_RX/U0_uart_fsm/U47 A3 ) - + ROUTED M1 ( 13336 7256 ) ( 13762 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n48 - ( U0_UART_RX/U0_uart_fsm/U79 Y ) - ( U0_UART_RX/U0_uart_fsm/U78 A2 ) - ( U0_UART_RX/U0_uart_fsm/U73 A1 ) - ( U0_UART_RX/U0_uart_fsm/U55 A2 ) - + ROUTED M1 ( 26408 30360 ) VIA12SQ_C W ( * 31272 ) VIA23SQ_C W ( 26864 * ) - NEW M1 ( 26864 34008 ) VIA12SQ_C W - NEW M2 ( 26864 31272 ) ( * 34008 ) - NEW M2 ( 26864 31272 ) VIA23SQ_C W - NEW M1 ( 28536 30208 ) VIA12SQ_C ( * 31272 ) VIA23SQ_C W - NEW M3 ( 26864 31272 ) ( 28536 * ) - NEW M1 ( 30512 32159 ) VIA12BAR W - NEW M2 ( 30360 32184 ) ( 30512 * ) - NEW M2 ( 30360 31272 ) ( * 32184 ) - NEW M2 ( 30360 31272 ) VIA23SQ_C W - NEW M3 ( 28536 31272 ) ( 30360 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n49 - ( U0_UART_RX/U0_uart_fsm/U57 Y ) - ( U0_UART_RX/U0_uart_fsm/U56 A3 ) - + ROUTED M1 ( 32032 27016 ) ( 32306 * ) - NEW M1 ( 32032 27016 ) VIA12SQ_C - NEW M2 ( 32032 25952 ) ( * 27016 ) - NEW M1 ( 32032 25952 ) VIA12SQ_C - NEW M1 ( 31272 25952 ) ( 32032 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n50 - ( U0_UART_RX/U0_uart_fsm/U66 Y ) - ( U0_UART_RX/U0_uart_fsm/U60 A1 ) - + ROUTED M1 ( 16620 25496 ) VIA12SQ_C_1_2 - NEW M2 ( 16680 25496 ) VIA23SQ_C W - NEW M3 ( 15768 25496 ) ( 16680 * ) - NEW M2 ( 15768 25496 ) VIA23SQ_C W - NEW M2 ( 15768 24584 ) ( * 25496 ) - NEW M1 ( 15768 24584 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n51 - ( U0_UART_RX/U0_uart_fsm/U61 Y ) - ( U0_UART_RX/U0_uart_fsm/U60 A2 ) - + ROUTED M1 ( 16984 25319 ) VIA12BAR_C - NEW M2 ( 16984 25192 ) VIA23SQ_C W - NEW M3 ( 12576 25192 ) ( 16984 * ) - NEW M2 ( 12576 25192 ) VIA23SQ_C W - NEW M2 ( 12576 24584 ) ( * 25192 ) - NEW M1 ( 12576 24584 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n52 - ( U0_UART_RX/U0_uart_fsm/U65 Y ) - ( U0_UART_RX/U0_uart_fsm/U61 A1 ) - + ROUTED M1 ( 12424 23824 ) VIA12SQ_C ( * 24888 ) VIA23SQ_C W ( 13640 * ) VIA23SQ_C W - NEW M1 ( 13640 25040 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n53 - ( U0_UART_RX/U0_uart_fsm/U64 Y ) - ( U0_UART_RX/U0_uart_fsm/U61 A2 ) - + ROUTED M1 ( 12272 23976 ) VIA12SQ_C - NEW M2 ( 12272 23672 ) ( * 23976 ) - NEW M2 ( 12272 23672 ) ( 12880 * ) VIA12SQ_C ( 13184 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n54 - ( U0_UART_RX/U0_uart_fsm/U63 Y ) - ( U0_UART_RX/U0_uart_fsm/U61 A3 ) - + ROUTED M1 ( 12120 23824 ) VIA12SQ_C - NEW M2 ( 12120 22912 ) ( * 23824 ) - NEW M2 ( 12120 22912 ) ( 12576 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n55 - ( U0_UART_RX/U0_uart_fsm/U62 Y ) - ( U0_UART_RX/U0_uart_fsm/U61 A4 ) - + ROUTED M1 ( 11968 23824 ) ( * 23976 ) - NEW M1 ( 10600 23824 ) ( 11968 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n56 - ( U0_UART_RX/U0_uart_fsm/U70 Y ) - ( U0_UART_RX/U0_uart_fsm/U66 A1 ) - + ROUTED M1 ( 15920 23824 ) VIA12SQ_C ( * 24584 ) VIA23SQ_C W - NEW M3 ( 11208 24584 ) ( 15920 * ) - NEW M2 ( 11208 24584 ) VIA23SQ_C W - NEW M2 ( 11208 24584 ) ( * 25040 ) VIA12SQ_C - NEW M1 ( 11056 25040 ) ( 11208 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n57 - ( U0_UART_RX/U0_uart_fsm/U69 Y ) - ( U0_UART_RX/U0_uart_fsm/U66 A2 ) - + ROUTED M1 ( 16072 23976 ) VIA12SQ_C - NEW M2 ( 16072 22912 ) ( * 23976 ) - NEW M2 ( 15312 22912 ) ( 16072 * ) - NEW M1 ( 15312 22912 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n58 - ( U0_UART_RX/U0_uart_fsm/U68 Y ) - ( U0_UART_RX/U0_uart_fsm/U66 A3 ) - + ROUTED M1 ( 16224 23824 ) VIA12SQ_C ( * 24888 ) VIA23SQ_C W ( 18656 * ) VIA23SQ_C W ( * 25303 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/n59 - ( U0_UART_RX/U0_uart_fsm/U77 Y ) - ( U0_UART_RX/U0_uart_fsm/U76 A1 ) - ( U0_UART_RX/U0_uart_fsm/U72 A ) - + ROUTED M1 ( 33856 28992 ) VIA12SQ_C - NEW M1 ( 31120 27320 ) VIA12SQ_C ( * 27928 ) VIA23SQ_C W ( 33704 * ) - NEW M3 ( 33704 27928 ) ( * 28232 ) - NEW M3 ( 33704 28232 ) ( 33856 * ) VIA23SQ_C W ( * 28815 ) - NEW M1 ( 43888 28840 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 33856 28840 ) ( 43888 * ) - NEW M2 ( 33856 28840 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[5] - ( U0_UART_RX/U0_uart_fsm/U26 Y ) - ( U0_UART_RX/U0_uart_fsm/U69 A2 ) - + ROUTED M1 ( 13792 22152 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 9080 22152 ) ( 13792 * ) - NEW M2 ( 9080 22152 ) VIA23SQ_C W - NEW M1 ( 9080 22304 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[4] - ( U0_UART_RX/U0_uart_fsm/U24 Y ) - ( U0_UART_RX/U0_uart_fsm/U63 A2 ) - + ROUTED M1 ( 5736 21088 ) VIA12SQ_C - NEW M2 ( 5736 21240 ) VIA23SQ_C W ( 11056 * ) VIA23SQ_C W ( * 22152 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[3] - ( U0_UART_RX/U0_uart_fsm/U23 Y ) - ( U0_UART_RX/U0_uart_fsm/U62 A2 ) - + ROUTED M1 ( 5432 23368 ) VIA12SQ_C VIA23SQ_C W ( 8928 * ) VIA23SQ_C W ( * 23976 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[2] - ( U0_UART_RX/U0_uart_fsm/U21 Y ) - ( U0_UART_RX/U0_uart_fsm/U70 A2 ) - + ROUTED M1 ( 6192 26104 ) VIA12SQ_C VIA23SQ_C W ( 9536 * ) VIA23SQ_C W - NEW M2 ( 9536 25496 ) ( * 26104 ) - NEW M1 ( 9536 25496 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[1] - ( U0_UART_RX/U0_uart_fsm/U19 Y ) - ( U0_UART_RX/U0_uart_fsm/U65 A2 ) - + ROUTED M1 ( 8208 25496 ) VIA12SQ_C VIA23SQ_C W ( 12120 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/check_edge[0] - ( U0_UART_RX/U0_uart_fsm/U17 Y ) - ( U0_UART_RX/U0_uart_fsm/U64 A2 ) - + ROUTED M1 ( 14704 23976 ) VIA12SQ_C - NEW M2 ( 14704 21088 ) ( * 23976 ) - NEW M1 ( 14704 21088 ) VIA12SQ_C - NEW M1 ( 13488 21088 ) ( 14704 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/next_state[2] - ( U0_UART_RX/U0_uart_fsm/U29 Y ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ D ) - + ROUTED M1 ( 34616 27320 ) VIA12SQ_C - NEW M2 ( 34616 26256 ) ( * 27320 ) - NEW M1 ( 34616 26256 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/next_state[1] - ( U0_UART_RX/U0_uart_fsm/U33 Y ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ D ) - + ROUTED M1 ( 28384 34008 ) VIA12SQ_C - NEW M2 ( 28384 33096 ) ( * 34008 ) - NEW M2 ( 28384 33096 ) VIA23SQ_C W ( 34008 * ) VIA23SQ_C W - NEW M2 ( 34008 31120 ) ( * 33096 ) - NEW M1 ( 34008 31120 ) VIA12SQ_C - NEW M1 ( 34008 31120 ) ( 34464 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/next_state[0] - ( U0_UART_RX/U0_uart_fsm/U36 Y ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ D ) - + ROUTED M1 ( 28384 28840 ) VIA12SQ_C - NEW M2 ( 28232 28840 ) ( 28384 * ) - NEW M2 ( 28232 27776 ) ( * 28840 ) - NEW M2 ( 28080 27776 ) ( 28232 * ) - NEW M1 ( 28080 27776 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/sub_40_carry[5] - ( U0_UART_RX/U0_uart_fsm/U11 Y ) - ( U0_UART_RX/U0_uart_fsm/U10 A2 ) - + ROUTED M1 ( 5888 10600 ) VIA12SQ_C - NEW M2 ( 5888 9384 ) ( * 10600 ) - NEW M2 ( 5888 9384 ) ( 6192 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/sub_40_carry[4] - ( U0_UART_RX/U0_uart_fsm/U13 Y ) - ( U0_UART_RX/U0_uart_fsm/U12 A1 ) - ( U0_UART_RX/U0_uart_fsm/U11 A2 ) - + ROUTED M1 ( 5888 8751 ) VIA12BAR_C - NEW M2 ( 5888 8472 ) ( * 8751 ) - NEW M2 ( 5888 8472 ) VIA23SQ_C W - NEW M3 ( 5432 8472 ) ( 5888 * ) - NEW M1 ( 5432 5280 ) VIA12SQ_C ( * 8472 ) VIA23SQ_C W - NEW M1 ( 4824 8472 ) VIA12SQ_C VIA23SQ_C W ( 5432 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_uart_fsm/sub_40_carry[3] - ( U0_UART_RX/U0_uart_fsm/U15 Y ) - ( U0_UART_RX/U0_uart_fsm/U14 A1 ) - ( U0_UART_RX/U0_uart_fsm/U13 A2 ) - + ROUTED M1 ( 4368 8751 ) VIA12BAR_C - NEW M2 ( 4368 8168 ) ( * 8751 ) - NEW M2 ( 4368 8168 ) ( 4520 * ) - NEW M1 ( 4520 7408 ) VIA12SQ_C ( * 8168 ) - NEW M2 ( 4520 8168 ) ( * 14704 ) - NEW M2 ( 4064 14704 ) ( 4520 * ) - NEW M2 ( 4064 14704 ) ( * 16528 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N8 - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_1 SO ) - ( U0_UART_RX/U0_edge_bit_counter/U34 A1 ) - + ROUTED M1 ( 16984 32336 ) VIA12SQ_C - NEW M2 ( 16984 32184 ) VIA23SQ_C W - NEW M3 ( 15920 32184 ) ( 16984 * ) - NEW M2 ( 15920 32184 ) VIA23SQ_C W - NEW M1 ( 15920 32336 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N9 - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_2 SO ) - ( U0_UART_RX/U0_edge_bit_counter/U33 A1 ) - + ROUTED M1 ( 16528 35680 ) ( 17562 * ) - NEW M1 ( 16528 35680 ) VIA12SQ_C - NEW M2 ( 16528 33856 ) ( * 35680 ) - NEW M1 ( 16528 33856 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N10 - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_3 SO ) - ( U0_UART_RX/U0_edge_bit_counter/U32 A1 ) - + ROUTED M1 ( 17136 39024 ) VIA12SQ_C - NEW M2 ( 17136 37960 ) ( * 39024 ) - NEW M2 ( 17136 37960 ) VIA23SQ_C W - NEW M3 ( 16072 37960 ) ( 17136 * ) - NEW M2 ( 16072 37960 ) VIA23SQ_C W - NEW M2 ( 16072 37200 ) ( * 37960 ) - NEW M1 ( 16072 37200 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N11 - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_4 SO ) - ( U0_UART_RX/U0_edge_bit_counter/U31 A1 ) - + ROUTED M1 ( 15342 40519 ) ( 15768 * ) VIA12SQ_C - NEW M2 ( 15768 39024 ) ( * 40519 ) - NEW M1 ( 15768 39024 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N12 - ( U0_UART_RX/U0_edge_bit_counter/U49 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U30 A1 ) - + ROUTED M1 ( 16528 42368 ) ( 16802 * ) - NEW M1 ( 16528 42368 ) VIA12SQ_C ( * 42824 ) VIA23SQ_C W - NEW M3 ( 15920 42824 ) ( 16528 * ) - NEW M2 ( 15920 42824 ) VIA23SQ_C W - NEW M2 ( 15920 42824 ) ( * 43280 ) VIA12SQ_C - NEW M1 ( 15768 43280 ) ( 15920 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N19 - ( U0_UART_RX/U0_edge_bit_counter/U35 Y ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ D ) - + ROUTED M1 ( 17288 30664 ) VIA12SQ_C ( * 31272 ) VIA23SQ_C W ( 18200 * ) VIA23SQ_C W ( * 31576 ) VIA12SQ_C ( 18504 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N20 - ( U0_UART_RX/U0_edge_bit_counter/U34 Y ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ D ) - + ROUTED M1 ( 16224 27320 ) VIA12SQ_C ( * 31576 ) VIA12SQ_C ( 16528 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N21 - ( U0_UART_RX/U0_edge_bit_counter/U33 Y ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ D ) - + ROUTED M1 ( 17744 34008 ) VIA12SQ_C ( * 34616 ) VIA23SQ_C W ( 18504 * ) VIA23SQ_C W ( * 34920 ) VIA12SQ_C - NEW M1 ( 18048 34920 ) ( 18504 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N22 - ( U0_UART_RX/U0_edge_bit_counter/U32 Y ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ D ) - + ROUTED M1 ( 17362 37352 ) ( 17592 * ) VIA12SQ_C ( * 37960 ) - NEW M2 ( 17592 37960 ) ( 17744 * ) - NEW M2 ( 17744 37960 ) ( * 38264 ) VIA12SQ_C - NEW M1 ( 17592 38264 ) ( 17744 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N23 - ( U0_UART_RX/U0_edge_bit_counter/U31 Y ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ D ) - + ROUTED M1 ( 16680 40696 ) VIA12SQ_C - NEW M2 ( 16680 39632 ) ( * 40696 ) - NEW M1 ( 16680 39632 ) VIA12SQ_C - NEW M1 ( 16376 39632 ) ( 16680 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N24 - ( U0_UART_RX/U0_edge_bit_counter/U30 Y ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ D ) - + ROUTED M1 ( 17592 44040 ) VIA12SQ_C - NEW M2 ( 17592 42976 ) ( * 44040 ) - NEW M1 ( 17592 42976 ) VIA12SQ_C - NEW M1 ( 17288 42976 ) ( 17592 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N26 - ( U0_UART_RX/U0_edge_bit_counter/U41 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U56 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U15 A ) - + ROUTED M1 ( 17896 17288 ) VIA12SQ_C - NEW M1 ( 11512 19416 ) VIA12SQ_C VIA23SQ_C W ( 17744 * ) VIA23SQ_C W - NEW M2 ( 17744 17288 ) ( * 19416 ) - NEW M2 ( 17744 17288 ) ( 17896 * ) - NEW M1 ( 19506 17288 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 17896 17288 ) ( 19506 * ) - NEW M2 ( 17896 17288 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N27 - ( U0_UART_RX/U0_edge_bit_counter/U43 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U51 A1 ) - + ROUTED M1 ( 9080 15008 ) VIA12SQ_C - NEW M2 ( 9080 14552 ) ( * 15008 ) - NEW M2 ( 9080 14552 ) VIA23SQ_C W ( 11816 * ) VIA23SQ_C W - NEW M2 ( 11816 14096 ) ( * 14552 ) - NEW M1 ( 11816 14096 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N28 - ( U0_UART_RX/U0_edge_bit_counter/U45 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U50 A1 ) - + ROUTED M1 ( 9424 7256 ) VIA12SQ_C VIA23SQ_C W ( 11208 * ) VIA23SQ_C W ( * 8624 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N29 - ( U0_UART_RX/U0_edge_bit_counter/U46 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U52 A1 ) - + ROUTED M1 ( 9840 4368 ) ( 10296 * ) VIA12SQ_C ( * 5280 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N30 - ( U0_UART_RX/U0_edge_bit_counter/U48 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U54 A1 ) - + ROUTED M1 ( 9840 9536 ) ( 9992 * ) VIA12SQ_C ( * 13640 ) VIA23SQ_C W ( 14704 * ) VIA23SQ_C W ( * 14096 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/N31 - ( U0_UART_RX/U0_edge_bit_counter/U59 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U36 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U18 A1 ) - + ROUTED M1 ( 19264 20657 ) VIA12BAR_C - NEW M2 ( 19264 19112 ) ( * 20657 ) - NEW M1 ( 16984 16072 ) ( 17136 * ) VIA12SQ_C ( * 18200 ) VIA23SQ_C W ( 19264 * ) VIA23SQ_C W ( * 19112 ) - NEW M1 ( 21088 18960 ) VIA12SQ_C - NEW M2 ( 21088 19112 ) VIA23SQ_C W - NEW M3 ( 19264 19112 ) ( 21088 * ) - NEW M2 ( 19264 19112 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/dftopt7_gOb13 - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ SI ) - ( U0_UART_RX/U0_edge_bit_counter/U25 A4 ) - ( U0_UART_RX/U0_edge_bit_counter/U24 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U23 A1 ) - + ROUTED M1 ( 16468 26712 ) VIA12SQ_C_1_2 - NEW M2 ( 16528 26712 ) ( * 27320 ) VIA23SQ_C W ( 23976 * ) - NEW M1 ( 27168 28259 ) VIA12SQ_C - NEW M2 ( 27168 27320 ) ( * 28259 ) - NEW M2 ( 27168 27320 ) VIA23SQ_C W - NEW M3 ( 26864 27320 ) ( 27168 * ) - NEW M1 ( 26316 25496 ) VIA12SQ_C_1_2 - NEW M2 ( 26256 25496 ) ( * 27320 ) VIA23SQ_C W - NEW M1 ( 26864 27320 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 23976 27320 ) ( 26256 * ) - NEW M3 ( 26256 27320 ) ( 26864 * ) - NEW M2 ( 23976 27320 ) VIA23SQ_C W - NEW M1 ( 23976 27472 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/dftopt8_gOb14 - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ SI ) - ( U0_UART_RX/U0_edge_bit_counter/U29 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U27 A2 ) - + ROUTED M1 ( 17532 30056 ) VIA12SQ_C_1_2 - NEW M2 ( 17592 30056 ) ( * 31576 ) VIA23SQ_C W ( 20936 * ) - NEW M1 ( 21088 27320 ) VIA12SQ_C ( * 31576 ) - NEW M2 ( 20936 31576 ) ( 21088 * ) - NEW M1 ( 20936 32184 ) VIA12SQ_C - NEW M2 ( 20936 31576 ) ( * 32184 ) - NEW M2 ( 20936 31576 ) VIA23SQ_C W - NEW M1 ( 27198 31880 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 20936 31880 ) ( 27198 * ) - NEW M3 ( 20936 31576 ) ( * 31880 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n18 - ( U0_UART_RX/U0_edge_bit_counter/U19 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U16 A1 ) - + ROUTED M1 ( 22304 20328 ) ( 23034 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n19 - ( U0_UART_RX/U0_edge_bit_counter/U17 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U16 A2 ) - + ROUTED M1 ( 22912 20632 ) VIA12SQ_C W ( * 21240 ) VIA23SQ_C W - NEW M3 ( 20176 21240 ) ( 22912 * ) - NEW M2 ( 20176 21240 ) VIA23SQ_C W - NEW M1 ( 20176 21240 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n20 - ( U0_UART_RX/U0_edge_bit_counter/U21 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U20 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U17 A2 ) - + ROUTED M1 ( 20480 20632 ) VIA12SQ_C ( * 23824 ) VIA12SQ_C - NEW M1 ( 19416 24888 ) ( 19568 * ) - NEW M1 ( 19416 24888 ) VIA12SQ_C - NEW M2 ( 19416 24584 ) ( * 24888 ) - NEW M2 ( 19416 24584 ) VIA23SQ_C W ( 20024 * ) - NEW M3 ( 20024 24280 ) ( * 24584 ) - NEW M3 ( 20024 24280 ) ( 20480 * ) VIA23SQ_C W - NEW M2 ( 20480 23824 ) ( * 24280 ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n21 - ( U0_UART_RX/U0_edge_bit_counter/U18 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U17 A3 ) - + ROUTED M1 ( 20632 20480 ) VIA12SQ_C - NEW M2 ( 20632 19568 ) ( * 20480 ) - NEW M1 ( 20632 19568 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n22 - ( U0_UART_RX/U0_edge_bit_counter/U36 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U6 A ) - ( U0_UART_RX/U0_edge_bit_counter/U29 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U26 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U19 A1 ) - + ROUTED M2 ( 20784 25800 ) ( 20936 * ) - NEW M2 ( 20784 25800 ) ( * 28840 ) - NEW M2 ( 20632 28840 ) ( 20784 * ) - NEW M1 ( 20632 32336 ) ( 20906 * ) - NEW M1 ( 20632 32336 ) VIA12SQ_C - NEW M2 ( 20632 28840 ) ( * 32336 ) - NEW M1 ( 19720 20936 ) VIA12SQ_C - NEW M2 ( 19720 20632 ) ( * 20936 ) - NEW M2 ( 19720 20632 ) VIA23SQ_C W ( 20936 * ) - NEW M1 ( 20632 28840 ) ( 20906 * ) - NEW M1 ( 20632 28840 ) VIA12SQ_C - NEW M2 ( 20936 20632 ) ( * 25800 ) - NEW M2 ( 20936 20632 ) VIA23SQ_C W - NEW M1 ( 21696 20480 ) VIA12SQ_C - NEW M2 ( 21696 20632 ) VIA23SQ_C W - NEW M3 ( 20936 20632 ) ( 21696 * ) - NEW M1 ( 20936 25800 ) VIA12SQ_C - NEW M1 ( 20936 25800 ) ( 21240 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n23 - ( U0_UART_RX/U0_edge_bit_counter/U20 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U19 A2 ) - + ROUTED M1 ( 21240 23216 ) VIA12SQ_C - NEW M2 ( 21240 20632 ) ( * 23216 ) - NEW M1 ( 21240 20632 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n24 - ( U0_UART_RX/U0_edge_bit_counter/U24 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U22 A2 ) - + ROUTED M1 ( 23672 25800 ) VIA12SQ_C VIA23SQ_C W ( 25952 * ) VIA23SQ_C W ( * 26560 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n25 - ( U0_UART_RX/U0_edge_bit_counter/U23 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U22 A3 ) - + ROUTED M1 ( 23368 24888 ) VIA12SQ_C VIA23SQ_C W ( 25192 * ) VIA23SQ_C W ( * 25192 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n26 - ( U0_UART_RX/U0_edge_bit_counter/U26 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U25 A3 ) - ( U0_UART_RX/U0_edge_bit_counter/U22 A4 ) - + ROUTED M1 ( 23520 25344 ) VIA12SQ_C - NEW M1 ( 23824 27928 ) VIA12SQ_C - NEW M2 ( 23520 27928 ) ( 23824 * ) - NEW M2 ( 23520 25496 ) ( * 27928 ) - NEW M2 ( 23520 25496 ) VIA23SQ_C W - NEW M3 ( 22608 25496 ) ( 23520 * ) - NEW M2 ( 22608 25496 ) VIA23SQ_C W - NEW M1 ( 22608 25496 ) VIA12SQ_C - NEW M1 ( 22000 25496 ) ( 22608 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n27 - ( U0_UART_RX/U0_edge_bit_counter/U27 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U25 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U24 A3 ) - + ROUTED M1 ( 26408 27928 ) VIA12SQ_C - NEW M2 ( 26408 27624 ) ( * 27928 ) - NEW M2 ( 26408 27624 ) VIA23SQ_C W - NEW M3 ( 24128 27624 ) ( 26408 * ) - NEW M1 ( 24128 27016 ) VIA12SQ_C ( * 27624 ) VIA23SQ_C W - NEW M1 ( 22000 26864 ) VIA12SQ_C ( * 27624 ) VIA23SQ_C W ( 24128 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n28 - ( U0_UART_RX/U0_edge_bit_counter/U29 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U28 A3 ) - + ROUTED M1 ( 23672 31272 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 21544 31272 ) ( 23672 * ) - NEW M2 ( 21544 31272 ) VIA23SQ_C W - NEW M2 ( 21544 31272 ) ( * 31576 ) VIA12SQ_C - NEW M1 ( 21392 31576 ) ( 21544 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n29 - ( U0_UART_RX/U0_edge_bit_counter/U16 Y ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ D ) - + ROUTED M1 ( 23368 22152 ) VIA12SQ_C - NEW M2 ( 23368 21240 ) ( * 22152 ) - NEW M1 ( 23368 21240 ) VIA12SQ_C - NEW M1 ( 23216 21240 ) ( 23368 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n30 - ( U0_UART_RX/U0_edge_bit_counter/U22 Y ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ D ) - + ROUTED M1 ( 23976 23976 ) VIA12SQ_C ( * 24584 ) VIA23SQ_C W - NEW M3 ( 22760 24584 ) ( 23976 * ) - NEW M2 ( 22760 24584 ) VIA23SQ_C W - NEW M2 ( 22760 24584 ) ( * 25040 ) VIA12SQ_C ( 22912 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n31 - ( U0_UART_RX/U0_edge_bit_counter/U25 Y ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ D ) - + ROUTED M1 ( 22912 27624 ) ( 23368 * ) - NEW M1 ( 22912 27624 ) VIA12SQ_C ( * 28840 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n32 - ( U0_UART_RX/U0_edge_bit_counter/U28 Y ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ D ) - + ROUTED M1 ( 22912 30968 ) ( 23216 * ) - NEW M1 ( 22912 30968 ) VIA12SQ_C ( * 32184 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n1 - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ SI ) - ( U0_UART_RX/U0_edge_bit_counter/U35 A1 ) - + ROUTED M1 ( 21696 30208 ) VIA12SQ_C ( * 32184 ) VIA23SQ_C W - NEW M3 ( 18960 32184 ) ( 21696 * ) - NEW M2 ( 18960 32184 ) VIA23SQ_C W - NEW M1 ( 18960 32336 ) VIA12SQ_C - NEW M1 ( 21696 30208 ) ( 22608 * ) VIA12SQ_C - NEW M2 ( 22608 29448 ) ( * 30208 ) - NEW M1 ( 22608 29448 ) VIA12SQ_C - NEW M1 ( 22608 29448 ) ( 23064 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n13 - ( U0_UART_RX/U0_edge_bit_counter/U40 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U43 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U42 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U37 A ) - + ROUTED M1 ( 8016 17288 ) ( 8290 * ) - NEW M1 ( 8016 17288 ) VIA12SQ_C ( * 17592 ) VIA23SQ_C W - NEW M3 ( 7560 17592 ) ( 8016 * ) - NEW M2 ( 7560 17592 ) VIA23SQ_C W - NEW M1 ( 7712 17592 ) VIA12SQ_C - NEW M2 ( 7560 17592 ) ( 7712 * ) - NEW M2 ( 7560 15616 ) ( * 17592 ) - NEW M1 ( 7560 15616 ) VIA12SQ_C - NEW M1 ( 8168 15464 ) ( * 15616 ) - NEW M1 ( 7560 15616 ) ( 8168 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n17 - ( U0_UART_RX/U0_edge_bit_counter/U42 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U45 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U44 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U38 A ) - + ROUTED M1 ( 7104 13944 ) VIA12SQ_C - NEW M2 ( 6952 13944 ) ( 7104 * ) - NEW M1 ( 6800 15160 ) VIA12SQ_C - NEW M2 ( 6800 13944 ) ( * 15160 ) - NEW M2 ( 6800 13944 ) ( 6952 * ) - NEW M1 ( 8472 7256 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 6952 7256 ) ( 8472 * ) - NEW M2 ( 6952 7256 ) VIA23SQ_C W - NEW M2 ( 6952 7256 ) ( * 13944 ) - NEW M1 ( 6892 7256 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n33 - ( U0_UART_RX/U0_edge_bit_counter/U44 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U47 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U46 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U45 A3 ) - + ROUTED M1 ( 8046 7560 ) ( 8320 * ) VIA12SQ_C VIA23SQ_C W ( 8624 * ) VIA23SQ_C W - NEW M1 ( 8624 7864 ) ( 8898 * ) - NEW M1 ( 8624 7864 ) VIA12SQ_C - NEW M2 ( 8624 7560 ) ( * 7864 ) - NEW M2 ( 8472 5736 ) ( * 6952 ) - NEW M2 ( 8472 6952 ) ( 8624 * ) - NEW M2 ( 8624 6952 ) ( * 7560 ) - NEW M1 ( 8320 3912 ) VIA12SQ_C ( 8472 * ) - NEW M2 ( 8472 3912 ) ( * 5736 ) - NEW M1 ( 7712 5736 ) VIA12SQ_C ( 8472 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n34 - ( U0_UART_RX/U0_edge_bit_counter/U47 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U48 A1 ) - + ROUTED M1 ( 7864 6192 ) VIA12SQ_C ( * 8472 ) VIA23SQ_C W ( 8624 * ) VIA23SQ_C W - NEW M1 ( 8624 8624 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n35 - ( U0_UART_RX/U0_edge_bit_counter/U37 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U41 A3 ) - + ROUTED M1 ( 8320 17896 ) VIA12SQ_C ( 8776 * ) - NEW M2 ( 8776 17896 ) ( * 18504 ) VIA23SQ_C W ( 10904 * ) VIA23SQ_C W - NEW M2 ( 10904 18200 ) ( * 18504 ) - NEW M1 ( 10904 18200 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n36 - ( U0_UART_RX/U0_edge_bit_counter/U38 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U43 A3 ) - + ROUTED M1 ( 8320 14856 ) ( 8624 * ) - NEW M1 ( 8320 14856 ) VIA12SQ_C - NEW M2 ( 8168 14856 ) ( 8320 * ) - NEW M2 ( 8168 14096 ) ( * 14856 ) - NEW M1 ( 8168 14096 ) VIA12SQ_C - NEW M1 ( 7408 14096 ) ( 8168 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n37 - ( U0_UART_RX/U0_edge_bit_counter/U39 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U47 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U46 A1 ) - + ROUTED M1 ( 7560 5432 ) VIA12SQ_C W - NEW M2 ( 7560 4216 ) ( * 5432 ) - NEW M2 ( 7560 4216 ) VIA23SQ_C W - NEW M1 ( 8624 4064 ) VIA12SQ_C - NEW M2 ( 8624 4216 ) VIA23SQ_C W - NEW M3 ( 7560 4216 ) ( 8624 * ) - NEW M1 ( 6344 4064 ) VIA12SQ_C - NEW M2 ( 6344 4216 ) VIA23SQ_C W ( 7560 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n38 - ( U0_UART_RX/U0_edge_bit_counter/U52 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U53 A3 ) - + ROUTED M1 ( 11816 10448 ) ( 12424 * ) - NEW M1 ( 11816 10448 ) VIA12SQ_C - NEW M2 ( 11816 6192 ) ( * 10448 ) - NEW M1 ( 11816 6192 ) VIA12SQ_C - NEW M1 ( 11512 6192 ) ( 11816 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n39 - ( U0_UART_RX/U0_edge_bit_counter/U51 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U53 A2 ) - + ROUTED M1 ( 13032 13184 ) ( 13184 * ) VIA12SQ_C - NEW M2 ( 13184 10904 ) ( * 13184 ) - NEW M2 ( 13184 10904 ) VIA23SQ_C W - NEW M3 ( 12728 10904 ) ( 13184 * ) - NEW M2 ( 12728 10904 ) VIA23SQ_C W - NEW M2 ( 12728 10448 ) ( * 10904 ) - NEW M1 ( 12728 10448 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n40 - ( U0_UART_RX/U0_edge_bit_counter/U50 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U53 A1 ) - + ROUTED M1 ( 12424 9536 ) ( 12576 * ) VIA12SQ_C ( * 10600 ) VIA12SQ_C ( 12788 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n41 - ( U0_UART_RX/U0_edge_bit_counter/U55 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U56 A3 ) - ( U0_UART_RX/U0_edge_bit_counter/U56 A2 ) - + ROUTED M1 ( 18960 16984 ) VIA12SQ_C - NEW M1 ( 19112 16528 ) ( 19324 * ) - NEW M1 ( 19112 16528 ) ( * 16680 ) VIA12SQ_C - NEW M2 ( 18960 16680 ) ( 19112 * ) - NEW M2 ( 18960 16680 ) ( * 16984 ) - NEW M2 ( 18960 16984 ) ( * 18504 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n42 - ( U0_UART_RX/U0_edge_bit_counter/U57 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U58 A4 ) - ( U0_UART_RX/U0_edge_bit_counter/U58 A1 ) - + ROUTED M1 ( 16832 17288 ) ( 17044 * ) - NEW M1 ( 14248 18200 ) ( 14704 * ) - NEW M1 ( 14248 18200 ) VIA12SQ_C - NEW M2 ( 14248 17896 ) ( * 18200 ) - NEW M2 ( 14248 17896 ) VIA23SQ_C W ( 16832 * ) VIA23SQ_C W - NEW M2 ( 16832 17288 ) ( * 17896 ) - NEW M1 ( 16832 17288 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n43 - ( U0_UART_RX/U0_edge_bit_counter/U58 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U59 A4 ) - + ROUTED M1 ( 16224 16680 ) VIA12SQ_C - NEW M2 ( 16224 15464 ) ( * 16680 ) - NEW M2 ( 16224 15464 ) ( 16376 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n44 - ( U0_UART_RX/U0_edge_bit_counter/U56 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U59 A3 ) - + ROUTED M1 ( 18656 16680 ) VIA12SQ_C - NEW M2 ( 18656 16376 ) ( * 16680 ) - NEW M2 ( 18656 16376 ) VIA23SQ_C W - NEW M3 ( 16072 16376 ) ( 18656 * ) - NEW M2 ( 16072 16376 ) VIA23SQ_C W - NEW M2 ( 16072 15768 ) ( * 16376 ) - NEW M1 ( 16072 15768 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n45 - ( U0_UART_RX/U0_edge_bit_counter/U54 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U59 A2 ) - + ROUTED M1 ( 15996 15464 ) VIA12SQ_C - NEW M2 ( 15994 15437 ) ( 16072 * ) - NEW M2 ( 15994 15464 ) ( 16072 * ) - NEW M2 ( 16072 14400 ) ( * 15450 ) - NEW M1 ( 16072 14400 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n46 - ( U0_UART_RX/U0_edge_bit_counter/U53 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U59 A1 ) - + ROUTED M1 ( 13062 10448 ) ( 13792 * ) VIA12SQ_C ( * 11208 ) VIA23SQ_C W ( 15616 * ) VIA23SQ_C W ( * 15312 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n47 - ( U0_UART_RX/U0_edge_bit_counter/U15 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U58 A2 ) - + ROUTED M1 ( 16984 16528 ) VIA12SQ_C ( * 16984 ) VIA23SQ_C W ( 17440 * ) VIA23SQ_C W ( * 17440 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n48 - ( U0_UART_RX/U0_edge_bit_counter/U6 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U35 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U34 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U33 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U32 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U31 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U30 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/U28 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U27 A3 ) - + ROUTED M1 ( 21544 27928 ) VIA12SQ_C ( * 28536 ) - NEW M3 ( 16984 38568 ) VIA34SQ_C - NEW M1 ( 16680 42216 ) VIA12SQ_C VIA23SQ_C W ( 16984 * ) VIA34SQ_C - NEW M4 ( 16984 38568 ) ( * 42216 ) - NEW M1 ( 17136 32184 ) VIA12SQ_C ( * 32488 ) - NEW M1 ( 19112 32184 ) VIA12SQ_C - NEW M1 ( 21240 28688 ) VIA12SQ_C ( * 29144 ) - NEW M2 ( 17136 32488 ) VIA23SQ_C W ( 19112 * ) VIA23SQ_C W - NEW M2 ( 19112 32184 ) ( * 32488 ) - NEW M1 ( 17440 35528 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 17136 35528 ) ( 17440 * ) - NEW M2 ( 21544 28536 ) ( * 29144 ) - NEW M2 ( 21240 29144 ) ( 21544 * ) - NEW M2 ( 21240 29144 ) VIA23SQ_C W - NEW M3 ( 20328 29144 ) ( 21240 * ) - NEW M3 ( 20328 29144 ) ( * 29448 ) - NEW M3 ( 19112 29448 ) ( 20328 * ) - NEW M2 ( 19112 29448 ) VIA23SQ_C W - NEW M2 ( 19112 29448 ) ( * 32184 ) - NEW M4 ( 16984 35528 ) ( * 38568 ) - NEW M3 ( 16984 35528 ) VIA34SQ_C - NEW M2 ( 17136 32488 ) ( * 35528 ) VIA23SQ_C W - NEW M1 ( 24128 30664 ) VIA12SQ_C - NEW M2 ( 24128 28536 ) ( * 30664 ) - NEW M2 ( 24128 28536 ) VIA23SQ_C W - NEW M3 ( 21544 28536 ) ( 24128 * ) - NEW M2 ( 21544 28536 ) VIA23SQ_C W - NEW M1 ( 15768 38872 ) VIA12SQ_C W - NEW M2 ( 15768 38568 ) ( * 38872 ) - NEW M2 ( 15768 38568 ) VIA23SQ_C W ( 16984 * ) VIA23SQ_C W ( * 38872 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n49 - ( U0_UART_RX/U0_edge_bit_counter/U14 Y ) - ( U0_UART_RX/U0_edge_bit_counter/U36 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/U20 A3 ) - + ROUTED M2 ( 20632 22000 ) ( * 24584 ) VIA12SQ_C - NEW M1 ( 19031 20480 ) VIA12SQ_C W ( * 20936 ) VIA23SQ_C W ( 20632 * ) VIA23SQ_C W ( * 22000 ) - NEW M1 ( 20632 22000 ) ( 21544 * ) - NEW M1 ( 20632 22000 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/dftopt3_gOb5 - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ SI ) - + ROUTED M1 ( 17744 36744 ) VIA12SQ_C ( * 37656 ) VIA23SQ_C W ( 20936 * ) VIA23SQ_C W ( * 39936 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/n53 - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ SI ) - + ROUTED M1 ( 17988 33400 ) VIA12SQ_C_1_2 - NEW M2 ( 18048 33400 ) ( * 36440 ) VIA23SQ_C W ( 21544 * ) VIA23SQ_C W - NEW M1 ( 21544 36592 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/add_31_carry[5] - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_4 C1 ) - ( U0_UART_RX/U0_edge_bit_counter/U49 A1 ) - + ROUTED M1 ( 14856 40392 ) VIA12SQ_C W ( * 44192 ) - NEW M2 ( 14509 44192 ) ( 14856 * ) - NEW M1 ( 14509 44192 ) VIA12SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/add_31_carry[4] - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_3 C1 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_4 B0 ) - + ROUTED M1 ( 15616 37048 ) VIA12SQ_C W ( * 39784 ) VIA23SQ_C W - NEW M3 ( 14248 39784 ) ( 15616 * ) - NEW M2 ( 14248 39784 ) VIA23SQ_C W - NEW M2 ( 14248 39784 ) ( * 40848 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/add_31_carry[3] - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_2 C1 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_3 B0 ) - + ROUTED M1 ( 15312 37504 ) VIA12SQ_C - NEW M2 ( 15312 36896 ) ( * 37504 ) - NEW M2 ( 15312 36896 ) ( 16072 * ) - NEW M2 ( 16072 33704 ) ( * 36896 ) - NEW M1 ( 16072 33704 ) VIA12SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_edge_bit_counter/add_31_carry[2] - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_1 C1 ) - ( U0_UART_RX/U0_edge_bit_counter/add_31_U1_1_2 B0 ) - + ROUTED M1 ( 15464 32488 ) VIA12SQ_C W ( * 34160 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/N58 - ( U0_UART_RX/U0_data_sampling/U62 Y ) - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg D ) - + ROUTED M1 ( 28840 38720 ) VIA12SQ_C - NEW M2 ( 28840 38872 ) VIA23SQ_C W ( 31272 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n23 - ( U0_UART_RX/U0_data_sampling/U46 Y ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ D ) - + ROUTED M1 ( 20480 39632 ) VIA12SQ_C - NEW M2 ( 20480 39784 ) VIA23SQ_C W ( 23520 * ) VIA23SQ_C W ( * 40696 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n24 - ( U0_UART_RX/U0_data_sampling/U37 Y ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ D ) - + ROUTED M1 ( 24128 44040 ) VIA12SQ_C - NEW M2 ( 24128 39632 ) ( * 44040 ) - NEW M1 ( 24128 39632 ) VIA12SQ_C - NEW M1 ( 23064 39632 ) ( 24128 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n25 - ( U0_UART_RX/U0_data_sampling/U27 Y ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ D ) - + ROUTED M1 ( 23138 35528 ) ( 23368 * ) VIA12SQ_C - NEW M2 ( 23368 34920 ) ( * 35528 ) - NEW M2 ( 23368 34920 ) VIA23SQ_C W - NEW M3 ( 21392 34920 ) ( 23368 * ) - NEW M2 ( 21392 34920 ) VIA23SQ_C W - NEW M1 ( 21392 35072 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n1 - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ Q ) - ( U0_UART_RX/U0_data_sampling/U63 A2 ) - ( U0_UART_RX/U0_data_sampling/U60 A2 ) - + ROUTED M1 ( 23368 37352 ) VIA12SQ_C ( * 39176 ) VIA23SQ_C W ( 26256 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 27776 40392 ) VIA12SQ_C ( * 41000 ) VIA23SQ_C W - NEW M3 ( 26256 41000 ) ( 27776 * ) - NEW M2 ( 26256 41000 ) VIA23SQ_C W - NEW M2 ( 26256 39176 ) ( * 41000 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n2 - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ Q ) - ( U0_UART_RX/U0_data_sampling/U63 A1 ) - ( U0_UART_RX/U0_data_sampling/U45 A2 ) - + ROUTED M1 ( 25222 38872 ) ( 26104 * ) - NEW M1 ( 28080 43736 ) VIA12SQ_C W VIA23SQ_C W - NEW M3 ( 26104 43736 ) ( 28080 * ) - NEW M2 ( 26104 43736 ) VIA23SQ_C W - NEW M2 ( 26104 38872 ) ( * 43736 ) - NEW M1 ( 26104 38872 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n3 - ( U0_UART_RX/U0_data_sampling/U12 Y ) - ( U0_UART_RX/U0_data_sampling/U15 A2 ) - ( U0_UART_RX/U0_data_sampling/U14 A1 ) - ( U0_UART_RX/U0_data_sampling/U6 A ) - + ROUTED M1 ( 3304 30664 ) VIA12SQ_C ( 3456 * ) - NEW M1 ( 5584 27624 ) VIA12SQ_C ( * 28840 ) VIA23SQ_C W - NEW M3 ( 3608 28840 ) ( 5584 * ) - NEW M2 ( 3608 28840 ) VIA23SQ_C W - NEW M2 ( 3456 28840 ) ( * 30664 ) - NEW M2 ( 3456 30664 ) ( 3912 * ) VIA12SQ_C - NEW M1 ( 3548 28840 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n4 - ( U0_UART_RX/U0_data_sampling/U14 Y ) - ( U0_UART_RX/U0_data_sampling/U17 A1 ) - ( U0_UART_RX/U0_data_sampling/U16 A2 ) - ( U0_UART_RX/U0_data_sampling/U15 A3 ) - + ROUTED M1 ( 4520 29600 ) VIA12SQ_C ( * 31272 ) VIA12SQ_C - NEW M1 ( 4672 28536 ) VIA12SQ_C - NEW M1 ( 6192 28840 ) VIA12SQ_C ( * 29448 ) VIA23SQ_C W - NEW M3 ( 4672 29448 ) ( 6192 * ) - NEW M2 ( 4672 29448 ) VIA23SQ_C W - NEW M2 ( 4672 28536 ) ( * 29448 ) - NEW M1 ( 6344 27016 ) VIA12SQ_C W ( * 27928 ) VIA23SQ_C W - NEW M3 ( 4672 27928 ) ( 6344 * ) - NEW M2 ( 4672 27928 ) VIA23SQ_C W - NEW M2 ( 4672 27928 ) ( * 28536 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n5 - ( U0_UART_RX/U0_data_sampling/U17 Y ) - ( U0_UART_RX/U0_data_sampling/U18 A1 ) - + ROUTED M1 ( 6496 27472 ) ( 6952 * ) VIA12SQ_C ( 7864 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n6 - ( U0_UART_RX/U0_data_sampling/U6 Y ) - ( U0_UART_RX/U0_data_sampling/U13 A3 ) - + ROUTED M1 ( 3304 31272 ) VIA12SQ_C ( 3760 * ) - NEW M2 ( 3760 31272 ) ( * 31576 ) - NEW M2 ( 3760 31576 ) ( 3912 * ) VIA12SQ_C ( 4186 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n11 - ( U0_UART_RX/U0_data_sampling/U10 Y ) - ( U0_UART_RX/U0_data_sampling/U17 A2 ) - ( U0_UART_RX/U0_data_sampling/U16 A1 ) - + ROUTED M1 ( 6344 21240 ) VIA12SQ_C ( 6496 * ) - NEW M2 ( 6496 21240 ) ( * 26864 ) - NEW M1 ( 6496 28688 ) VIA12SQ_C - NEW M2 ( 6496 26864 ) ( * 28688 ) - NEW M2 ( 6192 26864 ) ( 6496 * ) - NEW M2 ( 6192 26864 ) ( * 27320 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n12 - ( U0_UART_RX/U0_data_sampling/U20 Y ) - ( U0_UART_RX/U0_data_sampling/U23 A2 ) - ( U0_UART_RX/U0_data_sampling/U22 A1 ) - ( U0_UART_RX/U0_data_sampling/U5 A ) - + ROUTED M1 ( 3486 37352 ) ( 3912 * ) VIA12SQ_C ( * 37960 ) - NEW M1 ( 5280 36136 ) VIA12SQ_C ( * 37960 ) VIA23SQ_C W - NEW M3 ( 3912 37960 ) ( 5280 * ) - NEW M2 ( 3912 37960 ) VIA23SQ_C W - NEW M1 ( 3456 38872 ) ( 4490 * ) - NEW M1 ( 3456 38872 ) VIA12SQ_C - NEW M2 ( 3912 37960 ) ( * 38568 ) - NEW M2 ( 3456 38568 ) ( 3912 * ) - NEW M2 ( 3456 38568 ) ( * 38872 ) - NEW M1 ( 3396 40696 ) VIA12SQ_C_1_2 - NEW M2 ( 3456 38872 ) ( * 40696 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n13 - ( U0_UART_RX/U0_data_sampling/U22 Y ) - ( U0_UART_RX/U0_data_sampling/U25 A1 ) - ( U0_UART_RX/U0_data_sampling/U24 A2 ) - ( U0_UART_RX/U0_data_sampling/U23 A3 ) - + ROUTED M1 ( 4520 41000 ) VIA12SQ_C ( * 42216 ) - NEW M2 ( 4520 42216 ) ( 4672 * ) - NEW M2 ( 4672 42216 ) ( 5128 * ) - NEW M1 ( 5128 38264 ) VIA12SQ_C ( * 42216 ) - NEW M1 ( 5128 43736 ) ( 6010 * ) - NEW M1 ( 5128 43736 ) VIA12SQ_C - NEW M2 ( 5128 42216 ) ( * 43736 ) - NEW M1 ( 4672 42216 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n14 - ( U0_UART_RX/U0_data_sampling/U25 Y ) - ( U0_UART_RX/U0_data_sampling/U26 A1 ) - + ROUTED M1 ( 6227 43888 ) VIA12SQ_C W ( * 44040 ) VIA23SQ_C W ( 8320 * ) VIA23SQ_C W - NEW M1 ( 8320 44192 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n15 - ( U0_UART_RX/U0_data_sampling/U5 Y ) - ( U0_UART_RX/U0_data_sampling/U21 A3 ) - + ROUTED M1 ( 3456 36592 ) ( 3760 * ) VIA12SQ_C - NEW M2 ( 3760 34920 ) ( * 36592 ) - NEW M1 ( 3760 34920 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n16 - ( U0_UART_RX/U0_data_sampling/U4 Y ) - ( U0_UART_RX/U0_data_sampling/U25 A2 ) - ( U0_UART_RX/U0_data_sampling/U24 A1 ) - + ROUTED M1 ( 6648 42023 ) VIA12SQ_C - NEW M2 ( 6648 41608 ) ( * 42023 ) - NEW M2 ( 6648 41608 ) VIA23SQ_C W - NEW M3 ( 5736 41608 ) ( 6648 * ) - NEW M3 ( 5736 41608 ) ( * 41912 ) VIA23SQ_C W ( * 44040 ) VIA12SQ_C - NEW M3 ( 4976 41912 ) ( 5736 * ) - NEW M2 ( 4976 41912 ) VIA23SQ_C W - NEW M1 ( 4976 42064 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n17 - ( U0_UART_RX/U0_data_sampling/U36 Y ) - ( U0_UART_RX/U0_data_sampling/U27 A1 ) - + ROUTED M1 ( 20024 35376 ) VIA12SQ_C ( * 36744 ) VIA23SQ_C W ( 24584 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n18 - ( U0_UART_RX/U0_data_sampling/U61 Y ) - ( U0_UART_RX/U0_data_sampling/U46 A1 ) - ( U0_UART_RX/U0_data_sampling/U37 A2 ) - ( U0_UART_RX/U0_data_sampling/U27 A2 ) - + ROUTED M1 ( 21088 35832 ) VIA12SQ_C ( * 37656 ) - NEW M2 ( 21088 37656 ) ( 21240 * ) - NEW M1 ( 22760 39176 ) VIA12SQ_C - NEW M2 ( 22760 38568 ) ( * 39176 ) - NEW M2 ( 22760 38568 ) VIA23SQ_C W - NEW M3 ( 21240 38568 ) ( 22760 * ) - NEW M2 ( 21240 37656 ) ( * 38568 ) VIA23SQ_C W - NEW M1 ( 27016 37529 ) VIA12SQ_C - NEW M2 ( 27016 37656 ) VIA23SQ_C W - NEW M3 ( 21240 37656 ) ( 27016 * ) - NEW M2 ( 21240 37656 ) VIA23SQ_C W - NEW M3 ( 19168 38568 ) ( 21240 * ) - NEW M2 ( 19168 38568 ) VIA23SQ_C W - NEW M1 ( 19168 38720 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n19 - ( U0_UART_RX/U0_data_sampling/U28 Y ) - ( U0_UART_RX/U0_data_sampling/U27 S0 ) - + ROUTED M1 ( 20328 35528 ) VIA12SQ_C - NEW M2 ( 20328 34920 ) ( * 35528 ) - NEW M2 ( 20328 34920 ) VIA23SQ_C W - NEW M3 ( 14248 34920 ) ( 20328 * ) - NEW M2 ( 14248 34920 ) VIA23SQ_C W - NEW M2 ( 14248 34920 ) ( * 35224 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n20 - ( U0_UART_RX/U0_data_sampling/U31 Y ) - ( U0_UART_RX/U0_data_sampling/U28 A1 ) - + ROUTED M1 ( 12576 35376 ) ( 12850 * ) - NEW M1 ( 12576 35376 ) VIA12SQ_C - NEW M2 ( 12576 32944 ) ( * 35376 ) - NEW M1 ( 12576 32944 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n21 - ( U0_UART_RX/U0_data_sampling/U30 Y ) - ( U0_UART_RX/U0_data_sampling/U28 A2 ) - + ROUTED M1 ( 13488 38720 ) ( 14096 * ) - NEW M1 ( 13488 38720 ) VIA12SQ_C - NEW M2 ( 13488 35680 ) ( * 38720 ) - NEW M2 ( 13032 35680 ) ( 13488 * ) - NEW M1 ( 13032 35680 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n22 - ( U0_UART_RX/U0_data_sampling/U38 Y ) - ( U0_UART_RX/U0_data_sampling/U37 S0 ) - ( U0_UART_RX/U0_data_sampling/U28 A3 ) - + ROUTED M1 ( 13336 35832 ) VIA12SQ_C ( * 38264 ) VIA23SQ_C W - NEW M1 ( 22304 38872 ) VIA12SQ_C - NEW M2 ( 22304 38264 ) ( * 38872 ) - NEW M2 ( 22304 38264 ) VIA23SQ_C W - NEW M3 ( 13336 38264 ) ( 22304 * ) - NEW M1 ( 12728 38264 ) VIA12SQ_C VIA23SQ_C W ( 13336 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n26 - ( U0_UART_RX/U0_data_sampling/U29 Y ) - ( U0_UART_RX/U0_data_sampling/U28 A4 ) - + ROUTED M1 ( 11512 34616 ) VIA12SQ_C ( * 34920 ) VIA23SQ_C W ( 13488 * ) VIA23SQ_C W ( * 35528 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n27 - ( U0_UART_RX/U0_data_sampling/U47 Y ) - ( U0_UART_RX/U0_data_sampling/U46 S0 ) - ( U0_UART_RX/U0_data_sampling/U39 A3 ) - ( U0_UART_RX/U0_data_sampling/U30 A1 ) - + ROUTED M1 ( 13944 39176 ) VIA12SQ_C W - NEW M2 ( 13944 38872 ) ( * 39176 ) - NEW M1 ( 19720 38872 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 13944 38872 ) ( 19720 * ) - NEW M2 ( 13944 38872 ) VIA23SQ_C W - NEW M1 ( 13032 37048 ) ( 13944 * ) VIA12SQ_C ( * 38872 ) - NEW M1 ( 11208 37034 ) VIA12SQ_C - NEW M2 ( 11208 37048 ) VIA23SQ_C W ( 13032 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n28 - ( U0_UART_RX/U0_data_sampling/U51 Y ) - ( U0_UART_RX/U0_data_sampling/U48 A2 ) - ( U0_UART_RX/U0_data_sampling/U39 A4 ) - ( U0_UART_RX/U0_data_sampling/U30 A2 ) - + ROUTED M1 ( 13792 38872 ) VIA12SQ_C W - NEW M2 ( 13792 38568 ) ( * 38872 ) - NEW M1 ( 13214 37352 ) ( 13640 * ) VIA12SQ_C ( * 38568 ) - NEW M2 ( 13640 38568 ) ( 13792 * ) - NEW M1 ( 9688 39176 ) VIA12SQ_C - NEW M2 ( 9688 38568 ) ( * 39176 ) - NEW M2 ( 9688 38568 ) VIA23SQ_C W ( 13792 * ) VIA23SQ_C W - NEW M3 ( 13792 38568 ) ( 14552 * ) VIA23SQ_C W - NEW M1 ( 14552 38720 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n29 - ( U0_UART_RX/U0_data_sampling/U35 Y ) - ( U0_UART_RX/U0_data_sampling/U31 A1 ) - + ROUTED M1 ( 9688 32336 ) ( 12272 * ) VIA12SQ_C ( 12728 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n30 - ( U0_UART_RX/U0_data_sampling/U34 Y ) - ( U0_UART_RX/U0_data_sampling/U31 A2 ) - + ROUTED M1 ( 12880 32184 ) VIA12SQ_C W VIA23SQ_C W ( 13640 * ) VIA23SQ_C W - NEW M2 ( 13640 31272 ) ( * 32184 ) - NEW M1 ( 13640 31272 ) VIA12SQ_C - NEW M1 ( 13640 31272 ) ( 14096 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n31 - ( U0_UART_RX/U0_data_sampling/U33 Y ) - ( U0_UART_RX/U0_data_sampling/U31 A3 ) - + ROUTED M1 ( 13062 32336 ) ( 13336 * ) VIA12SQ_C - NEW M2 ( 13336 29600 ) ( * 32336 ) - NEW M1 ( 13336 29600 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n32 - ( U0_UART_RX/U0_data_sampling/U32 Y ) - ( U0_UART_RX/U0_data_sampling/U31 A4 ) - + ROUTED M1 ( 12272 30512 ) ( 13032 * ) VIA12SQ_C ( * 32032 ) VIA12SQ_C ( * 32184 ) - NEW M1 ( 13032 32184 ) ( 13184 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n33 - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ Q ) - ( U0_UART_RX/U0_data_sampling/U63 A4 ) - ( U0_UART_RX/U0_data_sampling/U36 A2 ) - + ROUTED M1 ( 27016 36288 ) VIA12SQ_C W - NEW M2 ( 26408 36288 ) ( 27016 * ) - NEW M2 ( 26408 36288 ) ( * 38264 ) - NEW M1 ( 26408 38720 ) VIA12SQ_C - NEW M2 ( 26408 38264 ) ( * 38720 ) - NEW M1 ( 25344 37352 ) VIA12SQ_C ( * 38264 ) VIA23SQ_C W ( 26408 * ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n34 - ( U0_UART_RX/U0_data_sampling/U45 Y ) - ( U0_UART_RX/U0_data_sampling/U37 A1 ) - + ROUTED M1 ( 23672 38720 ) ( 24402 * ) - NEW M1 ( 23672 38720 ) VIA12SQ_C - NEW M2 ( 23672 38872 ) VIA23SQ_C W - NEW M3 ( 21752 38872 ) ( 23672 * ) - NEW M2 ( 21752 38872 ) VIA23SQ_C W - NEW M1 ( 21752 38720 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n35 - ( U0_UART_RX/U0_data_sampling/U44 Y ) - ( U0_UART_RX/U0_data_sampling/U38 A1 ) - + ROUTED M1 ( 12272 39176 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 8776 39176 ) ( 12272 * ) - NEW M2 ( 8776 39176 ) VIA23SQ_C W - NEW M2 ( 8776 37808 ) ( * 39176 ) - NEW M1 ( 8776 37808 ) VIA12SQ_C - NEW M1 ( 8624 37808 ) ( 8776 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n36 - ( U0_UART_RX/U0_data_sampling/U43 Y ) - ( U0_UART_RX/U0_data_sampling/U38 A2 ) - + ROUTED M1 ( 12120 38872 ) VIA12SQ_C ( * 41760 ) VIA23SQ_C W ( 13032 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n37 - ( U0_UART_RX/U0_data_sampling/U42 Y ) - ( U0_UART_RX/U0_data_sampling/U38 A3 ) - + ROUTED M1 ( 11056 39936 ) ( 11816 * ) VIA12SQ_C - NEW M2 ( 11816 39176 ) ( * 39936 ) - NEW M1 ( 11816 39176 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n38 - ( U0_UART_RX/U0_data_sampling/U39 Y ) - ( U0_UART_RX/U0_data_sampling/U38 A4 ) - + ROUTED M1 ( 11816 38872 ) VIA12SQ_C ( 11968 * ) - NEW M2 ( 11968 37960 ) ( * 38872 ) - NEW M1 ( 11968 37960 ) VIA12SQ_C - NEW M1 ( 11968 37960 ) ( 12272 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n39 - ( U0_UART_RX/U0_data_sampling/U41 Y ) - ( U0_UART_RX/U0_data_sampling/U39 A1 ) - + ROUTED M1 ( 9232 35528 ) VIA12SQ_C VIA23SQ_C W ( 12728 * ) VIA23SQ_C W ( * 37048 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n40 - ( U0_UART_RX/U0_data_sampling/U40 Y ) - ( U0_UART_RX/U0_data_sampling/U39 A2 ) - + ROUTED M1 ( 12272 36288 ) VIA12SQ_C ( * 37352 ) - NEW M2 ( 12272 37352 ) ( 12728 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n41 - ( U0_UART_RX/U0_data_sampling/U55 Y ) - ( U0_UART_RX/U0_data_sampling/U54 A1 ) - ( U0_UART_RX/U0_data_sampling/U40 A1 ) - + ROUTED M1 ( 13336 34160 ) VIA12SQ_C - NEW M1 ( 10904 35376 ) VIA12SQ_C - NEW M2 ( 10904 34616 ) ( * 35376 ) - NEW M2 ( 10904 34616 ) VIA23SQ_C W ( 13336 * ) - NEW M3 ( 13336 34312 ) ( * 34616 ) - NEW M2 ( 13336 34312 ) VIA23SQ_C W - NEW M1 ( 13184 30857 ) VIA12SQ_C ( * 34312 ) - NEW M2 ( 13184 34312 ) ( 13336 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n42 - ( U0_UART_RX/U0_data_sampling/U57 Y ) - ( U0_UART_RX/U0_data_sampling/U56 A1 ) - ( U0_UART_RX/U0_data_sampling/U41 A1 ) - + ROUTED M1 ( 7408 34201 ) VIA12SQ_C ( * 35224 ) - NEW M2 ( 7408 35224 ) ( 7560 * ) - NEW M2 ( 7560 35224 ) ( * 35376 ) VIA12SQ_C - NEW M2 ( 7560 35376 ) ( * 35832 ) VIA23SQ_C W - NEW M3 ( 4672 35832 ) ( 7560 * ) - NEW M2 ( 4672 35832 ) VIA23SQ_C W - NEW M2 ( 4672 35832 ) ( * 37504 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n43 - ( U0_UART_RX/U0_data_sampling/U53 Y ) - ( U0_UART_RX/U0_data_sampling/U52 A1 ) - ( U0_UART_RX/U0_data_sampling/U42 A1 ) - + ROUTED M1 ( 8320 42064 ) VIA12SQ_C - NEW M2 ( 8320 41000 ) ( * 42064 ) - NEW M2 ( 8320 41000 ) VIA23SQ_C W ( 9384 * ) VIA23SQ_C W ( 9688 * ) - NEW M2 ( 9688 40848 ) ( * 41000 ) - NEW M1 ( 9688 40848 ) VIA12SQ_C - NEW M2 ( 9688 40392 ) ( * 40848 ) - NEW M2 ( 9384 40392 ) ( 9688 * ) - NEW M2 ( 9384 35984 ) ( * 40392 ) - NEW M1 ( 9384 35984 ) VIA12SQ_C - NEW M1 ( 9384 35984 ) ( 9536 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n44 - ( U0_UART_RX/U0_data_sampling/U59 Y ) - ( U0_UART_RX/U0_data_sampling/U58 A1 ) - ( U0_UART_RX/U0_data_sampling/U43 A1 ) - + ROUTED M1 ( 11664 42064 ) VIA12SQ_C ( * 42520 ) - NEW M1 ( 12576 40889 ) VIA12SQ_C ( * 42520 ) VIA23SQ_C W - NEW M3 ( 11664 42520 ) ( 12576 * ) - NEW M2 ( 11664 42520 ) VIA23SQ_C W - NEW M1 ( 11664 44192 ) VIA12SQ_C - NEW M2 ( 11664 42520 ) ( * 44192 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n45 - ( U0_UART_RX/U0_data_sampling/U50 Y ) - ( U0_UART_RX/U0_data_sampling/U49 A1 ) - ( U0_UART_RX/U0_data_sampling/U44 A1 ) - + ROUTED M1 ( 8928 37504 ) VIA12SQ_C - NEW M2 ( 8928 37656 ) VIA23SQ_C W - NEW M3 ( 7256 37656 ) ( 8928 * ) - NEW M1 ( 6496 40848 ) VIA12SQ_C - NEW M2 ( 6496 37656 ) ( * 40848 ) - NEW M2 ( 6496 37656 ) VIA23SQ_C W ( 7256 * ) - NEW M1 ( 7256 37504 ) VIA12SQ_C - NEW M2 ( 7256 37656 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n46 - ( U0_UART_RX/U0_data_sampling/U60 Y ) - ( U0_UART_RX/U0_data_sampling/U46 A2 ) - + ROUTED M1 ( 20176 39176 ) VIA12SQ_C VIA23SQ_C W ( 22608 * ) VIA23SQ_C W - NEW M2 ( 22608 37960 ) ( * 39176 ) - NEW M1 ( 22608 37960 ) VIA12SQ_C - NEW M1 ( 22608 37960 ) ( 22912 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n47 - ( U0_UART_RX/U0_data_sampling/U58 Y ) - ( U0_UART_RX/U0_data_sampling/U47 A1 ) - + ROUTED M1 ( 10752 37200 ) VIA12SQ_C - NEW M2 ( 10296 37200 ) ( 10752 * ) - NEW M2 ( 10296 37200 ) ( * 43280 ) VIA12SQ_C ( 10448 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n48 - ( U0_UART_RX/U0_data_sampling/U56 Y ) - ( U0_UART_RX/U0_data_sampling/U47 A2 ) - + ROUTED M1 ( 10904 37352 ) VIA12SQ_C - NEW M2 ( 10904 36744 ) ( * 37352 ) - NEW M2 ( 10904 36744 ) VIA23SQ_C W - NEW M3 ( 6040 36744 ) ( 10904 * ) - NEW M2 ( 6040 36744 ) VIA23SQ_C W - NEW M1 ( 6040 36744 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n49 - ( U0_UART_RX/U0_data_sampling/U54 Y ) - ( U0_UART_RX/U0_data_sampling/U47 A3 ) - + ROUTED M1 ( 11816 34616 ) ( 12120 * ) - NEW M1 ( 11816 34616 ) VIA12SQ_C ( * 37200 ) VIA12SQ_C - NEW M1 ( 11056 37200 ) ( 11816 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n50 - ( U0_UART_RX/U0_data_sampling/U48 Y ) - ( U0_UART_RX/U0_data_sampling/U47 A4 ) - + ROUTED M1 ( 11208 37352 ) VIA12SQ_C ( * 38264 ) VIA12SQ_C - NEW M1 ( 10296 38264 ) ( 11208 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n51 - ( U0_UART_RX/U0_data_sampling/U52 Y ) - ( U0_UART_RX/U0_data_sampling/U48 A1 ) - + ROUTED M1 ( 9840 38872 ) VIA12SQ_C ( * 41760 ) VIA12SQ_C - NEW M1 ( 9536 41760 ) ( 9840 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n52 - ( U0_UART_RX/U0_data_sampling/U49 Y ) - ( U0_UART_RX/U0_data_sampling/U48 A3 ) - + ROUTED M1 ( 8624 38872 ) ( 9506 * ) - NEW M1 ( 8624 38872 ) VIA12SQ_C ( * 39936 ) VIA12SQ_C - NEW M1 ( 7864 39936 ) ( 8624 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n53 - ( U0_UART_RX/U0_data_sampling/U63 Y ) - ( U0_UART_RX/U0_data_sampling/U62 A2 ) - + ROUTED M1 ( 27056 38872 ) ( 28080 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/n54 - ( U0_UART_RX/U0_data_sampling/U64 Y ) - ( U0_UART_RX/U0_data_sampling/U63 A3 ) - + ROUTED M1 ( 26712 38264 ) VIA12SQ_C ( * 41608 ) VIA12SQ_C ( 27776 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[4] - ( U0_UART_RX/U0_data_sampling/U18 Y ) - ( U0_UART_RX/U0_data_sampling/U43 A2 ) - ( U0_UART_RX/U0_data_sampling/U26 A2 ) - ( U0_UART_RX/U0_data_sampling/U19 A2 ) - + ROUTED M1 ( 9080 28840 ) VIA12SQ_C - NEW M1 ( 8016 44040 ) VIA12SQ_C - NEW M2 ( 8016 42824 ) ( * 44040 ) - NEW M2 ( 8016 42824 ) VIA23SQ_C W ( 9080 * ) VIA23SQ_C W - NEW M2 ( 9080 42216 ) ( * 42824 ) - NEW M1 ( 11360 42216 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 9080 42216 ) ( 11360 * ) - NEW M2 ( 9080 42216 ) VIA23SQ_C W - NEW M1 ( 9080 27776 ) VIA12SQ_C ( * 28840 ) - NEW M2 ( 9080 28840 ) ( * 42216 ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[3] - ( U0_UART_RX/U0_data_sampling/U16 Y ) - ( U0_UART_RX/U0_data_sampling/U42 A2 ) - ( U0_UART_RX/U0_data_sampling/U4 A ) - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_3 A0 ) - + ROUTED M1 ( 8168 30664 ) VIA12SQ_C - NEW M1 ( 6952 42216 ) VIA12SQ_C - NEW M2 ( 6952 41304 ) ( * 42216 ) - NEW M2 ( 6952 41304 ) VIA23SQ_C W ( 8168 * ) - NEW M3 ( 8168 40696 ) ( * 41304 ) - NEW M1 ( 9384 40696 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 8168 40696 ) ( 9384 * ) - NEW M2 ( 8168 40696 ) VIA23SQ_C W - NEW M2 ( 8168 30664 ) ( * 40696 ) - NEW M2 ( 8168 29600 ) ( * 30664 ) - NEW M1 ( 8168 29600 ) VIA12SQ_C - NEW M1 ( 7712 29600 ) ( 8168 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[2] - ( U0_UART_RX/U0_data_sampling/U15 Y ) - ( U0_UART_RX/U0_data_sampling/U44 A2 ) - ( U0_UART_RX/U0_data_sampling/U23 A1 ) - ( U0_UART_RX/U0_data_sampling/U22 A2 ) - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_2 A0 ) - + ROUTED M1 ( 3760 40873 ) VIA12BAR_C - NEW M2 ( 3760 39024 ) ( * 40873 ) - NEW M1 ( 3760 39024 ) VIA12SQ_C - NEW M1 ( 3760 39024 ) ( 4708 * ) - NEW M1 ( 4976 31120 ) VIA12SQ_C ( * 32184 ) - NEW M1 ( 6952 37352 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 4976 37352 ) ( 6952 * ) - NEW M2 ( 4976 37352 ) VIA23SQ_C W - NEW M2 ( 4976 32184 ) ( * 37352 ) - NEW M1 ( 4824 39024 ) VIA12SQ_C - NEW M2 ( 4824 37352 ) ( * 38999 ) - NEW M2 ( 4824 37352 ) ( 4976 * ) - NEW M2 ( 4976 32184 ) ( 5584 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[1] - ( U0_UART_RX/U0_data_sampling/U13 Y ) - ( U0_UART_RX/U0_data_sampling/U41 A2 ) - ( U0_UART_RX/U0_data_sampling/U21 A1 ) - ( U0_UART_RX/U0_data_sampling/U20 A1 ) - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_1 A0 ) - + ROUTED M1 ( 4824 34008 ) VIA12SQ_C - NEW M2 ( 4672 34008 ) ( 4824 * ) - NEW M1 ( 4672 32944 ) VIA12SQ_C ( * 34008 ) - NEW M1 ( 7256 35528 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 5888 35528 ) ( 7256 * ) - NEW M2 ( 4672 34008 ) ( * 35528 ) VIA23SQ_C W ( 5888 * ) VIA23SQ_C W - NEW M1 ( 5888 35680 ) VIA12SQ_C - NEW M3 ( 3912 35528 ) ( 4672 * ) - NEW M2 ( 3912 35528 ) VIA23SQ_C W - NEW M1 ( 3912 35680 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges[0] - ( U0_UART_RX/U0_data_sampling/U11 Y ) - ( U0_UART_RX/U0_data_sampling/U40 A2 ) - ( U0_UART_RX/U0_data_sampling/U21 A2 ) - ( U0_UART_RX/U0_data_sampling/U20 A2 ) - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_1 B0 ) - + ROUTED M1 ( 5280 34160 ) VIA12SQ_C ( * 34920 ) - NEW M1 ( 3638 34201 ) ( 4216 * ) VIA12SQ_C ( * 34920 ) - NEW M1 ( 5584 35503 ) VIA12BAR_C - NEW M2 ( 5584 34920 ) ( * 35503 ) - NEW M2 ( 5280 34920 ) ( 5584 * ) - NEW M1 ( 4216 35528 ) VIA12SQ_C - NEW M2 ( 4216 34920 ) ( * 35528 ) - NEW M1 ( 10600 35528 ) VIA12SQ_C - NEW M2 ( 10600 34920 ) ( * 35528 ) - NEW M2 ( 10600 34920 ) VIA23SQ_C W - NEW M3 ( 5280 34920 ) ( 10600 * ) - NEW M2 ( 5280 34920 ) VIA23SQ_C W - NEW M3 ( 4216 34920 ) ( 5280 * ) - NEW M2 ( 4216 34920 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_p1[4] - ( U0_UART_RX/U0_data_sampling/U19 Y ) - ( U0_UART_RX/U0_data_sampling/U33 A2 ) - + ROUTED M1 ( 11816 28840 ) VIA12SQ_C - NEW M2 ( 11208 28840 ) ( 11816 * ) - NEW M1 ( 11208 28840 ) VIA12SQ_C - NEW M1 ( 10904 28840 ) ( 11208 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_p1[3] - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_3 SO ) - ( U0_UART_RX/U0_data_sampling/U32 A2 ) - + ROUTED M1 ( 10600 30664 ) VIA12SQ_C - NEW M2 ( 10600 30512 ) ( * 30664 ) - NEW M2 ( 9992 30512 ) ( 10600 * ) - NEW M1 ( 9992 30512 ) VIA12SQ_C - NEW M1 ( 9688 30512 ) ( 9992 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_p1[2] - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_2 SO ) - ( U0_UART_RX/U0_data_sampling/U29 A1 ) - + ROUTED M1 ( 7104 32361 ) VIA12SQ_C ( * 32792 ) VIA23SQ_C W ( 10144 * ) VIA23SQ_C W ( * 34160 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_p1[1] - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_1 SO ) - ( U0_UART_RX/U0_data_sampling/U35 A2 ) - + ROUTED M1 ( 6344 33831 ) VIA12SQ_C - NEW M2 ( 6344 32184 ) ( * 33831 ) - NEW M2 ( 6344 32184 ) VIA23SQ_C W ( 8016 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_n1[4] - ( U0_UART_RX/U0_data_sampling/U26 Y ) - ( U0_UART_RX/U0_data_sampling/U58 A2 ) - + ROUTED M1 ( 9688 43888 ) VIA12SQ_C - NEW M2 ( 9688 44040 ) VIA23SQ_C W ( 12120 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_n1[3] - ( U0_UART_RX/U0_data_sampling/U24 Y ) - ( U0_UART_RX/U0_data_sampling/U52 A2 ) - + ROUTED M1 ( 7864 42216 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 6344 42216 ) ( 7864 * ) - NEW M2 ( 6344 42216 ) VIA23SQ_C W - NEW M1 ( 6344 42368 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_n1[2] - ( U0_UART_RX/U0_data_sampling/U23 Y ) - ( U0_UART_RX/U0_data_sampling/U49 A2 ) - + ROUTED M1 ( 5432 39632 ) ( 6192 * ) VIA12SQ_C ( * 40696 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/half_edges_n1[1] - ( U0_UART_RX/U0_data_sampling/U21 Y ) - ( U0_UART_RX/U0_data_sampling/U56 A2 ) - + ROUTED M1 ( 4368 37200 ) ( * 37352 ) - NEW M1 ( 4368 37200 ) VIA12SQ_C - NEW M2 ( 3304 37200 ) ( 4368 * ) - NEW M2 ( 3304 36288 ) ( * 37200 ) - NEW M1 ( 3304 36288 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/add_21_carry[4] - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_3 C1 ) - ( U0_UART_RX/U0_data_sampling/U19 A1 ) - + ROUTED M1 ( 9384 30360 ) VIA12SQ_C - NEW M2 ( 9384 28688 ) ( * 30360 ) - NEW M1 ( 9384 28688 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/add_21_carry[3] - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_2 C1 ) - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_3 B0 ) - + ROUTED M1 ( 6800 32488 ) VIA12SQ_C - NEW M2 ( 6800 31272 ) ( * 32488 ) - NEW M2 ( 6800 31272 ) VIA23SQ_C W ( 8624 * ) VIA23SQ_C W - NEW M2 ( 8624 30816 ) ( * 31272 ) - NEW M1 ( 8624 30816 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_data_sampling/add_21_carry[2] - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_1 C1 ) - ( U0_UART_RX/U0_data_sampling/add_21_U1_1_2 B0 ) - + ROUTED M1 ( 6040 33704 ) VIA12SQ_C - NEW M2 ( 6040 32032 ) ( * 33704 ) - NEW M1 ( 6040 32032 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N2 - ( U0_UART_RX/U0_deserializer/U19 Y ) - ( U0_UART_RX/U0_deserializer/U41 A1 ) - ( U0_UART_RX/U0_deserializer/U7 A ) - + ROUTED M1 ( 9688 15464 ) VIA12SQ_C ( 9840 * ) - NEW M2 ( 9840 15464 ) ( * 16680 ) - NEW M1 ( 9992 16832 ) VIA12SQ_C - NEW M2 ( 9992 16680 ) ( * 16832 ) - NEW M2 ( 9840 16680 ) ( 9992 * ) - NEW M1 ( 12120 17288 ) VIA12SQ_C - NEW M2 ( 12120 16680 ) ( * 17288 ) - NEW M2 ( 12120 16680 ) VIA23SQ_C W - NEW M3 ( 9840 16680 ) ( 12120 * ) - NEW M2 ( 9840 16680 ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N3 - ( U0_UART_RX/U0_deserializer/U29 Y ) - ( U0_UART_RX/U0_deserializer/U36 A1 ) - + ROUTED M1 ( 11208 15312 ) VIA12SQ_C - NEW M2 ( 11208 15464 ) VIA23SQ_C W - NEW M3 ( 6384 15464 ) ( 11208 * ) - NEW M2 ( 6384 15464 ) VIA23SQ_C W - NEW M1 ( 6384 15464 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N4 - ( U0_UART_RX/U0_deserializer/U31 Y ) - ( U0_UART_RX/U0_deserializer/U35 A1 ) - + ROUTED M1 ( 6496 13640 ) VIA12SQ_C VIA23SQ_C W ( 9080 * ) VIA23SQ_C W ( * 14096 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N5 - ( U0_UART_RX/U0_deserializer/U32 Y ) - ( U0_UART_RX/U0_deserializer/U37 A1 ) - + ROUTED M1 ( 5280 12728 ) VIA12SQ_C VIA23SQ_C W ( 10144 * ) VIA23SQ_C W - NEW M2 ( 10144 11968 ) ( * 12728 ) - NEW M1 ( 10144 11968 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N6 - ( U0_UART_RX/U0_deserializer/U34 Y ) - ( U0_UART_RX/U0_deserializer/U39 A1 ) - + ROUTED M1 ( 8776 11816 ) VIA12SQ_C VIA23SQ_C W ( 14704 * ) VIA23SQ_C W - NEW M1 ( 14704 11968 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/N7 - ( U0_UART_RX/U0_deserializer/U44 Y ) - ( U0_UART_RX/U0_deserializer/U9 A1 ) - + ROUTED M1 ( 35224 22456 ) ( 35954 * ) - NEW M1 ( 35224 22456 ) VIA12SQ_C - NEW M2 ( 35224 21848 ) ( * 22456 ) - NEW M2 ( 35224 21848 ) VIA23SQ_C W - NEW M3 ( 34312 21848 ) ( 35224 * ) - NEW M2 ( 34312 21848 ) VIA23SQ_C W - NEW M2 ( 34312 20328 ) ( * 21848 ) - NEW M2 ( 34312 20328 ) VIA23SQ_C W - NEW M3 ( 14400 20328 ) ( 34312 * ) - NEW M2 ( 14400 20328 ) VIA23SQ_C W - NEW M2 ( 14400 15616 ) ( * 20328 ) - NEW M1 ( 14400 15616 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n1 - ( U0_UART_RX/U0_deserializer/U9 Y ) - ( U0_UART_RX/U0_deserializer/U5 A ) - ( U0_UART_RX/U0_deserializer/U16 A1 ) - ( U0_UART_RX/U0_deserializer/U14 A1 ) - ( U0_UART_RX/U0_deserializer/U12 A1 ) - ( U0_UART_RX/U0_deserializer/U10 A1 ) - ( U0_UART_RX/U0_deserializer/U8 A1 ) - ( U0_UART_RX/U0_deserializer/U6 A1 ) - ( U0_UART_RX/U0_deserializer/U4 A1 ) - ( U0_UART_RX/U0_deserializer/U3 A1 ) - + ROUTED M1 ( 39024 42216 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 38568 42216 ) ( 39024 * ) - NEW M3 ( 38568 42216 ) VIA34SQ_C - NEW M4 ( 38568 40392 ) ( * 42216 ) - NEW M1 ( 37200 38872 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 38568 38872 ) VIA34SQ_C ( * 40392 ) - NEW M1 ( 37504 34008 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 36136 34008 ) ( 37504 * ) - NEW M3 ( 36136 34008 ) VIA34SQ_C - NEW M1 ( 35680 32184 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C - NEW M1 ( 35528 22912 ) ( 35832 * ) - NEW M1 ( 35528 22912 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C ( * 32184 ) - NEW M4 ( 35528 32184 ) ( 35680 * ) - NEW M4 ( 38264 42216 ) ( 38568 * ) - NEW M4 ( 38264 42216 ) ( * 44040 ) VIA34SQ_C - NEW M3 ( 37048 44040 ) ( 38264 * ) - NEW M2 ( 37048 44040 ) VIA23SQ_C W - NEW M1 ( 37048 44040 ) VIA12SQ_C - NEW M1 ( 36440 44040 ) ( 37048 * ) - NEW M3 ( 38568 40392 ) VIA34SQ_C - NEW M2 ( 38720 40392 ) VIA23SQ_C W - NEW M2 ( 38720 40392 ) ( * 40696 ) VIA12SQ_C - NEW M3 ( 37200 38872 ) ( 38391 * ) - NEW M1 ( 38416 38872 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 36136 38872 ) ( 37200 * ) - NEW M3 ( 36136 38872 ) VIA34SQ_C - NEW M4 ( 36136 36136 ) ( * 38872 ) - NEW M4 ( 36136 34008 ) ( * 36136 ) - NEW M4 ( 35832 34008 ) ( 36136 * ) - NEW M4 ( 35832 32184 ) ( * 34008 ) - NEW M4 ( 35680 32184 ) ( 35832 * ) - NEW M1 ( 34160 42216 ) VIA12SQ_C VIA23SQ_C W ( 35528 * ) VIA34SQ_C ( * 44040 ) VIA34SQ_C ( 36440 * ) VIA23SQ_C W VIA12SQ_C - NEW M3 ( 36136 36136 ) VIA34SQ_C - NEW M2 ( 36288 36136 ) VIA23SQ_C W - NEW M2 ( 36288 35528 ) ( * 36136 ) - NEW M1 ( 36288 35528 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n18 - ( U0_UART_RX/U0_deserializer/U3 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ D ) - + ROUTED M1 ( 29144 40696 ) VIA12SQ_C ( * 42672 ) VIA12SQ_C ( 33066 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n20 - ( U0_UART_RX/U0_deserializer/U4 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ D ) - + ROUTED M1 ( 29600 44040 ) VIA12SQ_C VIA23SQ_C W ( 35224 * ) VIA23SQ_C W - NEW M2 ( 35224 43584 ) ( * 44040 ) - NEW M1 ( 35224 43584 ) VIA12SQ_C - NEW M1 ( 35224 43584 ) ( 35498 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n22 - ( U0_UART_RX/U0_deserializer/U6 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ D ) - + ROUTED M1 ( 41152 40696 ) VIA12SQ_C ( * 41304 ) - NEW M2 ( 41000 41304 ) ( 41152 * ) - NEW M2 ( 41000 41304 ) ( * 41760 ) VIA12SQ_C - NEW M1 ( 39936 41760 ) ( 41000 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n24 - ( U0_UART_RX/U0_deserializer/U8 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ D ) - + ROUTED M1 ( 39632 41304 ) ( 40544 * ) VIA12SQ_C ( * 44344 ) - NEW M2 ( 40544 44344 ) ( 41152 * ) - NEW M2 ( 41152 44040 ) ( * 44344 ) - NEW M1 ( 41152 44040 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n26 - ( U0_UART_RX/U0_deserializer/U10 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ D ) - + ROUTED M1 ( 41152 38872 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 39368 38872 ) ( 41152 * ) - NEW M2 ( 39368 38872 ) VIA23SQ_C W - NEW M1 ( 39368 38872 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n28 - ( U0_UART_RX/U0_deserializer/U12 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ D ) - + ROUTED M1 ( 36288 37352 ) VIA12SQ_C ( * 38416 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n30 - ( U0_UART_RX/U0_deserializer/U14 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ D ) - + ROUTED M1 ( 37504 35528 ) VIA12SQ_C ( * 37048 ) VIA23SQ_C W - NEW M3 ( 35376 37048 ) ( 37504 * ) - NEW M2 ( 35376 37048 ) VIA23SQ_C W - NEW M2 ( 35376 36288 ) ( * 37048 ) - NEW M1 ( 35376 36288 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n32 - ( U0_UART_RX/U0_deserializer/U16 Y ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ D ) - + ROUTED M1 ( 38416 33248 ) ( 41000 * ) VIA12SQ_C - NEW M2 ( 41000 32184 ) ( * 33248 ) - NEW M1 ( 41000 32184 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n2 - ( U0_UART_RX/U0_deserializer/U18 Y ) - ( U0_UART_RX/U0_deserializer/U29 A2 ) - ( U0_UART_RX/U0_deserializer/U28 A1 ) - ( U0_UART_RX/U0_deserializer/U13 A ) - + ROUTED M1 ( 6496 18808 ) ( 6922 * ) - NEW M1 ( 6496 18808 ) VIA12SQ_C - NEW M2 ( 6496 18200 ) ( * 18808 ) - NEW M2 ( 6496 18200 ) VIA23SQ_C W - NEW M3 ( 5128 18200 ) ( 6496 * ) - NEW M2 ( 5128 18200 ) VIA23SQ_C W - NEW M2 ( 5128 17592 ) ( * 18200 ) - NEW M1 ( 5128 17592 ) VIA12SQ_C - NEW M1 ( 4064 15464 ) ( 5128 * ) - NEW M2 ( 5128 15464 ) ( * 17592 ) - NEW M1 ( 5128 15464 ) VIA12SQ_C - NEW M1 ( 5128 15464 ) ( 5402 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n3 - ( U0_UART_RX/U0_deserializer/U28 Y ) - ( U0_UART_RX/U0_deserializer/U31 A2 ) - ( U0_UART_RX/U0_deserializer/U30 A1 ) - ( U0_UART_RX/U0_deserializer/U15 A ) - + ROUTED M1 ( 4824 13944 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 3304 15160 ) VIA12SQ_C - NEW M2 ( 3304 13944 ) ( * 15160 ) - NEW M1 ( 5584 13944 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 4824 13944 ) ( 5584 * ) - NEW M2 ( 3304 13944 ) VIA23SQ_C W ( 4824 * ) - NEW M1 ( 3244 13944 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n4 - ( U0_UART_RX/U0_deserializer/U30 Y ) - ( U0_UART_RX/U0_deserializer/U33 A1 ) - ( U0_UART_RX/U0_deserializer/U32 A2 ) - ( U0_UART_RX/U0_deserializer/U31 A3 ) - + ROUTED M1 ( 4368 14248 ) VIA12SQ_C - NEW M2 ( 4216 14248 ) ( 4368 * ) - NEW M2 ( 4216 14248 ) ( * 14552 ) VIA23SQ_C W ( 5888 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 3760 12120 ) VIA12SQ_C ( * 12424 ) - NEW M2 ( 3760 12424 ) ( 4216 * ) - NEW M1 ( 6040 12424 ) VIA12SQ_C W VIA23SQ_C W - NEW M3 ( 4216 12424 ) ( 6040 * ) - NEW M2 ( 4216 12424 ) VIA23SQ_C W - NEW M2 ( 4216 12424 ) ( * 14248 ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n5 - ( U0_UART_RX/U0_deserializer/U33 Y ) - ( U0_UART_RX/U0_deserializer/U34 A1 ) - + ROUTED M1 ( 7560 11968 ) VIA12SQ_C - NEW M2 ( 7560 12120 ) VIA23SQ_C W - NEW M3 ( 6227 12120 ) ( 7560 * ) - NEW M2 ( 6227 12120 ) VIA23SQ_C W - NEW M2 ( 6227 12120 ) ( * 12272 ) VIA12SQ_C W - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n6 - ( U0_UART_RX/U0_deserializer/U13 Y ) - ( U0_UART_RX/U0_deserializer/U19 A3 ) - + ROUTED M1 ( 7286 18656 ) ( 9536 * ) VIA12SQ_C - NEW M2 ( 9536 17896 ) ( * 18656 ) - NEW M1 ( 9536 17896 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n7 - ( U0_UART_RX/U0_deserializer/U15 Y ) - ( U0_UART_RX/U0_deserializer/U29 A3 ) - + ROUTED M1 ( 4824 14552 ) VIA12SQ_C ( 5128 * ) - NEW M2 ( 5128 14552 ) ( * 14856 ) - NEW M2 ( 5128 14856 ) ( 5888 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n8 - ( U0_UART_RX/U0_deserializer/U17 Y ) - ( U0_UART_RX/U0_deserializer/U33 A2 ) - ( U0_UART_RX/U0_deserializer/U32 A1 ) - + ROUTED M3 ( 3304 11816 ) ( 4064 * ) - NEW M2 ( 3304 11816 ) VIA23SQ_C W - NEW M2 ( 3304 9536 ) ( * 11816 ) - NEW M1 ( 3304 9536 ) VIA12SQ_C - NEW M1 ( 5888 12120 ) VIA12SQ_C W - NEW M2 ( 5888 11816 ) ( * 12120 ) - NEW M2 ( 5888 11816 ) VIA23SQ_C W - NEW M3 ( 4064 11816 ) ( 5888 * ) - NEW M2 ( 4064 11816 ) VIA23SQ_C W - NEW M1 ( 4064 11968 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n9 - ( U0_UART_RX/U0_deserializer/U37 Y ) - ( U0_UART_RX/U0_deserializer/U38 A3 ) - + ROUTED M1 ( 11542 12272 ) ( 11938 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n10 - ( U0_UART_RX/U0_deserializer/U36 Y ) - ( U0_UART_RX/U0_deserializer/U38 A2 ) - + ROUTED M1 ( 12424 15008 ) VIA12SQ_C - NEW M2 ( 12424 12272 ) ( * 15008 ) - NEW M2 ( 12272 12272 ) ( 12424 * ) - NEW M1 ( 12272 12272 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n11 - ( U0_UART_RX/U0_deserializer/U35 Y ) - ( U0_UART_RX/U0_deserializer/U38 A1 ) - + ROUTED M1 ( 12120 12120 ) ( 12332 * ) - NEW M1 ( 12120 12120 ) VIA12SQ_C ( * 13032 ) VIA23SQ_C W - NEW M3 ( 10296 13032 ) ( 12120 * ) - NEW M2 ( 10296 13032 ) VIA23SQ_C W - NEW M1 ( 10296 13184 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n12 - ( U0_UART_RX/U0_deserializer/U40 Y ) - ( U0_UART_RX/U0_deserializer/U41 A3 ) - ( U0_UART_RX/U0_deserializer/U41 A2 ) - + ROUTED M1 ( 12728 18504 ) VIA12SQ_C - NEW M2 ( 12728 17896 ) ( * 18504 ) - NEW M2 ( 12728 17896 ) VIA23SQ_C W - NEW M3 ( 12424 17896 ) ( 12728 * ) - NEW M3 ( 12424 17896 ) VIA34SQ_C - NEW M4 ( 12424 16984 ) ( * 17896 ) - NEW M1 ( 12424 16528 ) VIA12SQ_C VIA23SQ_C W VIA34SQ_C ( * 16984 ) - NEW M1 ( 12728 16984 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 12424 16984 ) ( 12728 * ) - NEW M3 ( 12424 16984 ) VIA34SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n13 - ( U0_UART_RX/U0_deserializer/U42 Y ) - ( U0_UART_RX/U0_deserializer/U43 A4 ) - ( U0_UART_RX/U0_deserializer/U43 A1 ) - + ROUTED M1 ( 15008 17288 ) ( 15220 * ) - NEW M1 ( 16528 18200 ) ( 16680 * ) VIA12SQ_C - NEW M2 ( 16680 16984 ) ( * 18200 ) - NEW M2 ( 16680 16984 ) VIA23SQ_C W - NEW M3 ( 15008 16984 ) ( 16680 * ) - NEW M2 ( 15008 16984 ) VIA23SQ_C W - NEW M2 ( 15008 16984 ) ( * 17288 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n14 - ( U0_UART_RX/U0_deserializer/U43 Y ) - ( U0_UART_RX/U0_deserializer/U44 A4 ) - + ROUTED M1 ( 13944 16680 ) ( 14400 * ) - NEW M1 ( 13944 16680 ) VIA12SQ_C - NEW M2 ( 13944 15312 ) ( * 16680 ) - NEW M2 ( 13640 15312 ) ( 13944 * ) - NEW M1 ( 13640 15312 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n15 - ( U0_UART_RX/U0_deserializer/U41 Y ) - ( U0_UART_RX/U0_deserializer/U44 A3 ) - + ROUTED M1 ( 13032 16680 ) ( 13336 * ) VIA12SQ_C - NEW M2 ( 13336 15768 ) ( * 16680 ) - NEW M1 ( 13336 15768 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n16 - ( U0_UART_RX/U0_deserializer/U39 Y ) - ( U0_UART_RX/U0_deserializer/U44 A2 ) - + ROUTED M1 ( 13260 15464 ) VIA12SQ_C - NEW M2 ( 13258 15437 ) ( 13336 * ) - NEW M2 ( 13258 15464 ) ( 13336 * ) - NEW M2 ( 13336 12880 ) ( * 15450 ) - NEW M1 ( 13336 12880 ) VIA12SQ_C - NEW M1 ( 13336 12880 ) ( 13488 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n33 - ( U0_UART_RX/U0_deserializer/U38 Y ) - ( U0_UART_RX/U0_deserializer/U44 A1 ) - + ROUTED M1 ( 12424 12880 ) ( 12880 * ) VIA12SQ_C ( * 15312 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n34 - ( U0_UART_RX/U0_deserializer/U7 Y ) - ( U0_UART_RX/U0_deserializer/U43 A2 ) - + ROUTED M1 ( 10144 15312 ) VIA12SQ_C ( * 15768 ) VIA23SQ_C W ( 15160 * ) VIA23SQ_C W ( * 16528 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n35 - ( U0_UART_RX/U0_deserializer/U11 Y ) - ( U0_UART_RX/U0_deserializer/U41 A4 ) - + ROUTED M1 ( 12470 17136 ) VIA12SQ_C - NEW M2 ( 12470 17288 ) VIA23SQ_C W ( 13488 * ) VIA23SQ_C W - NEW M1 ( 13488 17440 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n43 - ( U0_UART_RX/U0_deserializer/U5 Y ) - ( U0_UART_RX/U0_deserializer/U16 A4 ) - ( U0_UART_RX/U0_deserializer/U14 A3 ) - ( U0_UART_RX/U0_deserializer/U12 A3 ) - ( U0_UART_RX/U0_deserializer/U10 A3 ) - ( U0_UART_RX/U0_deserializer/U8 A3 ) - ( U0_UART_RX/U0_deserializer/U6 A3 ) - ( U0_UART_RX/U0_deserializer/U4 A3 ) - ( U0_UART_RX/U0_deserializer/U3 A3 ) - + ROUTED M1 ( 33552 41608 ) VIA12SQ_C VIA23SQ_C W ( 35984 * ) - NEW M1 ( 35984 44648 ) VIA12SQ_C - NEW M2 ( 35984 41608 ) ( * 44648 ) - NEW M2 ( 35984 41608 ) VIA23SQ_C W - NEW M1 ( 39176 41304 ) VIA12SQ_C - NEW M2 ( 38872 41304 ) ( 39176 * ) - NEW M1 ( 38872 38264 ) VIA12SQ_C - NEW M1 ( 36744 38264 ) VIA12SQ_C VIA23SQ_C W - NEW M1 ( 35832 34920 ) VIA12SQ_C - NEW M1 ( 35680 32944 ) VIA12SQ_C ( 35984 * ) - NEW M2 ( 35984 32944 ) ( * 33704 ) - NEW M2 ( 38872 41304 ) ( * 41608 ) VIA23SQ_C W - NEW M2 ( 38872 38264 ) ( * 41304 ) - NEW M3 ( 35984 41608 ) ( 38872 * ) - NEW M2 ( 35832 33704 ) ( * 34920 ) - NEW M2 ( 35832 33704 ) ( 35984 * ) - NEW M2 ( 35832 34920 ) VIA23SQ_C W VIA34SQ_C ( * 38264 ) VIA34SQ_C ( 36744 * ) - NEW M2 ( 38872 38264 ) VIA23SQ_C W - NEW M3 ( 36744 38264 ) ( 38872 * ) - NEW M1 ( 39480 41608 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 38872 41608 ) ( 39480 * ) - NEW M2 ( 35984 33704 ) VIA23SQ_C W ( 37656 * ) VIA23SQ_C W ( * 34160 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n46 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_7_ SI ) - + ROUTED M1 ( 41400 32792 ) ( 41608 * ) VIA12SQ_C ( * 34947 ) - NEW M2 ( 41608 34947 ) ( 41760 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n47 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_5_ QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ SI ) - + ROUTED M1 ( 40726 37933 ) ( 41000 * ) VIA12SQ_C ( * 40088 ) VIA12SQ_C ( 41424 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n48 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_6_ SI ) - + ROUTED M1 ( 45408 38264 ) VIA12SQ_C - NEW M2 ( 45408 37048 ) ( * 38264 ) - NEW M2 ( 45408 37048 ) VIA23SQ_C W - NEW M3 ( 38112 37048 ) ( 45408 * ) - NEW M2 ( 38112 37048 ) VIA23SQ_C W - NEW M2 ( 38112 36136 ) ( * 37048 ) - NEW M1 ( 38112 36136 ) VIA12SQ_C - NEW M1 ( 37840 36136 ) ( 38112 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n49 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_4_ SI ) - + ROUTED M1 ( 45560 43584 ) ( 45864 * ) - NEW M1 ( 45864 42976 ) ( * 43584 ) - NEW M1 ( 41760 42976 ) ( 45864 * ) - NEW M1 ( 41760 42976 ) VIA12SQ_C - NEW M2 ( 41760 39480 ) ( * 42976 ) - NEW M1 ( 41760 39480 ) VIA12SQ_C - NEW M1 ( 41488 39480 ) ( 41760 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n50 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_2_ QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_3_ SI ) - + ROUTED M1 ( 41516 43432 ) VIA12SQ_C_1_2 - NEW M2 ( 41456 41304 ) ( * 43432 ) - NEW M2 ( 41456 41304 ) VIA23SQ_C W ( 45560 * ) VIA23SQ_C W - NEW M2 ( 45560 40240 ) ( * 41304 ) - NEW M1 ( 45560 40240 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_deserializer/n51 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ QN ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ SI ) - + ROUTED M1 ( 33856 43280 ) ( 34008 * ) VIA12SQ_C - NEW M2 ( 34008 41000 ) ( * 43280 ) - NEW M2 ( 34008 41000 ) VIA23SQ_C W - NEW M3 ( 29448 41000 ) ( 34008 * ) - NEW M2 ( 29448 41000 ) VIA23SQ_C W - NEW M2 ( 29448 40088 ) ( * 41000 ) - NEW M1 ( 29388 40088 ) VIA12SQ_C_1_2 - + USE SIGNAL ; - - U0_UART_RX/U0_strt_chk/n3 - ( U0_UART_RX/U0_strt_chk/U2 Y ) - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg D ) - + ROUTED M1 ( 29296 37352 ) VIA12SQ_C VIA23SQ_C W ( 33856 * ) VIA23SQ_C W - NEW M2 ( 33856 36288 ) ( * 37352 ) - NEW M1 ( 33856 36288 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_strt_chk/n1 - ( U0_UART_RX/U0_strt_chk/U3 Y ) - ( U0_UART_RX/U0_strt_chk/U2 A4 ) - + ROUTED M1 ( 33552 35376 ) VIA12SQ_C ( 34464 * ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n2 - ( U0_UART_RX/U0_par_chk/U3 Y ) - ( U0_UART_RX/U0_par_chk/U2 A4 ) - + ROUTED M1 ( 40088 31880 ) VIA12SQ_C - NEW M2 ( 40088 29144 ) ( * 31880 ) - NEW M2 ( 40088 29144 ) VIA23SQ_C W ( 40392 * ) VIA23SQ_C W - NEW M2 ( 40392 28688 ) ( * 29144 ) - NEW M1 ( 40392 28688 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n3 - ( U0_UART_RX/U0_par_chk/U7 Y ) - ( U0_UART_RX/U0_par_chk/U3 A1 ) - + ROUTED M1 ( 37504 32944 ) VIA12SQ_C - NEW M2 ( 37504 32488 ) ( * 32944 ) - NEW M2 ( 37504 32488 ) VIA23SQ_C W ( 40392 * ) - NEW M3 ( 40392 32184 ) ( * 32488 ) - NEW M3 ( 40392 32184 ) ( 42216 * ) VIA23SQ_C W ( * 35224 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n4 - ( U0_UART_RX/U0_par_chk/U5 Y ) - ( U0_UART_RX/U0_par_chk/U3 A2 ) - + ROUTED M1 ( 37200 32270 ) VIA12SQ_C ( 37808 * ) - NEW M2 ( 37808 32270 ) ( * 34920 ) - NEW M2 ( 37808 34920 ) ( 37960 * ) - NEW M2 ( 37960 34920 ) ( * 37960 ) - NEW M2 ( 37808 37960 ) ( 37960 * ) - NEW M2 ( 37808 37960 ) ( * 39936 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n5 - ( U0_UART_RX/U0_par_chk/U8 Y ) - ( U0_UART_RX/U0_par_chk/U3 A3 ) - + ROUTED M1 ( 39171 32027 ) ( 39405 * ) - NEW M1 ( 39171 32068 ) ( 39405 * ) - NEW M1 ( 39176 32032 ) VIA12SQ_C - NEW M2 ( 39176 29600 ) ( * 32032 ) - NEW M1 ( 39176 29600 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n6 - ( U0_UART_RX/U0_par_chk/U6 Y ) - ( U0_UART_RX/U0_par_chk/U5 A3 ) - + ROUTED M1 ( 37352 40848 ) VIA12SQ_C ( * 43280 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n7 - ( U0_UART_RX/U0_par_chk/U4 Y ) - ( U0_UART_RX/U0_par_chk/U7 A3 ) - + ROUTED M1 ( 42824 35376 ) VIA12SQ_C - NEW M2 ( 42824 34464 ) ( * 35376 ) - NEW M1 ( 42824 34464 ) VIA12SQ_C - NEW M1 ( 42824 34464 ) ( 43280 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n9 - ( U0_UART_RX/U0_par_chk/U2 Y ) - ( U0_UART_RX/U0_par_chk/par_err_reg D ) - + ROUTED M1 ( 41152 30664 ) VIA12SQ_C - NEW M2 ( 41152 29600 ) ( * 30664 ) - NEW M1 ( 41152 29600 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_par_chk/n1 - ( U0_UART_RX/U0_par_chk/U9 Y ) - ( U0_UART_RX/U0_par_chk/U2 A2 ) - + ROUTED M1 ( 39784 29144 ) ( 40362 * ) - NEW M1 ( 39784 29144 ) VIA12SQ_C - NEW M2 ( 39784 27513 ) ( * 29144 ) - NEW M1 ( 39784 27513 ) VIA12SQ_C - + USE SIGNAL ; - - dftopt2 - ( U0_UART_RX/U0_uart_fsm/current_state_reg_2_ QN ) - ( U0_UART_RX/U0_uart_fsm/U75 A3 ) - ( U0_UART_RX/U0_uart_fsm/U33 A1 ) - ( U0_UART_RX/U0_uart_fsm/U28 A2 ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_1_ SI ) - + ROUTED M1 ( 39024 26864 ) VIA12SQ_C ( * 27320 ) VIA23SQ_C W - NEW M3 ( 36288 27320 ) ( 39024 * ) - NEW M2 ( 36288 27320 ) VIA23SQ_C W - NEW M1 ( 35072 28840 ) VIA12SQ_C ( * 29144 ) VIA23SQ_C W ( 36288 * ) VIA23SQ_C W - NEW M2 ( 36288 27320 ) ( * 29144 ) - NEW M1 ( 35072 30512 ) VIA12SQ_C - NEW M2 ( 35072 30056 ) ( * 30512 ) - NEW M2 ( 35072 30056 ) VIA23SQ_C W ( 36288 * ) VIA23SQ_C W - NEW M2 ( 36288 29144 ) ( * 30056 ) - NEW M2 ( 36288 23368 ) ( * 27320 ) - NEW M1 ( 36288 23368 ) VIA12SQ_C - NEW M1 ( 35984 30512 ) ( * 30664 ) - NEW M1 ( 35188 30512 ) ( 35984 * ) - + USE SIGNAL ; - - U0_UART_RX/U0_stp_chk/n2 - ( U0_UART_RX/U0_stp_chk/stp_err_reg QN ) - ( U0_UART_RX/U0_stp_chk/U2 A4 ) - + ROUTED M1 ( 45256 26864 ) VIA12SQ_C ( * 27320 ) VIA23SQ_C W - NEW M3 ( 40240 27320 ) ( 45256 * ) - NEW M2 ( 40240 27320 ) VIA23SQ_C W - NEW M2 ( 40240 26104 ) ( * 27320 ) - NEW M2 ( 40088 26104 ) ( 40240 * ) - NEW M2 ( 40088 25648 ) ( * 26104 ) - NEW M1 ( 40088 25648 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_stp_chk/n4 - ( U0_UART_RX/U0_stp_chk/U2 Y ) - ( U0_UART_RX/U0_stp_chk/stp_err_reg D ) - + ROUTED M1 ( 41000 27320 ) VIA12SQ_C - NEW M2 ( 41000 26104 ) ( * 27320 ) - NEW M1 ( 41000 26104 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/U0_stp_chk/n1 - ( U0_UART_RX/U0_stp_chk/U3 Y ) - ( U0_UART_RX/U0_stp_chk/U2 A2 ) - + ROUTED M1 ( 39936 26252 ) VIA12SQ_C - NEW M2 ( 39936 25800 ) ( * 26252 ) - NEW M2 ( 39936 25800 ) VIA23SQ_C W - NEW M3 ( 38112 25800 ) ( 39936 * ) - NEW M2 ( 38112 25800 ) VIA23SQ_C W - NEW M2 ( 38112 25344 ) ( * 25800 ) - NEW M1 ( 38112 25344 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_RX/dftopt0 - ( U0_UART_RX/U0_data_sampling/Samples_reg_1_ QN ) - ( U0_UART_RX/U0_data_sampling/U64 A2 ) - ( U0_UART_RX/U0_deserializer/P_DATA_reg_1_ SI ) - + ROUTED M1 ( 28232 42216 ) VIA12SQ_C ( * 43432 ) - NEW M2 ( 28232 43432 ) ( 28384 * ) VIA23SQ_C W ( 29752 * ) VIA23SQ_C W VIA12SQ_C - NEW M1 ( 28384 43584 ) VIA12SQ_C - NEW M1 ( 28384 43554 ) ( 28498 * ) - NEW M1 ( 28384 43589 ) ( 28498 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt1 - ( U0_UART_RX/U0_deserializer/P_DATA_reg_0_ QN ) - ( U0_UART_RX/U0_data_sampling/sampled_bit_reg SI ) - + ROUTED M1 ( 31516 39480 ) VIA12SQ_C_1_2 - NEW M2 ( 31576 38872 ) ( * 39480 ) - NEW M2 ( 31576 38872 ) VIA23SQ_C W ( 33552 * ) VIA23SQ_C W ( * 39936 ) VIA12SQ_C - NEW M1 ( 33400 39936 ) ( 33552 * ) - + USE SIGNAL ; - - U0_UART_TX/dftopt0 - ( U0_UART_TX/U0_Serializer/DATA_V_reg_0_ QN ) - ( U0_UART_TX/U0_parity_calc/parity_reg SI ) - + ROUTED M1 ( 38416 13336 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 35832 13336 ) ( 38416 * ) - NEW M2 ( 35832 13336 ) VIA23SQ_C W - NEW M2 ( 35832 13336 ) ( * 16680 ) VIA12SQ_C - + USE SIGNAL ; - - dftopt3 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ SI ) - + ROUTED M1 ( 33400 20176 ) VIA12SQ_C ( * 21240 ) VIA23SQ_C W - NEW M3 ( 24584 21240 ) ( 33400 * ) - NEW M2 ( 24584 21240 ) VIA23SQ_C W - NEW M2 ( 24584 21240 ) ( * 23368 ) VIA12SQ_C - NEW M1 ( 24376 23368 ) ( 24584 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt10_gOb10 - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ QN ) - ( U0_UART_RX/U0_uart_fsm/current_state_reg_0_ SI ) - + ROUTED M1 ( 28628 29448 ) VIA12SQ_C_1_2 - NEW M2 ( 28688 24557 ) ( * 29448 ) - NEW M1 ( 28688 24557 ) VIA12SQ_C - NEW M1 ( 28414 24557 ) ( 28688 * ) - + USE SIGNAL ; - - U0_UART_TX/dftopt3 - ( U0_UART_TX/U0_Serializer/ser_count_reg_0_ QN ) - ( U0_UART_TX/U0_Serializer/U34 A2 ) - ( U0_UART_TX/U0_fsm/current_state_reg_2_ SI ) - + ROUTED M1 ( 35528 12728 ) VIA12SQ_C ( * 20632 ) VIA23SQ_C W ( 37048 * ) - NEW M3 ( 37048 20328 ) ( * 20632 ) - NEW M3 ( 37048 20328 ) ( 38568 * ) - NEW M1 ( 38568 22152 ) VIA12SQ_C - NEW M2 ( 38568 20328 ) ( * 22152 ) - NEW M2 ( 38568 20328 ) VIA23SQ_C W - NEW M1 ( 39784 20176 ) VIA12SQ_C - NEW M2 ( 39784 20328 ) VIA23SQ_C W - NEW M3 ( 38568 20328 ) ( 39784 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt3 - ( U0_UART_RX/U0_uart_fsm/current_state_reg_1_ QN ) - ( U0_UART_RX/U0_uart_fsm/U78 A1 ) - ( U0_UART_RX/U0_strt_chk/strt_glitch_reg SI ) - + ROUTED M1 ( 27016 33704 ) VIA12SQ_C W VIA23SQ_C W ( 29600 * ) - NEW M1 ( 29540 36744 ) VIA12SQ_C_1_2 - NEW M2 ( 29600 33704 ) ( * 36744 ) - NEW M2 ( 29600 33704 ) VIA23SQ_C W - NEW M1 ( 32792 33552 ) VIA12SQ_C - NEW M2 ( 32792 33704 ) VIA23SQ_C W - NEW M3 ( 29600 33704 ) ( 32792 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt6 - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ SI ) - + ROUTED M1 ( 23216 32792 ) VIA12SQ_C - NEW M2 ( 23216 32184 ) ( * 32792 ) - NEW M2 ( 23216 32184 ) VIA23SQ_C W ( 27472 * ) VIA23SQ_C W ( * 34947 ) VIA12SQ_C - + USE SIGNAL ; - - U0_UART_TX/dftopt6 - ( U0_UART_TX/U0_fsm/current_state_reg_1_ QN ) - ( U0_UART_TX/U0_fsm/U20 A2 ) - ( U0_UART_TX/U0_fsm/U13 A4 ) - ( U0_UART_TX/U0_fsm/U9 A1 ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ SI ) - + ROUTED M1 ( 45560 7837 ) VIA12SQ_C ( * 10904 ) VIA23SQ_C W - NEW M3 ( 43736 10904 ) ( 45560 * ) - NEW M1 ( 38568 8624 ) VIA12SQ_C - NEW M2 ( 38416 8624 ) ( 38568 * ) - NEW M2 ( 38416 8624 ) ( * 10600 ) - NEW M1 ( 43736 10600 ) VIA12SQ_C ( * 10904 ) VIA23SQ_C W - NEW M1 ( 41000 12120 ) VIA12SQ_C - NEW M2 ( 41000 11512 ) ( * 12120 ) - NEW M2 ( 41000 11512 ) VIA23SQ_C W - NEW M1 ( 26104 9992 ) VIA12SQ_C ( * 10600 ) VIA23SQ_C W ( 38416 * ) VIA23SQ_C W - NEW M3 ( 41000 11208 ) ( * 11512 ) - NEW M3 ( 41000 11208 ) ( 43736 * ) - NEW M3 ( 43736 10904 ) ( * 11208 ) - NEW M3 ( 38416 11512 ) ( 41000 * ) - NEW M2 ( 38416 11512 ) VIA23SQ_C W - NEW M2 ( 38416 10600 ) ( * 11512 ) - + USE SIGNAL ; - - dftopt15 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ Q ) - ( U0_UART_TX/U0_parity_calc/U21 A2 ) - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ SI ) - + ROUTED M1 ( 26256 16984 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 24584 16984 ) ( 26256 * ) - NEW M1 ( 24584 15768 ) VIA12SQ_C ( * 16984 ) VIA23SQ_C W - NEW M1 ( 23612 22760 ) VIA12SQ_C_1_2 - NEW M2 ( 23672 16984 ) ( * 22760 ) - NEW M2 ( 23672 16984 ) VIA23SQ_C W ( 24584 * ) - + USE SIGNAL ; - - U0_UART_TX/dftopt5 - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ Q ) - ( U0_UART_TX/U0_parity_calc/U17 A2 ) - ( U0_UART_TX/U0_Serializer/DATA_V_reg_5_ SI ) - + ROUTED M1 ( 16924 9384 ) VIA12SQ_C_1_2 - NEW M2 ( 16984 8472 ) ( * 9384 ) - NEW M2 ( 16984 8472 ) VIA23SQ_C W ( 20328 * ) VIA23SQ_C W ( * 10296 ) VIA23SQ_C W ( 20632 * ) - NEW M1 ( 20632 10296 ) VIA12SQ_C VIA23SQ_C W ( 22152 * ) VIA23SQ_C W VIA12SQ_C - + USE SIGNAL ; - - optlc_net_427 - ( optlc_1046 Y ) - ( U0_UART_TX/U0_mux/U7 A3 ) - + ROUTED M1 ( 42520 14552 ) VIA12SQ_C VIA23SQ_C W ( 43888 * ) VIA23SQ_C W ( * 15008 ) VIA12SQ_C - + USE SIGNAL ; - - dftopt14 - ( U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/U19 A3 ) - ( U0_UART_RX/U0_edge_bit_counter/U18 A2 ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ SI ) - + ROUTED M2 ( 21848 20936 ) VIA23SQ_C W ( 27776 * ) VIA23SQ_C W ( * 21088 ) - NEW M1 ( 27776 21571 ) VIA12SQ_C - NEW M2 ( 27776 21088 ) ( * 21571 ) - NEW M1 ( 21848 21240 ) VIA12SQ_C - NEW M2 ( 21848 20936 ) ( * 21240 ) - NEW M2 ( 27776 21088 ) ( 28840 * ) - NEW M2 ( 28840 20024 ) ( * 21088 ) - NEW M1 ( 28840 20024 ) VIA12SQ_C - NEW M1 ( 28840 20024 ) ( 29296 * ) - NEW M2 ( 21848 18808 ) ( * 20936 ) - NEW M1 ( 21848 18808 ) VIA12SQ_C - NEW M1 ( 21240 18808 ) ( 21848 * ) - + USE SIGNAL ; - - U0_UART_RX/dftopt17 - ( U0_UART_RX/U0_data_sampling/Samples_reg_0_ QN ) - ( U0_UART_RX/U0_data_sampling/U64 A1 ) - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ SI ) - + ROUTED M1 ( 27928 40240 ) VIA12SQ_C ( * 41304 ) - NEW M1 ( 27928 42520 ) VIA12SQ_C W - NEW M2 ( 27928 41304 ) ( * 42520 ) - NEW M1 ( 17080 40088 ) ( 17288 * ) VIA12SQ_C ( * 41304 ) VIA23SQ_C W ( 27928 * ) VIA23SQ_C W - + USE SIGNAL ; - - U0_UART_RX/dftopt18 - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ QN ) - ( U0_UART_RX/U0_data_sampling/Samples_reg_2_ SI ) - + ROUTED M1 ( 22152 34589 ) VIA12SQ_C - NEW M2 ( 22152 34616 ) VIA23SQ_C W ( 23216 * ) VIA23SQ_C W ( * 36136 ) VIA12SQ_C - + USE SIGNAL ; - - dftopt19 - ( U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ QN ) - ( U0_UART_RX/U0_edge_bit_counter/U56 A4 ) - ( U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ SI ) - + ROUTED M1 ( 19264 16072 ) VIA12SQ_C ( * 16680 ) - NEW M1 ( 20480 26712 ) VIA12SQ_C VIA23SQ_C W - NEW M3 ( 18808 26712 ) ( 20480 * ) - NEW M2 ( 18808 26712 ) VIA23SQ_C W - NEW M2 ( 18808 16680 ) ( * 26712 ) - NEW M2 ( 18808 16680 ) VIA23SQ_C W ( 19264 * ) VIA23SQ_C W - NEW M1 ( 19264 17136 ) VIA12SQ_C - NEW M2 ( 19264 16680 ) ( * 17136 ) - + USE SIGNAL ; - - SO - ( PIN SO ) - ( U0_UART_TX/U0_Serializer/ser_count_reg_2_ QN ) - ( U0_UART_TX/U0_Serializer/U31 A4 ) - + ROUTED M3 ( 45560 23976 ) ( 48454 * ) - NEW M2 ( 45560 23976 ) VIA23SQ_C W - NEW M1 ( 45408 23976 ) VIA12SQ_C ( 45560 * ) - NEW M1 ( 45560 21213 ) VIA12SQ_C ( * 23976 ) - + USE SIGNAL ; -END NETS -END DESIGN diff --git a/pnr/output/UART.gds b/pnr/output/UART.gds deleted file mode 100644 index 0f81899..0000000 Binary files a/pnr/output/UART.gds and /dev/null differ diff --git a/pnr/output/UART.lef b/pnr/output/UART.lef deleted file mode 100644 index 87fac92..0000000 --- a/pnr/output/UART.lef +++ /dev/null @@ -1,446 +0,0 @@ -VERSION 5.8 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -MACRO UART - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 48.712 BY 47.8 ; - SYMMETRY X Y ; - PIN RST - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M6 ; - RECT 22.428 0 22.484 0.286 ; - END - END RST - PIN TX_CLK - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER M4 ; - RECT 20.908 0 20.964 0.286 ; - END - END TX_CLK - PIN RX_CLK - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER M3 ; - RECT 0 24.252 0.286 24.308 ; - END - END RX_CLK - PIN RX_IN_S - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 30.332 47.514 30.388 47.8 ; - END - END RX_IN_S - PIN RX_OUT_P[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M5 ; - RECT 48.426 35.196 48.712 35.252 ; - END - END RX_OUT_P[7] - PIN RX_OUT_P[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 37.628 48.712 37.684 ; - END - END RX_OUT_P[6] - PIN RX_OUT_P[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 35.5 48.712 35.556 ; - END - END RX_OUT_P[5] - PIN RX_OUT_P[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 39.756 48.712 39.812 ; - END - END RX_OUT_P[4] - PIN RX_OUT_P[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 41.58 47.514 41.636 47.8 ; - END - END RX_OUT_P[3] - PIN RX_OUT_P[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 38.844 47.514 38.9 47.8 ; - END - END RX_OUT_P[2] - PIN RX_OUT_P[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 36.716 47.514 36.772 47.8 ; - END - END RX_OUT_P[1] - PIN RX_OUT_P[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 34.588 47.514 34.644 47.8 ; - END - END RX_OUT_P[0] - PIN RX_OUT_V - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 28.812 48.712 28.868 ; - END - END RX_OUT_V - PIN TX_IN_P[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M6 ; - RECT 29.724 0 29.78 0.286 ; - END - END TX_IN_P[7] - PIN TX_IN_P[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M6 ; - RECT 27.292 0 27.348 0.286 ; - END - END TX_IN_P[6] - PIN TX_IN_P[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 27.9 0 27.956 0.286 ; - END - END TX_IN_P[5] - PIN TX_IN_P[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 25.772 0 25.828 0.286 ; - END - END TX_IN_P[4] - PIN TX_IN_P[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M6 ; - RECT 32.156 0 32.212 0.286 ; - END - END TX_IN_P[3] - PIN TX_IN_P[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 18.172 48.712 18.228 ; - END - END TX_IN_P[2] - PIN TX_IN_P[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 30.028 0 30.084 0.286 ; - END - END TX_IN_P[1] - PIN TX_IN_P[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 16.652 0 16.708 0.286 ; - END - END TX_IN_P[0] - PIN TX_IN_V - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 32.764 0 32.82 0.286 ; - END - END TX_IN_V - PIN TX_OUT_S - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 16.044 48.712 16.1 ; - END - END TX_OUT_S - PIN TX_OUT_V - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 34.892 0 34.948 0.286 ; - END - END TX_OUT_V - PIN Prescale[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M5 ; - RECT 0 21.82 0.286 21.876 ; - END - END Prescale[5] - PIN Prescale[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 0 14.828 0.286 14.884 ; - END - END Prescale[4] - PIN Prescale[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 0 26.38 0.286 26.436 ; - END - END Prescale[3] - PIN Prescale[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 0 21.516 0.286 21.572 ; - END - END Prescale[2] - PIN Prescale[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 0 28.508 0.286 28.564 ; - END - END Prescale[1] - PIN Prescale[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 0 18.78 0.286 18.836 ; - END - END Prescale[0] - PIN parity_enable - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M5 ; - RECT 48.426 19.388 48.712 19.444 ; - END - END parity_enable - PIN parity_type - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 21.82 48.712 21.876 ; - END - END parity_type - PIN parity_error - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 30.94 48.712 30.996 ; - END - END parity_error - PIN framing_error - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 26.684 48.712 26.74 ; - END - END framing_error - PIN SI - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 13.612 47.514 13.668 47.8 ; - END - END SI - PIN SE - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 24.556 47.514 24.612 47.8 ; - END - END SE - PIN SO - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER M3 ; - RECT 48.426 23.948 48.712 24.004 ; - END - END SO - PIN scan_clk - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER M4 ; - RECT 18.78 0 18.836 0.286 ; - END - END scan_clk - PIN scan_rst - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 23.036 0 23.092 0.286 ; - END - END scan_rst - PIN test_mode - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M6 ; - RECT 24.86 0 24.916 0.286 ; - END - END test_mode - PIN VDD - DIRECTION INPUT ; - USE POWER ; - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - END VSS - OBS - LAYER M6 ; - RECT 23.184 0.7 24.16 1.005 ; - RECT 25.616 0.7 26.592 1.005 ; - RECT 28.048 0.7 29.024 1.005 ; - RECT 30.48 0.7 31.456 1.005 ; - RECT 0.7 0.986 48.012 47.1 ; - RECT 0.7 0.7 21.728 3.705 ; - RECT 32.912 0.7 48.012 3.705 ; - LAYER M4 ; - RECT 35.344 46.795 36.016 47.1 ; - RECT 37.472 46.795 38.144 47.1 ; - RECT 39.6 46.795 40.88 47.1 ; - RECT 17.408 0.7 18.08 1.005 ; - RECT 19.536 0.7 20.208 1.005 ; - RECT 21.664 0.7 22.336 1.005 ; - RECT 23.792 0.7 25.072 1.005 ; - RECT 26.528 0.7 27.2 1.005 ; - RECT 28.656 0.7 29.328 1.005 ; - RECT 30.784 0.7 32.064 1.005 ; - RECT 33.52 0.7 34.192 1.005 ; - RECT 31.088 45.595 33.888 47.1 ; - RECT 0.7 44.095 12.912 47.1 ; - RECT 14.368 44.095 23.856 47.1 ; - RECT 25.312 44.095 29.632 47.1 ; - RECT 42.336 44.095 48.012 47.1 ; - RECT 0.7 0.986 48.012 46.814 ; - RECT 0.7 0.7 15.952 3.705 ; - RECT 35.648 0.7 48.012 3.705 ; - POLYGON 48.012 47.1 48.012 0.7 35.648 0.7 35.648 0.986 34.192 0.986 34.192 0.7 33.52 0.7 33.52 0.986 32.064 0.986 32.064 0.7 30.784 0.7 30.784 0.986 29.328 0.986 29.328 0.7 28.656 0.7 28.656 0.986 27.2 0.986 27.2 0.7 26.528 0.7 26.528 0.986 25.072 0.986 25.072 0.7 24.308 0.7 24.308 0.623 24.31 0.623 24.31 0.513 24.25 0.513 24.25 0.623 24.252 0.623 24.252 0.7 23.792 0.7 23.792 0.986 22.336 0.986 22.336 0.7 21.664 0.7 21.664 0.986 20.208 0.986 20.208 0.7 19.536 0.7 19.536 0.986 18.08 0.986 18.08 0.7 17.408 0.7 17.408 0.986 15.952 0.986 15.952 0.7 0.7 0.7 0.7 47.1 12.912 47.1 12.912 46.814 14.368 46.814 14.368 47.1 23.856 47.1 23.856 46.814 25.312 46.814 25.312 47.1 29.632 47.1 29.632 46.814 31.088 46.814 31.088 47.1 33.888 47.1 33.888 46.814 35.344 46.814 35.344 47.1 36.016 47.1 36.016 46.814 37.472 46.814 37.472 47.1 38.144 47.1 38.144 46.814 39.6 46.814 39.6 47.1 40.88 47.1 40.88 46.814 42.336 46.814 42.336 47.1 ; - POLYGON 48.63 19.471 48.63 19.361 48.628 19.361 48.628 18.863 48.63 18.863 48.63 18.753 48.57 18.753 48.57 18.863 48.572 18.863 48.572 19.361 48.57 19.361 48.57 19.471 ; - LAYER M3 ; - RECT 47.707 38.384 48.012 39.056 ; - RECT 47.707 36.256 48.012 36.928 ; - RECT 47.707 29.568 48.012 30.24 ; - RECT 47.707 27.44 48.012 28.112 ; - RECT 0.7 27.136 1.005 27.808 ; - RECT 47.707 24.704 48.012 25.984 ; - RECT 0.7 25.008 1.005 25.68 ; - RECT 0.7 22.272 1.005 23.552 ; - RECT 47.707 22.576 48.012 23.248 ; - RECT 0.7 19.536 1.005 20.816 ; - RECT 47.707 16.8 48.012 17.472 ; - RECT 46.507 18.928 48.012 21.12 ; - RECT 0.7 15.584 2.205 18.08 ; - RECT 0.7 40.512 48.012 47.1 ; - RECT 0.7 34.8 47.726 40.512 ; - RECT 0.7 31.696 48.012 34.8 ; - RECT 0.7 29.264 47.726 32.269 ; - RECT 0.986 15.344 47.726 29.264 ; - RECT 0.986 14.128 47.726 17.133 ; - RECT 45.007 12.339 48.012 15.344 ; - RECT 0.7 0.7 48.012 14.128 ; - POLYGON 48.012 47.1 48.012 40.512 47.726 40.512 47.726 39.056 48.012 39.056 48.012 38.384 47.726 38.384 47.726 36.928 48.012 36.928 48.012 36.256 47.726 36.256 47.726 34.8 48.012 34.8 48.012 31.696 47.726 31.696 47.726 30.24 48.012 30.24 48.012 29.568 47.726 29.568 47.726 28.112 48.012 28.112 48.012 27.44 47.726 27.44 47.726 25.984 48.012 25.984 48.012 24.704 47.726 24.704 47.726 23.248 48.012 23.248 48.012 22.576 47.726 22.576 47.726 21.12 48.012 21.12 48.012 18.928 47.726 18.928 47.726 18.836 48.545 18.836 48.545 18.838 48.655 18.838 48.655 18.778 48.545 18.778 48.545 18.78 47.726 18.78 47.726 17.472 48.012 17.472 48.012 16.8 47.726 16.8 47.726 15.344 48.012 15.344 48.012 0.7 0.7 0.7 0.7 14.128 0.986 14.128 0.986 15.584 0.7 15.584 0.7 18.08 0.986 18.08 0.986 19.536 0.7 19.536 0.7 20.816 0.986 20.816 0.986 22.272 0.7 22.272 0.7 23.552 0.986 23.552 0.986 25.008 0.7 25.008 0.7 25.68 0.986 25.68 0.986 27.136 0.7 27.136 0.7 27.808 0.986 27.808 0.986 29.264 0.7 29.264 0.7 47.1 ; - POLYGON 27.983 0.598 27.983 0.538 27.873 0.538 27.873 0.54 22.967 0.54 22.967 0.538 22.857 0.538 22.857 0.598 22.967 0.598 22.967 0.596 27.873 0.596 27.873 0.598 ; - LAYER M5 ; - RECT 0.7 35.952 48.012 47.1 ; - RECT 0.7 32.947 47.726 37.501 ; - RECT 0.7 22.576 48.012 34.496 ; - RECT 0.986 20.144 48.012 24.125 ; - RECT 0.986 21.071 48.012 22.576 ; - RECT 0.7 18.115 3.705 21.12 ; - RECT 3.705 20.144 48.012 23.149 ; - RECT 0.986 18.688 47.726 21.693 ; - RECT 0.7 18.115 3.705 21.12 ; - RECT 0.7 0.7 48.012 18.688 ; - POLYGON 48.012 47.1 48.012 35.952 47.726 35.952 47.726 34.496 48.012 34.496 48.012 20.144 47.726 20.144 47.726 18.688 48.012 18.688 48.012 0.7 0.7 0.7 0.7 21.12 0.986 21.12 0.986 22.576 0.7 22.576 0.7 47.1 ; - POLYGON 27.375 0.598 27.375 0.538 27.265 0.538 27.265 0.54 24.335 0.54 24.335 0.538 24.225 0.538 24.225 0.598 24.335 0.598 24.335 0.596 27.265 0.596 27.265 0.598 ; - LAYER NWELL ; - RECT 0.23 0.23 48.482 47.57 ; - LAYER PO ; - RECT 0.122 0.122 48.59 47.678 ; - LAYER M1 ; - RECT 0.6 0.6 48.112 47.2 ; - LAYER M2 ; - RECT 0.7 0.7 48.012 47.1 ; - POLYGON 48.012 47.1 48.012 0.7 22.94 0.7 22.94 0.623 22.942 0.623 22.942 0.513 22.882 0.513 22.882 0.623 22.884 0.623 22.884 0.7 0.7 0.7 0.7 47.1 ; - LAYER VIA2 ; - RECT 22.887 0.543 22.937 0.593 ; - LAYER VIA3 ; - RECT 0.847 24.255 0.897 24.305 ; - RECT 48.575 18.783 48.625 18.833 ; - RECT 27.903 0.543 27.953 0.593 ; - LAYER VIA4 ; - RECT 48.575 19.391 48.625 19.441 ; - RECT 24.255 0.543 24.305 0.593 ; - LAYER VIA5 ; - RECT 27.295 0.543 27.345 0.593 ; - LAYER M7 ; - RECT 0.7 0.7 48.012 47.1 ; - LAYER M8 ; - RECT 0.7 0.7 48.012 47.1 ; - LAYER M9 ; - RECT 0.5 0.5 48.212 47.3 ; - LAYER MRDL ; - RECT 2 2 46.712 45.8 ; - LAYER OVERLAP ; - POLYGON 0 0 0 47.8 48.712 47.8 48.712 0 ; - END -END UART - -END LIBRARY diff --git a/pnr/output/UART.lvs.v b/pnr/output/UART.lvs.v deleted file mode 100644 index 4e001d8..0000000 --- a/pnr/output/UART.lvs.v +++ /dev/null @@ -1,2063 +0,0 @@ -// IC Compiler II Verilog Writer -// Generated on 04/24/2024 at 19:58:07 -// Library Name: UART.dlib -// Block Name: UART -// User Label: -// Write Command: write_verilog -exclude { empty_modules end_cap_cells well_tap_cells } output/UART.lvs.v -module stp_chk_test_1 ( CLK , RST , sampled_bit , Enable , stp_err , test_si , - test_se , VDD , VSS , dftopt0 , dftopt1 ) ; -input CLK ; -input RST ; -input sampled_bit ; -input Enable ; -output stp_err ; -input test_si ; -input test_se ; -input VDD ; -input VSS ; -input dftopt0 ; -input dftopt1 ; - -wire n2 ; -wire n4 ; -wire n1 ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT stp_err_reg ( .D ( n4 ) , .SI ( dftopt1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( stp_err ) , .QN ( n2 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -OAI22X1_RVT U2 ( .A1 ( sampled_bit ) , .A2 ( n1 ) , .A3 ( Enable ) , - .A4 ( n2 ) , .Y ( n4 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U3 ( .A ( Enable ) , .Y ( n1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module par_chk_DATA_WIDTH8_test_1 ( CLK , RST , parity_type , sampled_bit , - Enable , P_DATA , par_err , test_si , test_so , test_se , VDD , VSS , - dftopt0 ) ; -input CLK ; -input RST ; -input parity_type ; -input sampled_bit ; -input Enable ; -input [7:0] P_DATA ; -output par_err ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt0 ; - -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n7 ; -wire n9 ; -wire n1 ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT par_err_reg ( .D ( n9 ) , .SI ( dftopt0 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( par_err ) , .QN ( test_so ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U2 ( .A1 ( par_err ) , .A2 ( n1 ) , .A3 ( Enable ) , .A4 ( n2 ) , - .Y ( n9 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR3X1_RVT U3 ( .A1 ( n3 ) , .A2 ( n4 ) , .A3 ( n5 ) , .Y ( n2 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR3X1_RVT U5 ( .A1 ( P_DATA[1] ) , .A2 ( P_DATA[0] ) , .A3 ( n6 ) , - .Y ( n4 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR3X1_RVT U7 ( .A1 ( P_DATA[4] ) , .A2 ( P_DATA[5] ) , .A3 ( n7 ) , - .Y ( n3 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U4 ( .A1 ( P_DATA[7] ) , .A2 ( P_DATA[6] ) , .Y ( n7 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U6 ( .A1 ( P_DATA[3] ) , .A2 ( P_DATA[2] ) , .Y ( n6 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U8 ( .A1 ( sampled_bit ) , .A2 ( parity_type ) , .Y ( n5 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U9 ( .A ( Enable ) , .Y ( n1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module strt_chk_test_1 ( CLK , RST , sampled_bit , Enable , strt_glitch , - test_si , test_so , test_se , VDD , VSS , dftopt0 ) ; -input CLK ; -input RST ; -input sampled_bit ; -input Enable ; -output strt_glitch ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt0 ; - -wire n3 ; -wire n1 ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT strt_glitch_reg ( .D ( n3 ) , .SI ( dftopt0 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( strt_glitch ) , .QN ( test_so ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U2 ( .A1 ( sampled_bit ) , .A2 ( Enable ) , .A3 ( strt_glitch ) , - .A4 ( n1 ) , .Y ( n3 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U3 ( .A ( Enable ) , .Y ( n1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module deserializer_DATA_WIDTH8_test_1 ( CLK , RST , sampled_bit , Enable , - edge_count , Prescale , P_DATA , test_si , test_so , test_se , VDD , VSS , - dftopt1 , dftopt0 ) ; -input CLK ; -input RST ; -input sampled_bit ; -input Enable ; -input [5:0] edge_count ; -input [5:0] Prescale ; -output [7:0] P_DATA ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt1 ; -output dftopt0 ; - -wire N2 ; -wire N3 ; -wire N4 ; -wire N5 ; -wire N6 ; -wire N7 ; -wire n1 ; -wire n18 ; -wire n20 ; -wire n22 ; -wire n24 ; -wire n26 ; -wire n28 ; -wire n30 ; -wire n32 ; -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n7 ; -wire n8 ; -wire n9 ; -wire n10 ; -wire n11 ; -wire n12 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n16 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n43 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire n50 ; -wire n51 ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT P_DATA_reg_7_ ( .D ( n32 ) , .SI ( n46 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[7] ) , .QN ( test_so ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_6_ ( .D ( n30 ) , .SI ( n48 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[6] ) , .QN ( n46 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_5_ ( .D ( n28 ) , .SI ( test_si ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[5] ) , .QN ( n47 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_4_ ( .D ( n26 ) , .SI ( n49 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[4] ) , .QN ( n48 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_3_ ( .D ( n24 ) , .SI ( n50 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[3] ) , .QN ( n49 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_2_ ( .D ( n22 ) , .SI ( n47 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[2] ) , .QN ( n50 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_1_ ( .D ( n20 ) , .SI ( dftopt1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[1] ) , .QN ( n51 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT P_DATA_reg_0_ ( .D ( n18 ) , .SI ( n51 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[0] ) , .QN ( dftopt0 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U3 ( .A1 ( n1 ) , .A2 ( P_DATA[0] ) , .A3 ( n43 ) , - .A4 ( P_DATA[1] ) , .Y ( n18 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U4 ( .A1 ( n1 ) , .A2 ( P_DATA[1] ) , .A3 ( n43 ) , - .A4 ( P_DATA[2] ) , .Y ( n20 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U6 ( .A1 ( n1 ) , .A2 ( P_DATA[2] ) , .A3 ( n43 ) , - .A4 ( P_DATA[3] ) , .Y ( n22 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U8 ( .A1 ( n1 ) , .A2 ( P_DATA[3] ) , .A3 ( n43 ) , - .A4 ( P_DATA[4] ) , .Y ( n24 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U10 ( .A1 ( n1 ) , .A2 ( P_DATA[4] ) , .A3 ( n43 ) , - .A4 ( P_DATA[5] ) , .Y ( n26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U12 ( .A1 ( n1 ) , .A2 ( P_DATA[5] ) , .A3 ( n43 ) , - .A4 ( P_DATA[6] ) , .Y ( n28 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U14 ( .A1 ( n1 ) , .A2 ( P_DATA[6] ) , .A3 ( n43 ) , - .A4 ( P_DATA[7] ) , .Y ( n30 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U16 ( .A1 ( n1 ) , .A2 ( P_DATA[7] ) , .A3 ( sampled_bit ) , - .A4 ( n43 ) , .Y ( n32 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U5 ( .A ( n1 ) , .Y ( n43 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U7 ( .A ( N2 ) , .Y ( n34 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U9 ( .A1 ( N7 ) , .A2 ( Enable ) , .Y ( n1 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX1_RVT U11 ( .A ( edge_count[1] ) , .Y ( n35 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX1_RVT U13 ( .A ( n2 ) , .Y ( n6 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U15 ( .A ( n3 ) , .Y ( n7 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U17 ( .A ( Prescale[4] ) , .Y ( n8 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U18 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .Y ( n2 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U19 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .A3 ( n6 ) , - .Y ( N2 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U28 ( .A1 ( n2 ) , .A2 ( Prescale[2] ) , .Y ( n3 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U29 ( .A1 ( Prescale[2] ) , .A2 ( n2 ) , .A3 ( n7 ) , .Y ( N3 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U30 ( .A1 ( n3 ) , .A2 ( Prescale[3] ) , .Y ( n4 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U31 ( .A1 ( Prescale[3] ) , .A2 ( n3 ) , .A3 ( n4 ) , .Y ( N4 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U32 ( .A1 ( n8 ) , .A2 ( n4 ) , .Y ( N5 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND2X0_RVT U33 ( .A1 ( n4 ) , .A2 ( n8 ) , .Y ( n5 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XNOR2X1_RVT U34 ( .A1 ( n5 ) , .A2 ( Prescale[5] ) , .Y ( N6 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U35 ( .A1 ( N4 ) , .A2 ( edge_count[3] ) , .Y ( n11 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U36 ( .A1 ( N3 ) , .A2 ( edge_count[2] ) , .Y ( n10 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U37 ( .A1 ( N5 ) , .A2 ( edge_count[4] ) , .Y ( n9 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND3X0_RVT U38 ( .A1 ( n11 ) , .A2 ( n10 ) , .A3 ( n9 ) , .Y ( n33 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U39 ( .A1 ( N6 ) , .A2 ( edge_count[5] ) , .Y ( n16 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U40 ( .A1 ( Prescale[0] ) , .A2 ( edge_count[0] ) , .Y ( n12 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -OA22X1_RVT U41 ( .A1 ( N2 ) , .A2 ( n12 ) , .A3 ( n12 ) , .A4 ( n35 ) , - .Y ( n15 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U42 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[0] ) , .Y ( n13 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -OA22X1_RVT U43 ( .A1 ( n13 ) , .A2 ( n34 ) , .A3 ( edge_count[1] ) , - .A4 ( n13 ) , .Y ( n14 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR4X0_RVT U44 ( .A1 ( n33 ) , .A2 ( n16 ) , .A3 ( n15 ) , .A4 ( n14 ) , - .Y ( N7 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module data_sampling_test_1 ( CLK , RST , S_DATA , Prescale , edge_count , - Enable , sampled_bit , test_si , test_so , test_se , VDD , VSS , dftopt0 , - dftopt1 , dftopt2 , dftopt3 , dftopt4 , dftopt5 , dftopt9 , dftopt6 , - dftopt12 ) ; -input CLK ; -input RST ; -input S_DATA ; -input [5:0] Prescale ; -input [5:0] edge_count ; -input Enable ; -output sampled_bit ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt0 ; -output dftopt1 ; -input dftopt2 ; -input dftopt3 ; -output dftopt4 ; -input dftopt5 ; -input dftopt9 ; -output dftopt6 ; -input dftopt12 ; - -wire N58 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n1 ; -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n11 ; -wire n12 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n16 ; -wire n17 ; -wire n18 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n32 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n36 ; -wire n37 ; -wire n38 ; -wire n39 ; -wire n40 ; -wire n41 ; -wire n42 ; -wire n43 ; -wire n44 ; -wire n45 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire n50 ; -wire n51 ; -wire n52 ; -wire n53 ; -wire n54 ; -wire [4:0] half_edges ; -wire [4:1] half_edges_p1 ; -wire [4:1] half_edges_n1 ; -wire [4:2] add_21_carry ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT Samples_reg_2_ ( .D ( n25 ) , .SI ( dftopt12 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n33 ) , - .QN ( dftopt4 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT Samples_reg_1_ ( .D ( n24 ) , .SI ( dftopt9 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n2 ) , .QN ( dftopt1 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT Samples_reg_0_ ( .D ( n23 ) , .SI ( dftopt5 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n1 ) , .QN ( dftopt6 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT sampled_bit_reg ( .D ( N58 ) , .SI ( dftopt2 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( sampled_bit ) , - .QN ( test_so ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -HADDX1_RVT add_21_U1_1_1 ( .A0 ( half_edges[1] ) , .B0 ( half_edges[0] ) , - .C1 ( add_21_carry[2] ) , .SO ( half_edges_p1[1] ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -HADDX1_RVT add_21_U1_1_2 ( .A0 ( half_edges[2] ) , .B0 ( add_21_carry[2] ) , - .C1 ( add_21_carry[3] ) , .SO ( half_edges_p1[2] ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -HADDX1_RVT add_21_U1_1_3 ( .A0 ( half_edges[3] ) , .B0 ( add_21_carry[3] ) , - .C1 ( add_21_carry[4] ) , .SO ( half_edges_p1[3] ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX1_RVT U4 ( .A ( half_edges[3] ) , .Y ( n16 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX1_RVT U5 ( .A ( n12 ) , .Y ( n15 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U6 ( .A ( n3 ) , .Y ( n6 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U10 ( .A ( Prescale[4] ) , .Y ( n11 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX0_RVT U11 ( .A ( Prescale[1] ) , .Y ( half_edges[0] ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -OR2X1_RVT U12 ( .A1 ( Prescale[2] ) , .A2 ( Prescale[1] ) , .Y ( n3 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U13 ( .A1 ( Prescale[2] ) , .A2 ( Prescale[1] ) , .A3 ( n6 ) , - .Y ( half_edges[1] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U14 ( .A1 ( n3 ) , .A2 ( Prescale[3] ) , .Y ( n4 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U15 ( .A1 ( Prescale[3] ) , .A2 ( n3 ) , .A3 ( n4 ) , - .Y ( half_edges[2] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U16 ( .A1 ( n11 ) , .A2 ( n4 ) , .Y ( half_edges[3] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U17 ( .A1 ( n4 ) , .A2 ( n11 ) , .Y ( n5 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XNOR2X1_RVT U18 ( .A1 ( n5 ) , .A2 ( Prescale[5] ) , .Y ( half_edges[4] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U19 ( .A1 ( add_21_carry[4] ) , .A2 ( half_edges[4] ) , - .Y ( half_edges_p1[4] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U20 ( .A1 ( half_edges[1] ) , .A2 ( half_edges[0] ) , .Y ( n12 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U21 ( .A1 ( half_edges[1] ) , .A2 ( half_edges[0] ) , .A3 ( n15 ) , - .Y ( half_edges_n1[1] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U22 ( .A1 ( n12 ) , .A2 ( half_edges[2] ) , .Y ( n13 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U23 ( .A1 ( half_edges[2] ) , .A2 ( n12 ) , .A3 ( n13 ) , - .Y ( half_edges_n1[2] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U24 ( .A1 ( n16 ) , .A2 ( n13 ) , .Y ( half_edges_n1[3] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U25 ( .A1 ( n13 ) , .A2 ( n16 ) , .Y ( n14 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XNOR2X1_RVT U26 ( .A1 ( n14 ) , .A2 ( half_edges[4] ) , - .Y ( half_edges_n1[4] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -MUX21X1_RVT U27 ( .A1 ( n17 ) , .A2 ( n18 ) , .S0 ( n19 ) , .Y ( n25 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR4X0_RVT U28 ( .A1 ( n20 ) , .A2 ( n21 ) , .A3 ( n22 ) , .A4 ( n26 ) , - .Y ( n19 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U29 ( .A1 ( half_edges_p1[2] ) , .A2 ( edge_count[2] ) , - .Y ( n26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U30 ( .A1 ( n27 ) , .A2 ( n28 ) , .Y ( n21 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND4X0_RVT U31 ( .A1 ( n29 ) , .A2 ( n30 ) , .A3 ( n31 ) , .A4 ( n32 ) , - .Y ( n20 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U32 ( .A1 ( edge_count[3] ) , .A2 ( half_edges_p1[3] ) , - .Y ( n32 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U33 ( .A1 ( edge_count[4] ) , .A2 ( half_edges_p1[4] ) , - .Y ( n31 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U34 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[1] ) , .Y ( n30 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U35 ( .A1 ( edge_count[1] ) , .A2 ( half_edges_p1[1] ) , - .Y ( n29 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U36 ( .A1 ( Enable ) , .A2 ( n33 ) , .Y ( n17 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -MUX21X1_RVT U37 ( .A1 ( n34 ) , .A2 ( n18 ) , .S0 ( n22 ) , .Y ( n24 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND4X1_RVT U38 ( .A1 ( n35 ) , .A2 ( n36 ) , .A3 ( n37 ) , .A4 ( n38 ) , - .Y ( n22 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND4X1_RVT U39 ( .A1 ( n39 ) , .A2 ( n40 ) , .A3 ( n27 ) , .A4 ( n28 ) , - .Y ( n38 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U40 ( .A1 ( n41 ) , .A2 ( half_edges[0] ) , .Y ( n40 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U41 ( .A1 ( n42 ) , .A2 ( half_edges[1] ) , .Y ( n39 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U42 ( .A1 ( n43 ) , .A2 ( half_edges[3] ) , .Y ( n37 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U43 ( .A1 ( n44 ) , .A2 ( half_edges[4] ) , .Y ( n36 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U44 ( .A1 ( n45 ) , .A2 ( half_edges[2] ) , .Y ( n35 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U45 ( .A1 ( Enable ) , .A2 ( n2 ) , .Y ( n34 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -MUX21X1_RVT U46 ( .A1 ( n18 ) , .A2 ( n46 ) , .S0 ( n27 ) , .Y ( n23 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND4X0_RVT U47 ( .A1 ( n47 ) , .A2 ( n48 ) , .A3 ( n49 ) , .A4 ( n50 ) , - .Y ( n27 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND3X1_RVT U48 ( .A1 ( n51 ) , .A2 ( n28 ) , .A3 ( n52 ) , .Y ( n50 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U49 ( .A1 ( n45 ) , .A2 ( half_edges_n1[2] ) , .Y ( n52 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U50 ( .A ( edge_count[2] ) , .Y ( n45 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX0_RVT U51 ( .A ( edge_count[5] ) , .Y ( n28 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XOR2X1_RVT U52 ( .A1 ( n43 ) , .A2 ( half_edges_n1[3] ) , .Y ( n51 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U53 ( .A ( edge_count[3] ) , .Y ( n43 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XOR2X1_RVT U54 ( .A1 ( n41 ) , .A2 ( Prescale[1] ) , .Y ( n49 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U55 ( .A ( edge_count[0] ) , .Y ( n41 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XOR2X1_RVT U56 ( .A1 ( n42 ) , .A2 ( half_edges_n1[1] ) , .Y ( n48 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U57 ( .A ( edge_count[1] ) , .Y ( n42 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XOR2X1_RVT U58 ( .A1 ( n44 ) , .A2 ( half_edges_n1[4] ) , .Y ( n47 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U59 ( .A ( edge_count[4] ) , .Y ( n44 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U60 ( .A1 ( Enable ) , .A2 ( n1 ) , .Y ( n46 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U61 ( .A1 ( S_DATA ) , .A2 ( Enable ) , .Y ( n18 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U62 ( .A1 ( Enable ) , .A2 ( n53 ) , .Y ( N58 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO22X1_RVT U63 ( .A1 ( n2 ) , .A2 ( n1 ) , .A3 ( n54 ) , .A4 ( n33 ) , - .Y ( n53 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U64 ( .A1 ( dftopt6 ) , .A2 ( dftopt1 ) , .Y ( n54 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module edge_bit_counter_test_1 ( CLK , RST , Enable , Prescale , bit_count , - edge_count , test_si , test_so , test_se , VDD , VSS , dftopt0 , dftopt4 , - dftopt1 , dftopt2 , dftopt3 , dftopt5 , dftopt6 , HFSNET_0 , HFSNET_1 , - dftopt14 , dftopt7 , dftopt8 , dftopt9 , dftopt16 , dftopt10 , dftopt11 , - dftopt12 , dftopt13 ) ; -input CLK ; -input RST ; -input Enable ; -input [5:0] Prescale ; -output [3:0] bit_count ; -output [5:0] edge_count ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt0 ; -input dftopt4 ; -output dftopt1 ; -input dftopt2 ; -output dftopt3 ; -input dftopt5 ; -output dftopt6 ; -input HFSNET_0 ; -input HFSNET_1 ; -input dftopt14 ; -output dftopt7 ; -output dftopt8 ; -output dftopt9 ; -input dftopt16 ; -output dftopt10 ; -input dftopt11 ; -output dftopt12 ; -output dftopt13 ; - -wire N8 ; -wire N9 ; -wire N10 ; -wire N11 ; -wire N12 ; -wire N19 ; -wire N20 ; -wire N21 ; -wire N22 ; -wire N23 ; -wire N24 ; -wire N26 ; -wire N27 ; -wire N28 ; -wire N29 ; -wire N30 ; -wire N31 ; -wire dftopt7_gOb13 ; -wire dftopt8_gOb14 ; -wire n18 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n32 ; -wire n1 ; -wire n13 ; -wire n17 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n36 ; -wire n37 ; -wire n38 ; -wire n39 ; -wire n40 ; -wire n41 ; -wire n42 ; -wire n43 ; -wire n44 ; -wire n45 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire dftopt3_gOb5 ; -wire n53 ; -wire [5:2] add_31_carry ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT edge_count_reg_0_ ( .D ( N19 ) , .SI ( dftopt8_gOb14 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[0] ) , .QN ( n1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT edge_count_reg_5_ ( .D ( N24 ) , .SI ( dftopt0 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[5] ) , .QN ( dftopt9 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT edge_count_reg_1_ ( .D ( N20 ) , .SI ( dftopt7_gOb13 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[1] ) , .QN ( dftopt13 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT edge_count_reg_2_ ( .D ( N21 ) , .SI ( n53 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , .Q ( edge_count[2] ) , - .QN ( dftopt12 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT edge_count_reg_3_ ( .D ( N22 ) , .SI ( dftopt3_gOb5 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[3] ) , .QN ( n53 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT edge_count_reg_4_ ( .D ( N23 ) , .SI ( dftopt11 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[4] ) , .QN ( dftopt3_gOb5 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT bit_count_reg_0_ ( .D ( n32 ) , .SI ( dftopt5 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( bit_count[0] ) , .QN ( dftopt8_gOb14 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT bit_count_reg_1_ ( .D ( n31 ) , .SI ( n1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , .Q ( bit_count[1] ) , - .QN ( dftopt7_gOb13 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT bit_count_reg_2_ ( .D ( n30 ) , .SI ( dftopt4 ) , - .SE ( HFSNET_0 ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( bit_count[2] ) , - .QN ( dftopt1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT bit_count_reg_3_ ( .D ( n29 ) , .SI ( dftopt16 ) , - .SE ( HFSNET_0 ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( bit_count[3] ) , - .QN ( dftopt10 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U16 ( .A1 ( n18 ) , .A2 ( n19 ) , .Y ( n29 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND4X0_RVT U17 ( .A1 ( Enable ) , .A2 ( n20 ) , .A3 ( n21 ) , - .A4 ( bit_count[2] ) , .Y ( n19 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U18 ( .A1 ( N31 ) , .A2 ( dftopt10 ) , .Y ( n21 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U19 ( .A1 ( n22 ) , .A2 ( n23 ) , .A3 ( dftopt10 ) , .Y ( n18 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U20 ( .A1 ( n20 ) , .A2 ( bit_count[2] ) , .A3 ( n49 ) , - .Y ( n23 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U21 ( .A1 ( bit_count[1] ) , .A2 ( bit_count[0] ) , .Y ( n20 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U22 ( .A1 ( bit_count[2] ) , .A2 ( n24 ) , .A3 ( n25 ) , - .A4 ( n26 ) , .Y ( n30 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U23 ( .A1 ( dftopt7_gOb13 ) , .A2 ( bit_count[2] ) , .Y ( n25 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U24 ( .A1 ( Enable ) , .A2 ( dftopt7_gOb13 ) , .A3 ( n27 ) , - .Y ( n24 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U25 ( .A1 ( bit_count[1] ) , .A2 ( n27 ) , .A3 ( n26 ) , - .A4 ( dftopt7_gOb13 ) , .Y ( n31 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND3X1_RVT U26 ( .A1 ( bit_count[0] ) , .A2 ( n22 ) , .A3 ( Enable ) , - .Y ( n26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U27 ( .A1 ( Enable ) , .A2 ( dftopt8_gOb14 ) , .A3 ( n48 ) , - .Y ( n27 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U28 ( .A1 ( n48 ) , .A2 ( bit_count[0] ) , .A3 ( n28 ) , - .A4 ( Enable ) , .Y ( n32 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U29 ( .A1 ( n22 ) , .A2 ( dftopt8_gOb14 ) , .Y ( n28 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U30 ( .A1 ( N12 ) , .A2 ( n48 ) , .Y ( N24 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U31 ( .A1 ( N11 ) , .A2 ( n48 ) , .Y ( N23 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U32 ( .A1 ( N10 ) , .A2 ( n48 ) , .Y ( N22 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U33 ( .A1 ( N9 ) , .A2 ( n48 ) , .Y ( N21 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U34 ( .A1 ( N8 ) , .A2 ( n48 ) , .Y ( N20 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U35 ( .A1 ( n1 ) , .A2 ( n48 ) , .Y ( N19 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -OR2X1_RVT U36 ( .A1 ( n49 ) , .A2 ( N31 ) , .Y ( n22 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -HADDX1_RVT add_31_U1_1_1 ( .A0 ( edge_count[1] ) , .B0 ( edge_count[0] ) , - .C1 ( add_31_carry[2] ) , .SO ( N8 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -HADDX1_RVT add_31_U1_1_2 ( .A0 ( edge_count[2] ) , .B0 ( add_31_carry[2] ) , - .C1 ( add_31_carry[3] ) , .SO ( N9 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -HADDX1_RVT add_31_U1_1_3 ( .A0 ( edge_count[3] ) , .B0 ( add_31_carry[3] ) , - .C1 ( add_31_carry[4] ) , .SO ( N10 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -HADDX1_RVT add_31_U1_1_4 ( .A0 ( edge_count[4] ) , .B0 ( add_31_carry[4] ) , - .C1 ( add_31_carry[5] ) , .SO ( N11 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U6 ( .A ( n22 ) , .Y ( n48 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U14 ( .A ( Enable ) , .Y ( n49 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U15 ( .A ( N26 ) , .Y ( n47 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U37 ( .A ( n13 ) , .Y ( n35 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U38 ( .A ( n17 ) , .Y ( n36 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U39 ( .A ( Prescale[4] ) , .Y ( n37 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -OR2X1_RVT U40 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .Y ( n13 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U41 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .A3 ( n35 ) , - .Y ( N26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U42 ( .A1 ( n13 ) , .A2 ( Prescale[2] ) , .Y ( n17 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U43 ( .A1 ( Prescale[2] ) , .A2 ( n13 ) , .A3 ( n36 ) , - .Y ( N27 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U44 ( .A1 ( n17 ) , .A2 ( Prescale[3] ) , .Y ( n33 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U45 ( .A1 ( Prescale[3] ) , .A2 ( n17 ) , .A3 ( n33 ) , - .Y ( N28 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U46 ( .A1 ( n37 ) , .A2 ( n33 ) , .Y ( N29 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND2X0_RVT U47 ( .A1 ( n33 ) , .A2 ( n37 ) , .Y ( n34 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XNOR2X1_RVT U48 ( .A1 ( n34 ) , .A2 ( Prescale[5] ) , .Y ( N30 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U49 ( .A1 ( add_31_carry[5] ) , .A2 ( edge_count[5] ) , - .Y ( N12 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U50 ( .A1 ( N28 ) , .A2 ( edge_count[3] ) , .Y ( n40 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U51 ( .A1 ( N27 ) , .A2 ( edge_count[2] ) , .Y ( n39 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U52 ( .A1 ( N29 ) , .A2 ( edge_count[4] ) , .Y ( n38 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND3X0_RVT U53 ( .A1 ( n40 ) , .A2 ( n39 ) , .A3 ( n38 ) , .Y ( n46 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XOR2X1_RVT U54 ( .A1 ( N30 ) , .A2 ( edge_count[5] ) , .Y ( n45 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U55 ( .A1 ( Prescale[0] ) , .A2 ( edge_count[0] ) , .Y ( n41 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -OA22X1_RVT U56 ( .A1 ( N26 ) , .A2 ( n41 ) , .A3 ( n41 ) , .A4 ( dftopt13 ) , - .Y ( n44 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U57 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[0] ) , .Y ( n42 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -OA22X1_RVT U58 ( .A1 ( n42 ) , .A2 ( n47 ) , .A3 ( edge_count[1] ) , - .A4 ( n42 ) , .Y ( n43 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR4X0_RVT U59 ( .A1 ( n46 ) , .A2 ( n45 ) , .A3 ( n44 ) , .A4 ( n43 ) , - .Y ( N31 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module uart_rx_fsm_DATA_WIDTH8_test_1 ( CLK , RST , S_DATA , Prescale , - parity_enable , bit_count , edge_count , par_err , stp_err , strt_glitch , - strt_chk_en , edge_bit_en , deser_en , par_chk_en , stp_chk_en , - dat_samp_en , data_valid , test_si , test_so , test_se , VDD , VSS , - dftopt1 , dftopt0 , dftopt7 , dftopt8 , dftopt2 ) ; -input CLK ; -input RST ; -input S_DATA ; -input [5:0] Prescale ; -input parity_enable ; -input [3:0] bit_count ; -input [5:0] edge_count ; -input par_err ; -input stp_err ; -input strt_glitch ; -output strt_chk_en ; -output edge_bit_en ; -output deser_en ; -output par_chk_en ; -output stp_chk_en ; -output dat_samp_en ; -output data_valid ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt1 ; -output dftopt0 ; -input dftopt7 ; -input dftopt8 ; -input dftopt2 ; - -wire error_check_edge_5_ ; -wire error_check_edge_4_ ; -wire error_check_edge_3_ ; -wire error_check_edge_2_ ; -wire error_check_edge_1_ ; -wire n18 ; -wire n1 ; -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n7 ; -wire n8 ; -wire n9 ; -wire n13 ; -wire n14 ; -wire n16 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n32 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n36 ; -wire n37 ; -wire n38 ; -wire n39 ; -wire n40 ; -wire n41 ; -wire n42 ; -wire n43 ; -wire n44 ; -wire n45 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire n50 ; -wire n51 ; -wire n52 ; -wire n53 ; -wire n54 ; -wire n55 ; -wire n56 ; -wire n57 ; -wire n58 ; -wire n59 ; -wire [5:0] check_edge ; -wire [2:0] next_state ; -wire [5:3] sub_40_carry ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT current_state_reg_0_ ( .D ( next_state[0] ) , .SI ( dftopt2 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n2 ) , .QN ( n18 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT current_state_reg_2_ ( .D ( next_state[2] ) , .SI ( stp_err ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n1 ) , - .QN ( test_so ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT current_state_reg_1_ ( .D ( next_state[1] ) , .SI ( n2 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n28 ) , - .QN ( dftopt0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U4 ( .A ( n3 ) , .Y ( n7 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U5 ( .A ( n4 ) , .Y ( n8 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U6 ( .A ( Prescale[4] ) , .Y ( n9 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U9 ( .A ( Prescale[1] ) , .Y ( error_check_edge_1_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U10 ( .A1 ( Prescale[5] ) , .A2 ( sub_40_carry[5] ) , - .Y ( error_check_edge_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U11 ( .A1 ( Prescale[4] ) , .A2 ( sub_40_carry[4] ) , - .Y ( sub_40_carry[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U12 ( .A1 ( sub_40_carry[4] ) , .A2 ( Prescale[4] ) , - .Y ( error_check_edge_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U13 ( .A1 ( Prescale[3] ) , .A2 ( sub_40_carry[3] ) , - .Y ( sub_40_carry[4] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U14 ( .A1 ( sub_40_carry[3] ) , .A2 ( Prescale[3] ) , - .Y ( error_check_edge_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U15 ( .A1 ( Prescale[2] ) , .A2 ( Prescale[1] ) , - .Y ( sub_40_carry[3] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U16 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[2] ) , - .Y ( error_check_edge_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U17 ( .A ( Prescale[0] ) , .Y ( check_edge[0] ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -OR2X1_RVT U18 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .Y ( n3 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U19 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .A3 ( n7 ) , - .Y ( check_edge[1] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U20 ( .A1 ( n3 ) , .A2 ( Prescale[2] ) , .Y ( n4 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U21 ( .A1 ( Prescale[2] ) , .A2 ( n3 ) , .A3 ( n8 ) , - .Y ( check_edge[2] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR2X0_RVT U22 ( .A1 ( n4 ) , .A2 ( Prescale[3] ) , .Y ( n5 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U23 ( .A1 ( Prescale[3] ) , .A2 ( n4 ) , .A3 ( n5 ) , - .Y ( check_edge[3] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U24 ( .A1 ( n9 ) , .A2 ( n5 ) , .Y ( check_edge[4] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U25 ( .A1 ( n5 ) , .A2 ( n9 ) , .Y ( n6 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XNOR2X1_RVT U26 ( .A1 ( n6 ) , .A2 ( Prescale[5] ) , .Y ( check_edge[5] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U27 ( .A ( n13 ) , .Y ( strt_chk_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U28 ( .A1 ( n14 ) , .A2 ( test_so ) , .Y ( par_chk_en ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U29 ( .A1 ( n16 ) , .A2 ( n19 ) , .Y ( next_state[2] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND3X0_RVT U30 ( .A1 ( bit_count[3] ) , .A2 ( n20 ) , .A3 ( n21 ) , - .Y ( n19 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -MUX21X1_RVT U31 ( .A1 ( n14 ) , .A2 ( n22 ) , .S0 ( n23 ) , .Y ( n21 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U32 ( .A1 ( deser_en ) , .A2 ( n24 ) , .Y ( n22 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U33 ( .A1 ( test_so ) , .A2 ( n25 ) , .A3 ( n14 ) , - .Y ( next_state[1] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U34 ( .A1 ( n26 ) , .A2 ( n27 ) , .A3 ( n28 ) , .Y ( n25 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U35 ( .A ( strt_glitch ) , .Y ( n27 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO221X1_RVT U36 ( .A1 ( n29 ) , .A2 ( n30 ) , .A3 ( deser_en ) , .A4 ( n31 ) , - .A5 ( n32 ) , .Y ( next_state[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U37 ( .A1 ( n33 ) , .A2 ( n34 ) , .Y ( n32 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND4X0_RVT U38 ( .A1 ( n42 ) , .A2 ( n45 ) , .A3 ( n37 ) , .A4 ( n38 ) , - .Y ( n34 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND4X1_RVT U39 ( .A1 ( n43 ) , .A2 ( n40 ) , .A3 ( n39 ) , .A4 ( n41 ) , - .Y ( n38 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND3X1_RVT U40 ( .A1 ( bit_count[3] ) , .A2 ( stp_chk_en ) , .A3 ( n35 ) , - .Y ( n41 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U41 ( .A1 ( bit_count[1] ) , .A2 ( bit_count[0] ) , .Y ( n42 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U42 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[0] ) , .Y ( n40 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U43 ( .A ( n16 ) , .Y ( stp_chk_en ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U44 ( .A1 ( n14 ) , .A2 ( n1 ) , .Y ( n16 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX0_RVT U45 ( .A ( n44 ) , .Y ( n14 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U46 ( .A1 ( edge_count[1] ) , .A2 ( error_check_edge_1_ ) , - .Y ( n39 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND3X1_RVT U47 ( .A1 ( n46 ) , .A2 ( n36 ) , .A3 ( n47 ) , .Y ( n37 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U48 ( .A1 ( edge_count[3] ) , .A2 ( error_check_edge_3_ ) , - .Y ( n47 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U49 ( .A1 ( edge_count[4] ) , .A2 ( error_check_edge_4_ ) , - .Y ( n46 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U50 ( .A1 ( edge_count[2] ) , .A2 ( error_check_edge_2_ ) , - .Y ( n45 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U51 ( .A1 ( edge_count[5] ) , .A2 ( error_check_edge_5_ ) , - .Y ( n36 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -MUX21X1_RVT U52 ( .A1 ( bit_count[1] ) , .A2 ( bit_count[0] ) , .S0 ( n24 ) , - .Y ( n35 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U53 ( .A ( parity_enable ) , .Y ( n24 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U54 ( .A1 ( strt_glitch ) , .A2 ( n26 ) , .A3 ( n13 ) , - .Y ( n33 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U55 ( .A1 ( n28 ) , .A2 ( n48 ) , .Y ( n13 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND4X1_RVT U56 ( .A1 ( n20 ) , .A2 ( n23 ) , .A3 ( n49 ) , .A4 ( n2 ) , - .Y ( n26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U57 ( .A ( bit_count[3] ) , .Y ( n49 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND3X0_RVT U58 ( .A1 ( n20 ) , .A2 ( n23 ) , .A3 ( bit_count[3] ) , - .Y ( n31 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U59 ( .A ( bit_count[0] ) , .Y ( n23 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NOR2X0_RVT U60 ( .A1 ( n50 ) , .A2 ( n51 ) , .Y ( n20 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND4X0_RVT U61 ( .A1 ( n52 ) , .A2 ( n53 ) , .A3 ( n54 ) , .A4 ( n55 ) , - .Y ( n51 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U62 ( .A1 ( edge_count[3] ) , .A2 ( check_edge[3] ) , .Y ( n55 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U63 ( .A1 ( edge_count[4] ) , .A2 ( check_edge[4] ) , .Y ( n54 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U64 ( .A1 ( edge_count[0] ) , .A2 ( check_edge[0] ) , .Y ( n53 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U65 ( .A1 ( edge_count[1] ) , .A2 ( check_edge[1] ) , .Y ( n52 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND4X0_RVT U66 ( .A1 ( n56 ) , .A2 ( n57 ) , .A3 ( n58 ) , .A4 ( n43 ) , - .Y ( n50 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U67 ( .A ( bit_count[2] ) , .Y ( n43 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -INVX0_RVT U68 ( .A ( bit_count[1] ) , .Y ( n58 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XNOR2X1_RVT U69 ( .A1 ( edge_count[5] ) , .A2 ( check_edge[5] ) , .Y ( n57 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U70 ( .A1 ( edge_count[2] ) , .A2 ( check_edge[2] ) , .Y ( n56 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U71 ( .A ( S_DATA ) , .Y ( n30 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX0_RVT U72 ( .A ( n59 ) , .Y ( n29 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U73 ( .A1 ( n48 ) , .A2 ( n44 ) , .Y ( edge_bit_en ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U74 ( .A1 ( n18 ) , .A2 ( n28 ) , .Y ( n44 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND3X1_RVT U75 ( .A1 ( n28 ) , .A2 ( n2 ) , .A3 ( test_so ) , - .Y ( deser_en ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR3X0_RVT U76 ( .A1 ( n59 ) , .A2 ( stp_err ) , .A3 ( par_err ) , - .Y ( data_valid ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND3X0_RVT U77 ( .A1 ( n28 ) , .A2 ( n2 ) , .A3 ( n1 ) , .Y ( n59 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NAND2X0_RVT U78 ( .A1 ( dftopt0 ) , .A2 ( n48 ) , .Y ( dat_samp_en ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U79 ( .A1 ( n18 ) , .A2 ( S_DATA ) , .A3 ( n1 ) , .Y ( n48 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module UART_RX_test_1 ( CLK , RST , RX_IN , parity_enable , parity_type , - Prescale , P_DATA , data_valid , parity_error , framing_error , test_si , - test_so , test_se , VDD , VSS , dftopt4 , dftopt8 , HFSNET_0 , HFSNET_2 , - dftopt9 , dftopt10 , dftopt14 , dftopt7 , dftopt16 , dftopt15 , dftopt20 ) ; -input CLK ; -input RST ; -input RX_IN ; -input parity_enable ; -input parity_type ; -input [5:0] Prescale ; -output [7:0] P_DATA ; -output data_valid ; -output parity_error ; -output framing_error ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt4 ; -output dftopt8 ; -input HFSNET_0 ; -input HFSNET_2 ; -output dftopt9 ; -output dftopt10 ; -input dftopt14 ; -output dftopt7 ; -input dftopt16 ; -output dftopt15 ; -output dftopt20 ; - -wire strt_glitch ; -wire strt_chk_en ; -wire edge_bit_en ; -wire deser_en ; -wire par_chk_en ; -wire stp_chk_en ; -wire dat_samp_en ; -wire sampled_bit ; -wire HFSNET_1 ; -wire n4 ; -wire dftopt9_gOb6 ; -wire dftopt2 ; -wire n7 ; -wire n8 ; -wire [3:0] bit_count ; -wire [5:0] edge_count ; -supply1 VDD ; -supply0 VSS ; -wire dftopt0 ; -wire dftopt1 ; -wire dftopt10_gOb10 ; -wire dftopt3 ; -wire dftopt6 ; -wire dftopt17 ; -wire dftopt18 ; -wire SYNOPSYS_UNCONNECTED_1 ; -wire SYNOPSYS_UNCONNECTED_2 ; -wire SYNOPSYS_UNCONNECTED_3 ; -wire SYNOPSYS_UNCONNECTED_4 ; -wire SYNOPSYS_UNCONNECTED_5 ; -wire SYNOPSYS_UNCONNECTED_6 ; -wire SYNOPSYS_UNCONNECTED_7 ; -wire SYNOPSYS_UNCONNECTED_8 ; -wire SYNOPSYS_UNCONNECTED_9 ; -wire SYNOPSYS_UNCONNECTED_10 ; -wire SYNOPSYS_UNCONNECTED_11 ; -wire SYNOPSYS_UNCONNECTED_12 ; -wire SYNOPSYS_UNCONNECTED_13 ; -wire SYNOPSYS_UNCONNECTED_14 ; -wire SYNOPSYS_UNCONNECTED_15 ; -wire SYNOPSYS_UNCONNECTED_16 ; -wire SYNOPSYS_UNCONNECTED_17 ; -wire SYNOPSYS_UNCONNECTED_18 ; -wire SYNOPSYS_UNCONNECTED_19 ; -wire SYNOPSYS_UNCONNECTED_20 ; - -NBUFFX8_RVT HFSBUF_432_1 ( .A ( HFSNET_2 ) , .Y ( HFSNET_1 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -uart_rx_fsm_DATA_WIDTH8_test_1 U0_uart_fsm ( .CLK ( CLK ) , - .RST ( HFSNET_1 ) , .S_DATA ( RX_IN ) , .Prescale ( Prescale ) , - .parity_enable ( parity_enable ) , .bit_count ( bit_count ) , - .edge_count ( edge_count ) , .par_err ( parity_error ) , - .stp_err ( framing_error ) , .strt_glitch ( strt_glitch ) , - .strt_chk_en ( strt_chk_en ) , .edge_bit_en ( edge_bit_en ) , - .deser_en ( deser_en ) , .par_chk_en ( par_chk_en ) , - .stp_chk_en ( stp_chk_en ) , .dat_samp_en ( dat_samp_en ) , - .data_valid ( data_valid ) , .test_si ( SYNOPSYS_UNCONNECTED_1 ) , - .test_so ( dftopt7 ) , .test_se ( test_se ) , .VDD ( VDD ) , - .VSS ( VSS ) , .dftopt1 ( SYNOPSYS_UNCONNECTED_2 ) , - .dftopt0 ( dftopt3 ) , .dftopt7 ( SYNOPSYS_UNCONNECTED_3 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_4 ) , .dftopt2 ( dftopt10_gOb10 ) ) ; -edge_bit_counter_test_1 U0_edge_bit_counter ( .CLK ( CLK ) , .RST ( RST ) , - .Enable ( edge_bit_en ) , .Prescale ( Prescale ) , - .bit_count ( bit_count ) , .edge_count ( edge_count ) , - .test_si ( SYNOPSYS_UNCONNECTED_5 ) , - .test_so ( SYNOPSYS_UNCONNECTED_6 ) , .test_se ( test_se ) , - .VDD ( VDD ) , .VSS ( VSS ) , .dftopt0 ( test_si ) , - .dftopt4 ( dftopt4 ) , .dftopt1 ( dftopt10_gOb10 ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_7 ) , - .dftopt3 ( SYNOPSYS_UNCONNECTED_8 ) , .dftopt5 ( dftopt6 ) , - .dftopt6 ( SYNOPSYS_UNCONNECTED_9 ) , .HFSNET_0 ( HFSNET_0 ) , - .HFSNET_1 ( HFSNET_1 ) , .dftopt14 ( SYNOPSYS_UNCONNECTED_10 ) , - .dftopt7 ( SYNOPSYS_UNCONNECTED_11 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_12 ) , .dftopt9 ( dftopt2 ) , - .dftopt16 ( dftopt16 ) , .dftopt10 ( dftopt15 ) , .dftopt11 ( dftopt17 ) , - .dftopt12 ( dftopt18 ) , .dftopt13 ( dftopt20 ) ) ; -data_sampling_test_1 U0_data_sampling ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .S_DATA ( RX_IN ) , - .Prescale ( { Prescale[5] , Prescale[4] , Prescale[3] , Prescale[2] , - Prescale[1] , SYNOPSYS_UNCONNECTED_13 } ) , - .edge_count ( edge_count ) , .Enable ( dat_samp_en ) , - .sampled_bit ( sampled_bit ) , .test_si ( SYNOPSYS_UNCONNECTED_14 ) , - .test_so ( n8 ) , .test_se ( test_se ) , .VDD ( VDD ) , .VSS ( VSS ) , - .dftopt0 ( SYNOPSYS_UNCONNECTED_15 ) , .dftopt1 ( dftopt0 ) , - .dftopt2 ( dftopt1 ) , .dftopt3 ( SYNOPSYS_UNCONNECTED_16 ) , - .dftopt4 ( dftopt6 ) , .dftopt5 ( n4 ) , .dftopt9 ( dftopt2 ) , - .dftopt6 ( dftopt17 ) , .dftopt12 ( dftopt18 ) ) ; -deserializer_DATA_WIDTH8_test_1 U0_deserializer ( .CLK ( CLK ) , - .RST ( HFSNET_1 ) , .sampled_bit ( sampled_bit ) , .Enable ( deser_en ) , - .edge_count ( edge_count ) , .Prescale ( Prescale ) , .P_DATA ( P_DATA ) , - .test_si ( n8 ) , .test_so ( n7 ) , .test_se ( test_se ) , .VDD ( VDD ) , - .VSS ( VSS ) , .dftopt1 ( dftopt0 ) , .dftopt0 ( dftopt1 ) ) ; -strt_chk_test_1 U0_strt_chk ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .sampled_bit ( sampled_bit ) , .Enable ( strt_chk_en ) , - .strt_glitch ( strt_glitch ) , .test_si ( SYNOPSYS_UNCONNECTED_17 ) , - .test_so ( n4 ) , .test_se ( test_se ) , .VDD ( VDD ) , .VSS ( VSS ) , - .dftopt0 ( dftopt3 ) ) ; -par_chk_DATA_WIDTH8_test_1 U0_par_chk ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .parity_type ( parity_type ) , .sampled_bit ( sampled_bit ) , - .Enable ( par_chk_en ) , .P_DATA ( P_DATA ) , .par_err ( parity_error ) , - .test_si ( SYNOPSYS_UNCONNECTED_18 ) , .test_so ( dftopt9_gOb6 ) , - .test_se ( test_se ) , .VDD ( VDD ) , .VSS ( VSS ) , .dftopt0 ( n7 ) ) ; -stp_chk_test_1 U0_stp_chk ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .sampled_bit ( sampled_bit ) , .Enable ( stp_chk_en ) , - .stp_err ( framing_error ) , .test_si ( SYNOPSYS_UNCONNECTED_19 ) , - .test_se ( test_se ) , .VDD ( VDD ) , .VSS ( VSS ) , - .dftopt0 ( SYNOPSYS_UNCONNECTED_20 ) , .dftopt1 ( dftopt9_gOb6 ) ) ; -endmodule - - -module parity_calc_WIDTH8_test_1 ( CLK , RST , parity_enable , parity_type , - Busy , DATA , Data_Valid , parity , test_si , test_so , test_se , VDD , - VSS , dftopt2 , dftopt0 , dftopt8 , dftopt1 , dftopt4 , dftopt3 , - dftopt9 , dftopt12 , dftopt5 , dftopt6 , dftopt17 , dftopt20 , dftopt7 ) ; -input CLK ; -input RST ; -input parity_enable ; -input parity_type ; -input Busy ; -input [7:0] DATA ; -input Data_Valid ; -output parity ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt2 ; -output dftopt0 ; -input dftopt8 ; -output dftopt1 ; -input dftopt4 ; -input dftopt3 ; -input dftopt9 ; -input dftopt12 ; -input dftopt5 ; -output dftopt6 ; -input dftopt17 ; -input dftopt20 ; -input dftopt7 ; - -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n8 ; -wire n18 ; -wire n20 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n27 ; -wire n29 ; -wire n31 ; -wire n33 ; -wire n35 ; -wire n37 ; -wire n39 ; -wire n41 ; -wire n43 ; -wire n1 ; -wire n6 ; -wire n7 ; -wire n10 ; -wire n11 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n16 ; -wire n17 ; -wire n28 ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT DATA_V_reg_7_ ( .D ( n43 ) , .SI ( dftopt20 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n11 ) , .QN ( n25 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_6_ ( .D ( n41 ) , .SI ( n1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( dftopt6 ) , .QN ( n24 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_5_ ( .D ( n39 ) , .SI ( n11 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n6 ) , .QN ( n23 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_4_ ( .D ( n37 ) , .SI ( n6 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( dftopt1 ) , .QN ( n22 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_3_ ( .D ( n35 ) , .SI ( dftopt17 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n13 ) , .QN ( dftopt0 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_2_ ( .D ( n33 ) , .SI ( n28 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n1 ) , .QN ( n20 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_1_ ( .D ( n31 ) , .SI ( n7 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n14 ) , .QN ( n28 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_0_ ( .D ( n29 ) , .SI ( dftopt5 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n7 ) , .QN ( n18 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SDFFARX1_RVT parity_reg ( .D ( n27 ) , .SI ( dftopt7 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( parity ) , .QN ( test_so ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U2 ( .A1 ( parity ) , .A2 ( n17 ) , .A3 ( parity_enable ) , - .A4 ( n2 ) , .Y ( n27 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR3X1_RVT U3 ( .A1 ( parity_type ) , .A2 ( n3 ) , .A3 ( n4 ) , .Y ( n2 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR3X1_RVT U4 ( .A1 ( n24 ) , .A2 ( n25 ) , .A3 ( n5 ) , .Y ( n4 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U9 ( .A1 ( n8 ) , .A2 ( n7 ) , .A3 ( DATA[0] ) , .A4 ( n15 ) , - .Y ( n29 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U11 ( .A1 ( n8 ) , .A2 ( n14 ) , .A3 ( DATA[1] ) , .A4 ( n15 ) , - .Y ( n31 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U13 ( .A1 ( n8 ) , .A2 ( n1 ) , .A3 ( DATA[2] ) , .A4 ( n15 ) , - .Y ( n33 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U15 ( .A1 ( n8 ) , .A2 ( n13 ) , .A3 ( DATA[3] ) , .A4 ( n15 ) , - .Y ( n35 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U17 ( .A1 ( n8 ) , .A2 ( dftopt1 ) , .A3 ( DATA[4] ) , - .A4 ( n15 ) , .Y ( n37 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U19 ( .A1 ( n8 ) , .A2 ( n6 ) , .A3 ( DATA[5] ) , .A4 ( n15 ) , - .Y ( n39 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U21 ( .A1 ( n8 ) , .A2 ( dftopt6 ) , .A3 ( DATA[6] ) , - .A4 ( n15 ) , .Y ( n41 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U23 ( .A1 ( n8 ) , .A2 ( n11 ) , .A3 ( DATA[7] ) , .A4 ( n15 ) , - .Y ( n43 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U5 ( .A ( n8 ) , .Y ( n15 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR3X1_RVT U6 ( .A1 ( n13 ) , .A2 ( n20 ) , .A3 ( n10 ) , .Y ( n3 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U7 ( .A1 ( n18 ) , .A2 ( n14 ) , .Y ( n10 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -XOR2X1_RVT U8 ( .A1 ( n22 ) , .A2 ( n23 ) , .Y ( n5 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND2X0_RVT U10 ( .A1 ( Data_Valid ) , .A2 ( n16 ) , .Y ( n8 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U12 ( .A ( Busy ) , .Y ( n16 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U14 ( .A ( parity_enable ) , .Y ( n17 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module mux_test_1 ( CLK , RST , IN_0 , IN_1 , IN_2 , IN_3 , SEL , OUT , - test_si , test_se , VDD , VSS , dftopt5 , p0 , p1 , dftopt0 , p2 , p3 ) ; -input CLK ; -input RST ; -input IN_0 ; -input IN_1 ; -input IN_2 ; -input IN_3 ; -input [1:0] SEL ; -output OUT ; -input test_si ; -input test_se ; -input VDD ; -input VSS ; -input dftopt5 ; -input p0 ; -input p1 ; -input dftopt0 ; -input p2 ; -input p3 ; - -wire mux_out ; -wire n4 ; -wire n5 ; -wire n2 ; -wire n3 ; -supply1 VDD ; -supply0 VSS ; -wire SYNOPSYS_UNCONNECTED_1 ; - -SDFFARX1_RVT OUT_reg ( .D ( mux_out ) , .SI ( dftopt0 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( OUT ) , - .QN ( SYNOPSYS_UNCONNECTED_1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U6 ( .A1 ( SEL[1] ) , .A2 ( n4 ) , .A3 ( n5 ) , .A4 ( n2 ) , - .Y ( mux_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U7 ( .A1 ( SEL[0] ) , .A2 ( IN_1 ) , .A3 ( p3 ) , .A4 ( n3 ) , - .Y ( n5 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U8 ( .A1 ( p2 ) , .A2 ( SEL[0] ) , .A3 ( IN_2 ) , .A4 ( n3 ) , - .Y ( n4 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U4 ( .A ( SEL[0] ) , .Y ( n3 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U5 ( .A ( SEL[1] ) , .Y ( n2 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module Serializer_WIDTH8_test_1 ( CLK , RST , DATA , Enable , Busy , - Data_Valid , ser_out , ser_done , test_si , test_so , test_se , VDD , - VSS , dftopt0 , dftopt1 , dftopt2 , dftopt3 , dftopt4 , dftopt9 , - dftopt5 , dftopt6 , dftopt7 , dftopt8 , dftopt10 , dftopt13 , dftopt11 , - dftopt12 ) ; -input CLK ; -input RST ; -input [7:0] DATA ; -input Enable ; -input Busy ; -input Data_Valid ; -output ser_out ; -output ser_done ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -output dftopt0 ; -input dftopt1 ; -output dftopt2 ; -input dftopt3 ; -output dftopt4 ; -input dftopt9 ; -output dftopt5 ; -input dftopt6 ; -input dftopt7 ; -output dftopt8 ; -output dftopt10 ; -input dftopt13 ; -output dftopt11 ; -input dftopt12 ; - -wire N23 ; -wire N24 ; -wire N25 ; -wire n13 ; -wire n18 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n15 ; -wire n16 ; -wire n17 ; -wire dftopt10_gOb12 ; -wire n34 ; -wire n35 ; -wire dftopt8_gOb9 ; -wire n37 ; -wire dftopt2_gOb8 ; -wire n39 ; -wire [7:1] DATA_V ; -wire [2:0] ser_count ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT DATA_V_reg_7_ ( .D ( n25 ) , .SI ( n35 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[7] ) , .QN ( dftopt10_gOb12 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_6_ ( .D ( n26 ) , .SI ( dftopt10_gOb12 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[6] ) , - .QN ( n34 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_5_ ( .D ( n27 ) , .SI ( dftopt3 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[5] ) , .QN ( n35 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_4_ ( .D ( n28 ) , .SI ( n34 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[4] ) , .QN ( dftopt8_gOb9 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_3_ ( .D ( n29 ) , .SI ( dftopt8_gOb9 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[3] ) , - .QN ( n37 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_2_ ( .D ( n30 ) , .SI ( n37 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[2] ) , .QN ( dftopt2_gOb8 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_1_ ( .D ( n31 ) , .SI ( dftopt2_gOb8 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[1] ) , - .QN ( n39 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT DATA_V_reg_0_ ( .D ( n24 ) , .SI ( n39 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_out ) , .QN ( dftopt0 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT ser_count_reg_0_ ( .D ( N23 ) , .SI ( n13 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_count[0] ) , .QN ( dftopt11 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT ser_count_reg_1_ ( .D ( N24 ) , .SI ( dftopt13 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_count[1] ) , - .QN ( n13 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT ser_count_reg_2_ ( .D ( N25 ) , .SI ( dftopt12 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_count[2] ) , - .QN ( dftopt5 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND3X1_RVT U18 ( .A1 ( ser_count[1] ) , .A2 ( ser_count[0] ) , - .A3 ( ser_count[2] ) , .Y ( ser_done ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U19 ( .A1 ( DATA[0] ) , .A2 ( n16 ) , .A3 ( DATA_V[1] ) , - .A4 ( n15 ) , .A5 ( ser_out ) , .A6 ( n18 ) , .Y ( n24 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO22X1_RVT U20 ( .A1 ( DATA_V[7] ) , .A2 ( n18 ) , .A3 ( DATA[7] ) , - .A4 ( n16 ) , .Y ( n25 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U21 ( .A1 ( DATA[6] ) , .A2 ( n16 ) , .A3 ( DATA_V[7] ) , - .A4 ( n15 ) , .A5 ( DATA_V[6] ) , .A6 ( n18 ) , .Y ( n26 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U22 ( .A1 ( DATA[5] ) , .A2 ( n16 ) , .A3 ( DATA_V[6] ) , - .A4 ( n15 ) , .A5 ( DATA_V[5] ) , .A6 ( n18 ) , .Y ( n27 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U23 ( .A1 ( DATA[4] ) , .A2 ( n16 ) , .A3 ( DATA_V[5] ) , - .A4 ( n15 ) , .A5 ( DATA_V[4] ) , .A6 ( n18 ) , .Y ( n28 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U24 ( .A1 ( DATA[3] ) , .A2 ( n16 ) , .A3 ( DATA_V[4] ) , - .A4 ( n15 ) , .A5 ( DATA_V[3] ) , .A6 ( n18 ) , .Y ( n29 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U25 ( .A1 ( DATA[2] ) , .A2 ( n16 ) , .A3 ( DATA_V[3] ) , - .A4 ( n15 ) , .A5 ( DATA_V[2] ) , .A6 ( n18 ) , .Y ( n30 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO222X1_RVT U26 ( .A1 ( DATA[1] ) , .A2 ( n16 ) , .A3 ( DATA_V[2] ) , - .A4 ( n15 ) , .A5 ( n18 ) , .A6 ( DATA_V[1] ) , .Y ( n31 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U27 ( .A1 ( n19 ) , .A2 ( n20 ) , .Y ( n18 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND2X0_RVT U28 ( .A1 ( Enable ) , .A2 ( n19 ) , .Y ( n20 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -NAND2X0_RVT U29 ( .A1 ( Data_Valid ) , .A2 ( n17 ) , .Y ( n19 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U30 ( .A1 ( ser_count[2] ) , .A2 ( n21 ) , .A3 ( n22 ) , - .Y ( N25 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND4X1_RVT U31 ( .A1 ( Enable ) , .A2 ( ser_count[1] ) , - .A3 ( ser_count[0] ) , .A4 ( dftopt5 ) , .Y ( n22 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AO21X1_RVT U32 ( .A1 ( Enable ) , .A2 ( n13 ) , .A3 ( N23 ) , .Y ( n21 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U33 ( .A1 ( Enable ) , .A2 ( n23 ) , .Y ( N24 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -AND2X1_RVT U34 ( .A1 ( Enable ) , .A2 ( dftopt11 ) , .Y ( N23 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U14 ( .A ( n20 ) , .Y ( n15 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U15 ( .A ( n19 ) , .Y ( n16 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U16 ( .A ( Busy ) , .Y ( n17 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -XNOR2X1_RVT U17 ( .A1 ( n13 ) , .A2 ( ser_count[0] ) , .Y ( n23 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module uart_tx_fsm_test_1 ( CLK , RST , Data_Valid , ser_done , - parity_enable , Ser_enable , mux_sel , busy , test_si , test_so , - test_se , VDD , VSS , dftopt0 , dftopt1 , dftopt2 , dftopt3 , dftopt11 , - dftopt4 ) ; -input CLK ; -input RST ; -input Data_Valid ; -input ser_done ; -input parity_enable ; -output Ser_enable ; -output [1:0] mux_sel ; -output busy ; -input test_si ; -output test_so ; -input test_se ; -input VDD ; -input VSS ; -input dftopt0 ; -output dftopt1 ; -output dftopt2 ; -input dftopt3 ; -input dftopt11 ; -output dftopt4 ; - -wire dftopt2_gOb7 ; -wire current_state_1_ ; -wire current_state_0_ ; -wire busy_c ; -wire n5 ; -wire n8 ; -wire n10 ; -wire n11 ; -wire n12 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n6 ; -wire n9 ; -wire dftopt1_gOb4 ; -wire [2:0] next_state ; -supply1 VDD ; -supply0 VSS ; - -SDFFARX1_RVT current_state_reg_0_ ( .D ( next_state[0] ) , - .SI ( dftopt1_gOb4 ) , .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , - .Q ( current_state_0_ ) , .QN ( n8 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT current_state_reg_1_ ( .D ( next_state[1] ) , .SI ( n8 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( current_state_1_ ) , - .QN ( dftopt4 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT current_state_reg_2_ ( .D ( next_state[2] ) , .SI ( dftopt11 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( dftopt2_gOb7 ) , - .QN ( n5 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SDFFARX1_RVT busy_reg ( .D ( busy_c ) , .SI ( dftopt2_gOb7 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( busy ) , - .QN ( dftopt1_gOb4 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -NOR3X0_RVT U9 ( .A1 ( dftopt4 ) , .A2 ( dftopt2_gOb7 ) , .A3 ( n10 ) , - .Y ( next_state[2] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OA21X1_RVT U10 ( .A1 ( parity_enable ) , .A2 ( n6 ) , - .A3 ( current_state_0_ ) , .Y ( n10 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OA21X1_RVT U11 ( .A1 ( n11 ) , .A2 ( n12 ) , .A3 ( n5 ) , - .Y ( next_state[1] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U12 ( .A1 ( n13 ) , .A2 ( n5 ) , .Y ( next_state[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U13 ( .A1 ( current_state_0_ ) , .A2 ( n6 ) , .A3 ( n14 ) , - .A4 ( dftopt4 ) , .Y ( n13 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -OR2X1_RVT U14 ( .A1 ( Data_Valid ) , .A2 ( current_state_0_ ) , .Y ( n14 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U15 ( .A1 ( n8 ) , .A2 ( n5 ) , .A3 ( n15 ) , .Y ( mux_sel[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO22X1_RVT U16 ( .A1 ( n9 ) , .A2 ( n5 ) , .A3 ( dftopt2_gOb7 ) , - .A4 ( n15 ) , .Y ( mux_sel[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U17 ( .A1 ( current_state_0_ ) , .A2 ( n5 ) , .A3 ( n15 ) , - .Y ( busy_c ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND3X1_RVT U18 ( .A1 ( n5 ) , .A2 ( n6 ) , .A3 ( n11 ) , .Y ( Ser_enable ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U19 ( .A1 ( n9 ) , .A2 ( current_state_0_ ) , .Y ( n11 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -AO21X1_RVT U20 ( .A1 ( current_state_0_ ) , .A2 ( dftopt4 ) , .A3 ( n15 ) , - .Y ( n12 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -AND2X1_RVT U21 ( .A1 ( current_state_1_ ) , .A2 ( n8 ) , .Y ( n15 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U7 ( .A ( n12 ) , .Y ( n9 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -INVX1_RVT U8 ( .A ( ser_done ) , .Y ( n6 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module UART_TX_DATA_WIDTH8_test_1 ( CLK , RST , P_DATA , Data_Valid , - parity_enable , parity_type , TX_OUT , busy , test_si , test_se , VDD , - VSS , dftopt4 , dftopt8 , dftopt9 , dftopt12 , dftopt14 , p0 , p1 , - dftopt13 , dftopt16 , dftopt17 , dftopt20 , dftopt18 , p2 , p3 ) ; -input CLK ; -input RST ; -input [7:0] P_DATA ; -input Data_Valid ; -input parity_enable ; -input parity_type ; -output TX_OUT ; -output busy ; -input test_si ; -input test_se ; -input VDD ; -input VSS ; -output dftopt4 ; -input dftopt8 ; -input dftopt9 ; -input dftopt12 ; -output dftopt14 ; -input p0 ; -input p1 ; -input dftopt13 ; -output dftopt16 ; -input dftopt17 ; -input dftopt20 ; -output dftopt18 ; -input p2 ; -input p3 ; - -wire dftopt0 ; -wire seriz_done ; -wire seriz_en ; -wire ser_data ; -wire parity ; -wire n3 ; -wire [1:0] mux_sel ; -supply1 VDD ; -supply0 VSS ; -wire dftopt3 ; -wire dftopt5 ; -wire dftopt6 ; -wire SYNOPSYS_UNCONNECTED_1 ; -wire SYNOPSYS_UNCONNECTED_2 ; -wire SYNOPSYS_UNCONNECTED_3 ; -wire SYNOPSYS_UNCONNECTED_4 ; -wire SYNOPSYS_UNCONNECTED_5 ; -wire SYNOPSYS_UNCONNECTED_6 ; -wire SYNOPSYS_UNCONNECTED_7 ; -wire SYNOPSYS_UNCONNECTED_8 ; -wire SYNOPSYS_UNCONNECTED_9 ; -wire SYNOPSYS_UNCONNECTED_10 ; -wire SYNOPSYS_UNCONNECTED_11 ; -wire SYNOPSYS_UNCONNECTED_12 ; -wire SYNOPSYS_UNCONNECTED_13 ; -wire SYNOPSYS_UNCONNECTED_14 ; -wire SYNOPSYS_UNCONNECTED_15 ; -wire SYNOPSYS_UNCONNECTED_16 ; -wire SYNOPSYS_UNCONNECTED_17 ; -wire SYNOPSYS_UNCONNECTED_18 ; -wire SYNOPSYS_UNCONNECTED_19 ; -wire SYNOPSYS_UNCONNECTED_20 ; -wire SYNOPSYS_UNCONNECTED_21 ; -wire SYNOPSYS_UNCONNECTED_22 ; -wire SYNOPSYS_UNCONNECTED_23 ; -wire SYNOPSYS_UNCONNECTED_24 ; -wire SYNOPSYS_UNCONNECTED_25 ; -wire SYNOPSYS_UNCONNECTED_26 ; -wire SYNOPSYS_UNCONNECTED_27 ; -wire SYNOPSYS_UNCONNECTED_28 ; -wire SYNOPSYS_UNCONNECTED_29 ; - -uart_tx_fsm_test_1 U0_fsm ( .CLK ( CLK ) , .RST ( RST ) , - .Data_Valid ( Data_Valid ) , .ser_done ( seriz_done ) , - .parity_enable ( parity_enable ) , .Ser_enable ( seriz_en ) , - .mux_sel ( mux_sel ) , .busy ( busy ) , - .test_si ( SYNOPSYS_UNCONNECTED_1 ) , - .test_so ( SYNOPSYS_UNCONNECTED_2 ) , .test_se ( test_se ) , - .VDD ( VDD ) , .VSS ( VSS ) , .dftopt0 ( SYNOPSYS_UNCONNECTED_3 ) , - .dftopt1 ( SYNOPSYS_UNCONNECTED_4 ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_5 ) , - .dftopt3 ( SYNOPSYS_UNCONNECTED_6 ) , .dftopt11 ( dftopt3 ) , - .dftopt4 ( dftopt6 ) ) ; -Serializer_WIDTH8_test_1 U0_Serializer ( .CLK ( CLK ) , .RST ( RST ) , - .DATA ( P_DATA ) , .Enable ( seriz_en ) , .Busy ( busy ) , - .Data_Valid ( Data_Valid ) , .ser_out ( ser_data ) , - .ser_done ( seriz_done ) , .test_si ( SYNOPSYS_UNCONNECTED_7 ) , - .test_so ( SYNOPSYS_UNCONNECTED_8 ) , .test_se ( test_se ) , - .VDD ( VDD ) , .VSS ( VSS ) , .dftopt0 ( dftopt0 ) , - .dftopt1 ( SYNOPSYS_UNCONNECTED_9 ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_10 ) , .dftopt3 ( dftopt5 ) , - .dftopt4 ( SYNOPSYS_UNCONNECTED_11 ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_12 ) , .dftopt5 ( dftopt18 ) , - .dftopt6 ( SYNOPSYS_UNCONNECTED_13 ) , - .dftopt7 ( SYNOPSYS_UNCONNECTED_14 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_15 ) , - .dftopt10 ( SYNOPSYS_UNCONNECTED_16 ) , .dftopt13 ( dftopt13 ) , - .dftopt11 ( dftopt3 ) , .dftopt12 ( TX_OUT ) ) ; -mux_test_1 U0_mux ( .CLK ( CLK ) , .RST ( RST ) , - .IN_0 ( SYNOPSYS_UNCONNECTED_17 ) , .IN_1 ( ser_data ) , - .IN_2 ( parity ) , .IN_3 ( SYNOPSYS_UNCONNECTED_18 ) , .SEL ( mux_sel ) , - .OUT ( TX_OUT ) , .test_si ( SYNOPSYS_UNCONNECTED_19 ) , - .test_se ( test_se ) , .VDD ( VDD ) , .VSS ( VSS ) , - .dftopt5 ( SYNOPSYS_UNCONNECTED_20 ) , .p0 ( SYNOPSYS_UNCONNECTED_21 ) , - .p1 ( SYNOPSYS_UNCONNECTED_22 ) , .dftopt0 ( n3 ) , .p2 ( p2 ) , - .p3 ( p3 ) ) ; -parity_calc_WIDTH8_test_1 U0_parity_calc ( .CLK ( CLK ) , .RST ( RST ) , - .parity_enable ( parity_enable ) , .parity_type ( parity_type ) , - .Busy ( busy ) , .DATA ( P_DATA ) , .Data_Valid ( Data_Valid ) , - .parity ( parity ) , .test_si ( SYNOPSYS_UNCONNECTED_23 ) , - .test_so ( n3 ) , .test_se ( test_se ) , .VDD ( VDD ) , .VSS ( VSS ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_24 ) , .dftopt0 ( dftopt4 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_25 ) , .dftopt1 ( dftopt5 ) , - .dftopt4 ( SYNOPSYS_UNCONNECTED_26 ) , - .dftopt3 ( SYNOPSYS_UNCONNECTED_27 ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_28 ) , - .dftopt12 ( SYNOPSYS_UNCONNECTED_29 ) , .dftopt5 ( dftopt6 ) , - .dftopt6 ( dftopt16 ) , .dftopt17 ( dftopt17 ) , .dftopt20 ( dftopt20 ) , - .dftopt7 ( dftopt0 ) ) ; -endmodule - - -module mux2X1_1 ( IN_0 , IN_1 , SEL , OUT , VDD , VSS ) ; -input IN_0 ; -input IN_1 ; -input SEL ; -output OUT ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -MUX21X1_RVT U1 ( .A1 ( IN_0 ) , .A2 ( IN_1 ) , .S0 ( SEL ) , .Y ( OUT ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module mux2X1_2 ( IN_0 , IN_1 , SEL , OUT , VDD , VSS ) ; -input IN_0 ; -input IN_1 ; -input SEL ; -output OUT ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; -wire cts0 ; - -MUX21X2_RVT U1 ( .A1 ( cts0 ) , .A2 ( IN_1 ) , .S0 ( SEL ) , .Y ( OUT ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NBUFFX2_RVT IN_0_btd306 ( .A ( IN_0 ) , .Y ( cts0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module mux2X1_0 ( IN_0 , IN_1 , SEL , OUT , VDD , VSS ) ; -input IN_0 ; -input IN_1 ; -input SEL ; -output OUT ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; -wire cts0 ; - -MUX21X2_RVT U1 ( .A1 ( cts0 ) , .A2 ( IN_1 ) , .S0 ( SEL ) , .Y ( OUT ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -NBUFFX2_RVT IN_0_btd307 ( .A ( IN_0 ) , .Y ( cts0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module UART ( RST , TX_CLK , RX_CLK , RX_IN_S , RX_OUT_P , RX_OUT_V , - TX_IN_P , TX_IN_V , TX_OUT_S , TX_OUT_V , Prescale , parity_enable , - parity_type , parity_error , framing_error , SI , SE , SO , scan_clk , - scan_rst , test_mode , VDD , VSS ) ; -input RST ; -input TX_CLK ; -input RX_CLK ; -input RX_IN_S ; -output [7:0] RX_OUT_P ; -output RX_OUT_V ; -input [7:0] TX_IN_P ; -input TX_IN_V ; -output TX_OUT_S ; -output TX_OUT_V ; -input [5:0] Prescale ; -input parity_enable ; -input parity_type ; -output parity_error ; -output framing_error ; -input SI ; -input SE ; -output SO ; -input scan_clk ; -input scan_rst ; -input test_mode ; -input VDD ; -input VSS ; - -wire dftopt3 ; -wire UART_RX_SCAN_CLK ; -wire UART_TX_SCAN_CLK ; -wire SCAN_RST ; -wire dftopt2 ; -supply1 VDD ; -supply0 VSS ; -wire dftopt15 ; -wire HFSNET_0 ; -wire HFSNET_1 ; -wire optlc_net_426 ; -wire optlc_net_427 ; -wire dftopt14 ; -wire dftopt19 ; -wire SYNOPSYS_UNCONNECTED_1 ; -wire SYNOPSYS_UNCONNECTED_2 ; -wire SYNOPSYS_UNCONNECTED_3 ; -wire SYNOPSYS_UNCONNECTED_4 ; -wire SYNOPSYS_UNCONNECTED_5 ; -wire SYNOPSYS_UNCONNECTED_6 ; -wire SYNOPSYS_UNCONNECTED_7 ; -wire SYNOPSYS_UNCONNECTED_8 ; -wire SYNOPSYS_UNCONNECTED_9 ; -wire SYNOPSYS_UNCONNECTED_10 ; -wire SYNOPSYS_UNCONNECTED_11 ; -wire SYNOPSYS_UNCONNECTED_12 ; - -NBUFFX8_RVT HFSBUF_156_0 ( .A ( SE ) , .Y ( HFSNET_0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux2X1_0 U0_mux2X1 ( .IN_0 ( RX_CLK ) , .IN_1 ( scan_clk ) , - .SEL ( test_mode ) , .OUT ( UART_RX_SCAN_CLK ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux2X1_2 U1_mux2X1 ( .IN_0 ( TX_CLK ) , .IN_1 ( scan_clk ) , - .SEL ( test_mode ) , .OUT ( UART_TX_SCAN_CLK ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux2X1_1 U2_mux2X1 ( .IN_0 ( RST ) , .IN_1 ( scan_rst ) , .SEL ( test_mode ) , - .OUT ( SCAN_RST ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -UART_TX_DATA_WIDTH8_test_1 U0_UART_TX ( .CLK ( UART_TX_SCAN_CLK ) , - .RST ( HFSNET_1 ) , .P_DATA ( TX_IN_P ) , .Data_Valid ( TX_IN_V ) , - .parity_enable ( parity_enable ) , .parity_type ( parity_type ) , - .TX_OUT ( TX_OUT_S ) , .busy ( TX_OUT_V ) , - .test_si ( SYNOPSYS_UNCONNECTED_1 ) , .test_se ( HFSNET_0 ) , - .VDD ( VDD ) , .VSS ( VSS ) , .dftopt4 ( dftopt3 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_2 ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_3 ) , - .dftopt12 ( SYNOPSYS_UNCONNECTED_4 ) , - .dftopt14 ( SYNOPSYS_UNCONNECTED_5 ) , .p0 ( SYNOPSYS_UNCONNECTED_6 ) , - .p1 ( SYNOPSYS_UNCONNECTED_7 ) , .dftopt13 ( dftopt2 ) , - .dftopt16 ( dftopt15 ) , .dftopt17 ( dftopt14 ) , .dftopt20 ( dftopt19 ) , - .dftopt18 ( SO ) , .p2 ( optlc_net_426 ) , .p3 ( optlc_net_427 ) ) ; -UART_RX_test_1 U0_UART_RX ( .CLK ( UART_RX_SCAN_CLK ) , .RST ( HFSNET_1 ) , - .RX_IN ( RX_IN_S ) , .parity_enable ( parity_enable ) , - .parity_type ( parity_type ) , .Prescale ( Prescale ) , - .P_DATA ( RX_OUT_P ) , .data_valid ( RX_OUT_V ) , - .parity_error ( parity_error ) , .framing_error ( framing_error ) , - .test_si ( SI ) , .test_so ( SYNOPSYS_UNCONNECTED_8 ) , .test_se ( SE ) , - .VDD ( VDD ) , .VSS ( VSS ) , .dftopt4 ( dftopt3 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_9 ) , .HFSNET_0 ( HFSNET_0 ) , - .HFSNET_2 ( SCAN_RST ) , .dftopt9 ( SYNOPSYS_UNCONNECTED_10 ) , - .dftopt10 ( SYNOPSYS_UNCONNECTED_11 ) , - .dftopt14 ( SYNOPSYS_UNCONNECTED_12 ) , .dftopt7 ( dftopt2 ) , - .dftopt16 ( dftopt15 ) , .dftopt15 ( dftopt14 ) , .dftopt20 ( dftopt19 ) ) ; -NBUFFX8_RVT HFSBUF_223_2 ( .A ( SCAN_RST ) , .Y ( HFSNET_1 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -TIEH_RVT optlc_1045 ( .Y ( optlc_net_426 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -TIEL_RVT optlc_1046 ( .Y ( optlc_net_427 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x30000y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x34560y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x39120y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x43680y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x48240y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x52800y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x64960y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x69520y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x74080y30000 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x110560y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x115120y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x119680y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x124240y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x128800y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x133360y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x137920y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x206320y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x210880y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x215440y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x247360y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x251920y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x256480y30000 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x30000y46720 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x34560y46720 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x39120y46720 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x86240y46720 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x171360y46720 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x175920y46720 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x180480y46720 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x438880y46720 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x30000y63440 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x49760y80160 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x367440y80160 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x43680y96880 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x48240y96880 ( .VDD ( VDD ) , .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x233680y96880 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x320320y96880 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x455600y113600 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x168320y130320 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x443440y130320 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x454080y130320 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x30000y147040 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x311200y147040 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x203280y163760 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x207840y163760 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x337040y163760 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x341600y163760 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x51280y180480 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x122720y180480 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x191120y180480 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x449520y180480 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x454080y180480 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x30000y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x156160y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x160720y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x165280y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x169840y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x174400y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x178960y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x183520y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x244320y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x248880y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x253440y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x258000y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x262560y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x335520y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x340080y197200 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x92320y213920 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x96880y213920 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x101440y213920 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x335520y213920 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x340080y213920 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x373520y213920 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x183520y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x241280y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x245840y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x422160y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x426720y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x431280y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x435840y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x440400y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x444960y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x449520y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x454080y247360 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x98400y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x102960y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x115120y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x119680y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x124240y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x245840y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x454080y264080 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x52800y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x140960y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x145520y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x150080y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x154640y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x159200y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x186560y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x428240y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x432800y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x452560y280800 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x57360y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x61920y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x244320y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x248880y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x253440y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x258000y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x302080y297520 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x194160y314240 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x64960y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x69520y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x80160y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x84720y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x89280y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x144000y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x166800y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x241280y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x245840y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x250400y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x254960y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x259520y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x455600y330960 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x148560y347680 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x153120y347680 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x317280y347680 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x162240y364400 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x280800y364400 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x137920y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x142480y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x189600y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x194160y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x198720y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x203280y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x207840y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x253440y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x384160y414560 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x30000y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x34560y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x39120y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x69520y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x127280y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL2_RVT \xofiller!SHFILL2_RVT!x131840y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x221520y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x226080y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x230640y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL3_RVT \xofiller!SHFILL3_RVT!x396320y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -SHFILL1_RVT \xofiller!SHFILL1_RVT!x400880y431280 ( .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - diff --git a/pnr/output/UART.tlef b/pnr/output/UART.tlef deleted file mode 100644 index 976857d..0000000 --- a/pnr/output/UART.tlef +++ /dev/null @@ -1,745 +0,0 @@ -VERSION 5.8 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.001 ; - -LAYER NWELL - TYPE MASTERSLICE ; -END NWELL - -LAYER PO - TYPE MASTERSLICE ; -END PO - -LAYER CO - TYPE CUT ; -END CO - -LAYER M1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.152 ; - WIDTH 0.05 ; - PROPERTY LEF58_WIDTH "WIDTH 0.05 WRONGDIRECTION ;" ; -END M1 - -LAYER VIA1 - TYPE CUT ; -END VIA1 - -LAYER M2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.152 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M2 - -LAYER VIA2 - TYPE CUT ; -END VIA2 - -LAYER M3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.304 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M3 - -LAYER VIA3 - TYPE CUT ; -END VIA3 - -LAYER M4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.304 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M4 - -LAYER VIA4 - TYPE CUT ; -END VIA4 - -LAYER M5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.608 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M5 - -LAYER VIA5 - TYPE CUT ; -END VIA5 - -LAYER M6 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.608 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M6 - -LAYER VIA6 - TYPE CUT ; -END VIA6 - -LAYER M7 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 1.216 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M7 - -LAYER VIA7 - TYPE CUT ; -END VIA7 - -LAYER M8 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 1.216 ; - WIDTH 0.056 ; - PROPERTY LEF58_WIDTH "WIDTH 0.056 WRONGDIRECTION ;" ; -END M8 - -LAYER VIA8 - TYPE CUT ; -END VIA8 - -LAYER M9 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 2.432 ; - WIDTH 0.16 ; - PROPERTY LEF58_WIDTH "WIDTH 0.16 WRONGDIRECTION ;" ; -END M9 - -LAYER VIARDL - TYPE CUT ; -END VIARDL - -LAYER MRDL - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 4.864 ; - WIDTH 2 ; - PROPERTY LEF58_WIDTH "WIDTH 2 WRONGDIRECTION ;" ; -END MRDL - -LAYER DNW - TYPE MASTERSLICE ; -END DNW - -LAYER DIFF - TYPE MASTERSLICE ; -END DIFF - -LAYER PIMP - TYPE MASTERSLICE ; -END PIMP - -LAYER NIMP - TYPE MASTERSLICE ; -END NIMP - -LAYER DIFF_18 - TYPE MASTERSLICE ; -END DIFF_18 - -LAYER PAD - TYPE MASTERSLICE ; -END PAD - -LAYER ESD_25 - TYPE MASTERSLICE ; -END ESD_25 - -LAYER SBLK - TYPE MASTERSLICE ; -END SBLK - -LAYER HVTIMP - TYPE MASTERSLICE ; -END HVTIMP - -LAYER LVTIMP - TYPE MASTERSLICE ; -END LVTIMP - -LAYER M1PIN - TYPE MASTERSLICE ; -END M1PIN - -LAYER M2PIN - TYPE MASTERSLICE ; -END M2PIN - -LAYER M3PIN - TYPE MASTERSLICE ; -END M3PIN - -LAYER M4PIN - TYPE MASTERSLICE ; -END M4PIN - -LAYER M5PIN - TYPE MASTERSLICE ; -END M5PIN - -LAYER M6PIN - TYPE MASTERSLICE ; -END M6PIN - -LAYER M7PIN - TYPE MASTERSLICE ; -END M7PIN - -LAYER M8PIN - TYPE MASTERSLICE ; -END M8PIN - -LAYER M9PIN - TYPE MASTERSLICE ; -END M9PIN - -LAYER MRDL9PIN - TYPE MASTERSLICE ; -END MRDL9PIN - -LAYER HOTNWL - TYPE MASTERSLICE ; -END HOTNWL - -LAYER DIOD - TYPE MASTERSLICE ; -END DIOD - -LAYER BJTDMY - TYPE MASTERSLICE ; -END BJTDMY - -LAYER RNW - TYPE MASTERSLICE ; -END RNW - -LAYER RMARK - TYPE MASTERSLICE ; -END RMARK - -LAYER prBoundary - TYPE MASTERSLICE ; -END prBoundary - -LAYER LOGO - TYPE MASTERSLICE ; -END LOGO - -LAYER IP - TYPE MASTERSLICE ; -END IP - -LAYER RM1 - TYPE MASTERSLICE ; -END RM1 - -LAYER RM2 - TYPE MASTERSLICE ; -END RM2 - -LAYER RM3 - TYPE MASTERSLICE ; -END RM3 - -LAYER RM4 - TYPE MASTERSLICE ; -END RM4 - -LAYER RM5 - TYPE MASTERSLICE ; -END RM5 - -LAYER RM6 - TYPE MASTERSLICE ; -END RM6 - -LAYER RM7 - TYPE MASTERSLICE ; -END RM7 - -LAYER RM8 - TYPE MASTERSLICE ; -END RM8 - -LAYER RM9 - TYPE MASTERSLICE ; -END RM9 - -LAYER DM1EXCL - TYPE MASTERSLICE ; -END DM1EXCL - -LAYER DM2EXCL - TYPE MASTERSLICE ; -END DM2EXCL - -LAYER DM3EXCL - TYPE MASTERSLICE ; -END DM3EXCL - -LAYER DM4EXCL - TYPE MASTERSLICE ; -END DM4EXCL - -LAYER DM5EXCL - TYPE MASTERSLICE ; -END DM5EXCL - -LAYER DM6EXCL - TYPE MASTERSLICE ; -END DM6EXCL - -LAYER DM7EXCL - TYPE MASTERSLICE ; -END DM7EXCL - -LAYER DM8EXCL - TYPE MASTERSLICE ; -END DM8EXCL - -LAYER DM9EXCL - TYPE MASTERSLICE ; -END DM9EXCL - -LAYER DIFF_25 - TYPE MASTERSLICE ; -END DIFF_25 - -LAYER DIFF_FM - TYPE MASTERSLICE ; -END DIFF_FM - -LAYER PO_FM - TYPE MASTERSLICE ; -END PO_FM - -VIA VIA12SQ_C - LAYER M1 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA1 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M2 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA12SQ_C - -VIA VIA12BAR_C - LAYER M1 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA1 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M2 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA12BAR_C - -VIA VIA12LG_C - LAYER M1 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA1 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M2 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA12LG_C - -VIA VIA12SQ - LAYER M1 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA1 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M2 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA12SQ - -VIA VIA12BAR - LAYER M1 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA1 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M2 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA12BAR - -VIA VIA12LG - LAYER M1 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA1 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M2 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA12LG - -VIA VIA23SQ_C - LAYER M2 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA2 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M3 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA23SQ_C - -VIA VIA23BAR_C - LAYER M2 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA2 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M3 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA23BAR_C - -VIA VIA23LG_C - LAYER M2 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA2 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M3 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA23LG_C - -VIA VIA23SQ - LAYER M2 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA2 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M3 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA23SQ - -VIA VIA23BAR - LAYER M2 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA2 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M3 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA23BAR - -VIA VIA23LG - LAYER M2 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA2 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M3 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA23LG - -VIA VIA34SQ_C - LAYER M3 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA3 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M4 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA34SQ_C - -VIA VIA34BAR_C - LAYER M3 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA3 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M4 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA34BAR_C - -VIA VIA34LG_C - LAYER M3 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA3 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M4 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA34LG_C - -VIA VIA34SQ - LAYER M3 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA3 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M4 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA34SQ - -VIA VIA34BAR - LAYER M3 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA3 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M4 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA34BAR - -VIA VIA34LG - LAYER M3 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA3 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M4 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA34LG - -VIA VIA45SQ_C - LAYER M4 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA4 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M5 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA45SQ_C - -VIA VIA45BAR_C - LAYER M4 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA4 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M5 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA45BAR_C - -VIA VIA45LG_C - LAYER M4 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA4 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M5 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA45LG_C - -VIA VIA45SQ - LAYER M4 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA4 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M5 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA45SQ - -VIA VIA45BAR - LAYER M4 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA4 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M5 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA45BAR - -VIA VIA45LG - LAYER M4 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA4 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M5 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA45LG - -VIA VIA56SQ_C - LAYER M5 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA5 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M6 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA56SQ_C - -VIA VIA56BAR_C - LAYER M5 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA5 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M6 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA56BAR_C - -VIA VIA56LG_C - LAYER M5 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA5 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M6 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA56LG_C - -VIA VIA56SQ - LAYER M5 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA5 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M6 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA56SQ - -VIA VIA56BAR - LAYER M5 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA5 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M6 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA56BAR - -VIA VIA56LG - LAYER M5 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA5 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M6 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA56LG - -VIA VIA67SQ_C - LAYER M6 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA6 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M7 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA67SQ_C - -VIA VIA67BAR_C - LAYER M6 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA6 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M7 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA67BAR_C - -VIA VIA67LG_C - LAYER M6 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA6 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M7 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA67LG_C - -VIA VIA67SQ - LAYER M6 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA6 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M7 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA67SQ - -VIA VIA67BAR - LAYER M6 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA6 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M7 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA67BAR - -VIA VIA67LG - LAYER M6 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA6 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M7 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA67LG - -VIA VIA78SQ_C - LAYER M7 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA7 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M8 ; - RECT -0.03 -0.055 0.03 0.055 ; -END VIA78SQ_C - -VIA VIA78BAR_C - LAYER M7 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA7 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M8 ; - RECT -0.03 -0.08 0.03 0.08 ; -END VIA78BAR_C - -VIA VIA78LG_C - LAYER M7 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA7 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M8 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA78LG_C - -VIA VIA78SQ - LAYER M7 ; - RECT -0.055 -0.03 0.055 0.03 ; - LAYER VIA7 ; - RECT -0.025 -0.025 0.025 0.025 ; - LAYER M8 ; - RECT -0.055 -0.03 0.055 0.03 ; -END VIA78SQ - -VIA VIA78BAR - LAYER M7 ; - RECT -0.055 -0.055 0.055 0.055 ; - LAYER VIA7 ; - RECT -0.025 -0.05 0.025 0.05 ; - LAYER M8 ; - RECT -0.055 -0.055 0.055 0.055 ; -END VIA78BAR - -VIA VIA78LG - LAYER M7 ; - RECT -0.08 -0.055 0.08 0.055 ; - LAYER VIA7 ; - RECT -0.05 -0.05 0.05 0.05 ; - LAYER M8 ; - RECT -0.08 -0.055 0.08 0.055 ; -END VIA78LG - -VIA VIA89_C - LAYER M8 ; - RECT -0.095 -0.08 0.095 0.08 ; - LAYER VIA8 ; - RECT -0.065 -0.065 0.065 0.065 ; - LAYER M9 ; - RECT -0.08 -0.095 0.08 0.095 ; -END VIA89_C - -VIA VIA89 - LAYER M8 ; - RECT -0.095 -0.08 0.095 0.08 ; - LAYER VIA8 ; - RECT -0.065 -0.065 0.065 0.065 ; - LAYER M9 ; - RECT -0.095 -0.08 0.095 0.08 ; -END VIA89 - -VIA VIA9RDL - LAYER M9 ; - RECT -1.5 -1.5 1.5 1.5 ; - LAYER VIARDL ; - RECT -1 -1 1 1 ; - LAYER MRDL ; - RECT -1.5 -1.5 1.5 1.5 ; -END VIA9RDL - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.152 BY 1.672 ; -END unit - -END LIBRARY diff --git a/pnr/output/UART.v b/pnr/output/UART.v deleted file mode 100644 index 398dd15..0000000 --- a/pnr/output/UART.v +++ /dev/null @@ -1,1510 +0,0 @@ -// IC Compiler II Verilog Writer -// Generated on 04/24/2024 at 19:58:07 -// Library Name: UART.dlib -// Block Name: UART -// User Label: -// Write Command: write_verilog -exclude { all_physical_cells analog_pg corner_cells cover_cells diode_cells empty_modules end_cap_cells physical_only_cells filler_cells pg_objects well_tap_cells leaf_module_declarations } output/UART.v -module stp_chk_test_1 ( CLK , RST , sampled_bit , Enable , stp_err , test_si , - test_se , dftopt0 , dftopt1 ) ; -input CLK ; -input RST ; -input sampled_bit ; -input Enable ; -output stp_err ; -input test_si ; -input test_se ; -input dftopt0 ; -input dftopt1 ; - -wire n2 ; -wire n4 ; -wire n1 ; - -SDFFARX1_RVT stp_err_reg ( .D ( n4 ) , .SI ( dftopt1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( stp_err ) , .QN ( n2 ) ) ; -OAI22X1_RVT U2 ( .A1 ( sampled_bit ) , .A2 ( n1 ) , .A3 ( Enable ) , - .A4 ( n2 ) , .Y ( n4 ) ) ; -INVX1_RVT U3 ( .A ( Enable ) , .Y ( n1 ) ) ; -endmodule - - -module par_chk_DATA_WIDTH8_test_1 ( CLK , RST , parity_type , sampled_bit , - Enable , P_DATA , par_err , test_si , test_so , test_se , dftopt0 ) ; -input CLK ; -input RST ; -input parity_type ; -input sampled_bit ; -input Enable ; -input [7:0] P_DATA ; -output par_err ; -input test_si ; -output test_so ; -input test_se ; -input dftopt0 ; - -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n7 ; -wire n9 ; -wire n1 ; - -SDFFARX1_RVT par_err_reg ( .D ( n9 ) , .SI ( dftopt0 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( par_err ) , .QN ( test_so ) ) ; -AO22X1_RVT U2 ( .A1 ( par_err ) , .A2 ( n1 ) , .A3 ( Enable ) , .A4 ( n2 ) , - .Y ( n9 ) ) ; -XNOR3X1_RVT U3 ( .A1 ( n3 ) , .A2 ( n4 ) , .A3 ( n5 ) , .Y ( n2 ) ) ; -XNOR3X1_RVT U5 ( .A1 ( P_DATA[1] ) , .A2 ( P_DATA[0] ) , .A3 ( n6 ) , - .Y ( n4 ) ) ; -XNOR3X1_RVT U7 ( .A1 ( P_DATA[4] ) , .A2 ( P_DATA[5] ) , .A3 ( n7 ) , - .Y ( n3 ) ) ; -XNOR2X1_RVT U4 ( .A1 ( P_DATA[7] ) , .A2 ( P_DATA[6] ) , .Y ( n7 ) ) ; -XNOR2X1_RVT U6 ( .A1 ( P_DATA[3] ) , .A2 ( P_DATA[2] ) , .Y ( n6 ) ) ; -XNOR2X1_RVT U8 ( .A1 ( sampled_bit ) , .A2 ( parity_type ) , .Y ( n5 ) ) ; -INVX1_RVT U9 ( .A ( Enable ) , .Y ( n1 ) ) ; -endmodule - - -module strt_chk_test_1 ( CLK , RST , sampled_bit , Enable , strt_glitch , - test_si , test_so , test_se , dftopt0 ) ; -input CLK ; -input RST ; -input sampled_bit ; -input Enable ; -output strt_glitch ; -input test_si ; -output test_so ; -input test_se ; -input dftopt0 ; - -wire n3 ; -wire n1 ; - -SDFFARX1_RVT strt_glitch_reg ( .D ( n3 ) , .SI ( dftopt0 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( strt_glitch ) , .QN ( test_so ) ) ; -AO22X1_RVT U2 ( .A1 ( sampled_bit ) , .A2 ( Enable ) , .A3 ( strt_glitch ) , - .A4 ( n1 ) , .Y ( n3 ) ) ; -INVX1_RVT U3 ( .A ( Enable ) , .Y ( n1 ) ) ; -endmodule - - -module deserializer_DATA_WIDTH8_test_1 ( CLK , RST , sampled_bit , Enable , - edge_count , Prescale , P_DATA , test_si , test_so , test_se , dftopt1 , - dftopt0 ) ; -input CLK ; -input RST ; -input sampled_bit ; -input Enable ; -input [5:0] edge_count ; -input [5:0] Prescale ; -output [7:0] P_DATA ; -input test_si ; -output test_so ; -input test_se ; -input dftopt1 ; -output dftopt0 ; - -wire N2 ; -wire N3 ; -wire N4 ; -wire N5 ; -wire N6 ; -wire N7 ; -wire n1 ; -wire n18 ; -wire n20 ; -wire n22 ; -wire n24 ; -wire n26 ; -wire n28 ; -wire n30 ; -wire n32 ; -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n7 ; -wire n8 ; -wire n9 ; -wire n10 ; -wire n11 ; -wire n12 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n16 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n43 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire n50 ; -wire n51 ; - -SDFFARX1_RVT P_DATA_reg_7_ ( .D ( n32 ) , .SI ( n46 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[7] ) , .QN ( test_so ) ) ; -SDFFARX1_RVT P_DATA_reg_6_ ( .D ( n30 ) , .SI ( n48 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[6] ) , .QN ( n46 ) ) ; -SDFFARX1_RVT P_DATA_reg_5_ ( .D ( n28 ) , .SI ( test_si ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[5] ) , .QN ( n47 ) ) ; -SDFFARX1_RVT P_DATA_reg_4_ ( .D ( n26 ) , .SI ( n49 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[4] ) , .QN ( n48 ) ) ; -SDFFARX1_RVT P_DATA_reg_3_ ( .D ( n24 ) , .SI ( n50 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[3] ) , .QN ( n49 ) ) ; -SDFFARX1_RVT P_DATA_reg_2_ ( .D ( n22 ) , .SI ( n47 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[2] ) , .QN ( n50 ) ) ; -SDFFARX1_RVT P_DATA_reg_1_ ( .D ( n20 ) , .SI ( dftopt1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[1] ) , .QN ( n51 ) ) ; -SDFFARX1_RVT P_DATA_reg_0_ ( .D ( n18 ) , .SI ( n51 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( P_DATA[0] ) , .QN ( dftopt0 ) ) ; -AO22X1_RVT U3 ( .A1 ( n1 ) , .A2 ( P_DATA[0] ) , .A3 ( n43 ) , - .A4 ( P_DATA[1] ) , .Y ( n18 ) ) ; -AO22X1_RVT U4 ( .A1 ( n1 ) , .A2 ( P_DATA[1] ) , .A3 ( n43 ) , - .A4 ( P_DATA[2] ) , .Y ( n20 ) ) ; -AO22X1_RVT U6 ( .A1 ( n1 ) , .A2 ( P_DATA[2] ) , .A3 ( n43 ) , - .A4 ( P_DATA[3] ) , .Y ( n22 ) ) ; -AO22X1_RVT U8 ( .A1 ( n1 ) , .A2 ( P_DATA[3] ) , .A3 ( n43 ) , - .A4 ( P_DATA[4] ) , .Y ( n24 ) ) ; -AO22X1_RVT U10 ( .A1 ( n1 ) , .A2 ( P_DATA[4] ) , .A3 ( n43 ) , - .A4 ( P_DATA[5] ) , .Y ( n26 ) ) ; -AO22X1_RVT U12 ( .A1 ( n1 ) , .A2 ( P_DATA[5] ) , .A3 ( n43 ) , - .A4 ( P_DATA[6] ) , .Y ( n28 ) ) ; -AO22X1_RVT U14 ( .A1 ( n1 ) , .A2 ( P_DATA[6] ) , .A3 ( n43 ) , - .A4 ( P_DATA[7] ) , .Y ( n30 ) ) ; -AO22X1_RVT U16 ( .A1 ( n1 ) , .A2 ( P_DATA[7] ) , .A3 ( sampled_bit ) , - .A4 ( n43 ) , .Y ( n32 ) ) ; -INVX1_RVT U5 ( .A ( n1 ) , .Y ( n43 ) ) ; -INVX1_RVT U7 ( .A ( N2 ) , .Y ( n34 ) ) ; -NAND2X0_RVT U9 ( .A1 ( N7 ) , .A2 ( Enable ) , .Y ( n1 ) ) ; -INVX1_RVT U11 ( .A ( edge_count[1] ) , .Y ( n35 ) ) ; -INVX1_RVT U13 ( .A ( n2 ) , .Y ( n6 ) ) ; -INVX1_RVT U15 ( .A ( n3 ) , .Y ( n7 ) ) ; -INVX1_RVT U17 ( .A ( Prescale[4] ) , .Y ( n8 ) ) ; -OR2X1_RVT U18 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .Y ( n2 ) ) ; -AO21X1_RVT U19 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .A3 ( n6 ) , - .Y ( N2 ) ) ; -OR2X1_RVT U28 ( .A1 ( n2 ) , .A2 ( Prescale[2] ) , .Y ( n3 ) ) ; -AO21X1_RVT U29 ( .A1 ( Prescale[2] ) , .A2 ( n2 ) , .A3 ( n7 ) , .Y ( N3 ) ) ; -NOR2X0_RVT U30 ( .A1 ( n3 ) , .A2 ( Prescale[3] ) , .Y ( n4 ) ) ; -AO21X1_RVT U31 ( .A1 ( Prescale[3] ) , .A2 ( n3 ) , .A3 ( n4 ) , .Y ( N4 ) ) ; -XNOR2X1_RVT U32 ( .A1 ( n8 ) , .A2 ( n4 ) , .Y ( N5 ) ) ; -NAND2X0_RVT U33 ( .A1 ( n4 ) , .A2 ( n8 ) , .Y ( n5 ) ) ; -XNOR2X1_RVT U34 ( .A1 ( n5 ) , .A2 ( Prescale[5] ) , .Y ( N6 ) ) ; -XNOR2X1_RVT U35 ( .A1 ( N4 ) , .A2 ( edge_count[3] ) , .Y ( n11 ) ) ; -XNOR2X1_RVT U36 ( .A1 ( N3 ) , .A2 ( edge_count[2] ) , .Y ( n10 ) ) ; -XNOR2X1_RVT U37 ( .A1 ( N5 ) , .A2 ( edge_count[4] ) , .Y ( n9 ) ) ; -NAND3X0_RVT U38 ( .A1 ( n11 ) , .A2 ( n10 ) , .A3 ( n9 ) , .Y ( n33 ) ) ; -XOR2X1_RVT U39 ( .A1 ( N6 ) , .A2 ( edge_count[5] ) , .Y ( n16 ) ) ; -NOR2X0_RVT U40 ( .A1 ( Prescale[0] ) , .A2 ( edge_count[0] ) , .Y ( n12 ) ) ; -OA22X1_RVT U41 ( .A1 ( N2 ) , .A2 ( n12 ) , .A3 ( n12 ) , .A4 ( n35 ) , - .Y ( n15 ) ) ; -AND2X1_RVT U42 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[0] ) , .Y ( n13 ) ) ; -OA22X1_RVT U43 ( .A1 ( n13 ) , .A2 ( n34 ) , .A3 ( edge_count[1] ) , - .A4 ( n13 ) , .Y ( n14 ) ) ; -NOR4X0_RVT U44 ( .A1 ( n33 ) , .A2 ( n16 ) , .A3 ( n15 ) , .A4 ( n14 ) , - .Y ( N7 ) ) ; -endmodule - - -module data_sampling_test_1 ( CLK , RST , S_DATA , Prescale , edge_count , - Enable , sampled_bit , test_si , test_so , test_se , dftopt0 , dftopt1 , - dftopt2 , dftopt3 , dftopt4 , dftopt5 , dftopt9 , dftopt6 , dftopt12 ) ; -input CLK ; -input RST ; -input S_DATA ; -input [5:0] Prescale ; -input [5:0] edge_count ; -input Enable ; -output sampled_bit ; -input test_si ; -output test_so ; -input test_se ; -input dftopt0 ; -output dftopt1 ; -input dftopt2 ; -input dftopt3 ; -output dftopt4 ; -input dftopt5 ; -input dftopt9 ; -output dftopt6 ; -input dftopt12 ; - -wire N58 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n1 ; -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n11 ; -wire n12 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n16 ; -wire n17 ; -wire n18 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n32 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n36 ; -wire n37 ; -wire n38 ; -wire n39 ; -wire n40 ; -wire n41 ; -wire n42 ; -wire n43 ; -wire n44 ; -wire n45 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire n50 ; -wire n51 ; -wire n52 ; -wire n53 ; -wire n54 ; -wire [4:0] half_edges ; -wire [4:1] half_edges_p1 ; -wire [4:1] half_edges_n1 ; -wire [4:2] add_21_carry ; - -SDFFARX1_RVT Samples_reg_2_ ( .D ( n25 ) , .SI ( dftopt12 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n33 ) , - .QN ( dftopt4 ) ) ; -SDFFARX1_RVT Samples_reg_1_ ( .D ( n24 ) , .SI ( dftopt9 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n2 ) , .QN ( dftopt1 ) ) ; -SDFFARX1_RVT Samples_reg_0_ ( .D ( n23 ) , .SI ( dftopt5 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n1 ) , .QN ( dftopt6 ) ) ; -SDFFARX1_RVT sampled_bit_reg ( .D ( N58 ) , .SI ( dftopt2 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( sampled_bit ) , - .QN ( test_so ) ) ; -HADDX1_RVT add_21_U1_1_1 ( .A0 ( half_edges[1] ) , .B0 ( half_edges[0] ) , - .C1 ( add_21_carry[2] ) , .SO ( half_edges_p1[1] ) ) ; -HADDX1_RVT add_21_U1_1_2 ( .A0 ( half_edges[2] ) , .B0 ( add_21_carry[2] ) , - .C1 ( add_21_carry[3] ) , .SO ( half_edges_p1[2] ) ) ; -HADDX1_RVT add_21_U1_1_3 ( .A0 ( half_edges[3] ) , .B0 ( add_21_carry[3] ) , - .C1 ( add_21_carry[4] ) , .SO ( half_edges_p1[3] ) ) ; -INVX1_RVT U4 ( .A ( half_edges[3] ) , .Y ( n16 ) ) ; -INVX1_RVT U5 ( .A ( n12 ) , .Y ( n15 ) ) ; -INVX1_RVT U6 ( .A ( n3 ) , .Y ( n6 ) ) ; -INVX1_RVT U10 ( .A ( Prescale[4] ) , .Y ( n11 ) ) ; -INVX0_RVT U11 ( .A ( Prescale[1] ) , .Y ( half_edges[0] ) ) ; -OR2X1_RVT U12 ( .A1 ( Prescale[2] ) , .A2 ( Prescale[1] ) , .Y ( n3 ) ) ; -AO21X1_RVT U13 ( .A1 ( Prescale[2] ) , .A2 ( Prescale[1] ) , .A3 ( n6 ) , - .Y ( half_edges[1] ) ) ; -NOR2X0_RVT U14 ( .A1 ( n3 ) , .A2 ( Prescale[3] ) , .Y ( n4 ) ) ; -AO21X1_RVT U15 ( .A1 ( Prescale[3] ) , .A2 ( n3 ) , .A3 ( n4 ) , - .Y ( half_edges[2] ) ) ; -XNOR2X1_RVT U16 ( .A1 ( n11 ) , .A2 ( n4 ) , .Y ( half_edges[3] ) ) ; -NAND2X0_RVT U17 ( .A1 ( n4 ) , .A2 ( n11 ) , .Y ( n5 ) ) ; -XNOR2X1_RVT U18 ( .A1 ( n5 ) , .A2 ( Prescale[5] ) , .Y ( half_edges[4] ) ) ; -XOR2X1_RVT U19 ( .A1 ( add_21_carry[4] ) , .A2 ( half_edges[4] ) , - .Y ( half_edges_p1[4] ) ) ; -OR2X1_RVT U20 ( .A1 ( half_edges[1] ) , .A2 ( half_edges[0] ) , .Y ( n12 ) ) ; -AO21X1_RVT U21 ( .A1 ( half_edges[1] ) , .A2 ( half_edges[0] ) , .A3 ( n15 ) , - .Y ( half_edges_n1[1] ) ) ; -NOR2X0_RVT U22 ( .A1 ( n12 ) , .A2 ( half_edges[2] ) , .Y ( n13 ) ) ; -AO21X1_RVT U23 ( .A1 ( half_edges[2] ) , .A2 ( n12 ) , .A3 ( n13 ) , - .Y ( half_edges_n1[2] ) ) ; -XNOR2X1_RVT U24 ( .A1 ( n16 ) , .A2 ( n13 ) , .Y ( half_edges_n1[3] ) ) ; -NAND2X0_RVT U25 ( .A1 ( n13 ) , .A2 ( n16 ) , .Y ( n14 ) ) ; -XNOR2X1_RVT U26 ( .A1 ( n14 ) , .A2 ( half_edges[4] ) , - .Y ( half_edges_n1[4] ) ) ; -MUX21X1_RVT U27 ( .A1 ( n17 ) , .A2 ( n18 ) , .S0 ( n19 ) , .Y ( n25 ) ) ; -NOR4X0_RVT U28 ( .A1 ( n20 ) , .A2 ( n21 ) , .A3 ( n22 ) , .A4 ( n26 ) , - .Y ( n19 ) ) ; -XOR2X1_RVT U29 ( .A1 ( half_edges_p1[2] ) , .A2 ( edge_count[2] ) , - .Y ( n26 ) ) ; -NAND2X0_RVT U30 ( .A1 ( n27 ) , .A2 ( n28 ) , .Y ( n21 ) ) ; -NAND4X0_RVT U31 ( .A1 ( n29 ) , .A2 ( n30 ) , .A3 ( n31 ) , .A4 ( n32 ) , - .Y ( n20 ) ) ; -XNOR2X1_RVT U32 ( .A1 ( edge_count[3] ) , .A2 ( half_edges_p1[3] ) , - .Y ( n32 ) ) ; -XNOR2X1_RVT U33 ( .A1 ( edge_count[4] ) , .A2 ( half_edges_p1[4] ) , - .Y ( n31 ) ) ; -XNOR2X1_RVT U34 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[1] ) , .Y ( n30 ) ) ; -XNOR2X1_RVT U35 ( .A1 ( edge_count[1] ) , .A2 ( half_edges_p1[1] ) , - .Y ( n29 ) ) ; -AND2X1_RVT U36 ( .A1 ( Enable ) , .A2 ( n33 ) , .Y ( n17 ) ) ; -MUX21X1_RVT U37 ( .A1 ( n34 ) , .A2 ( n18 ) , .S0 ( n22 ) , .Y ( n24 ) ) ; -AND4X1_RVT U38 ( .A1 ( n35 ) , .A2 ( n36 ) , .A3 ( n37 ) , .A4 ( n38 ) , - .Y ( n22 ) ) ; -AND4X1_RVT U39 ( .A1 ( n39 ) , .A2 ( n40 ) , .A3 ( n27 ) , .A4 ( n28 ) , - .Y ( n38 ) ) ; -XOR2X1_RVT U40 ( .A1 ( n41 ) , .A2 ( half_edges[0] ) , .Y ( n40 ) ) ; -XOR2X1_RVT U41 ( .A1 ( n42 ) , .A2 ( half_edges[1] ) , .Y ( n39 ) ) ; -XOR2X1_RVT U42 ( .A1 ( n43 ) , .A2 ( half_edges[3] ) , .Y ( n37 ) ) ; -XOR2X1_RVT U43 ( .A1 ( n44 ) , .A2 ( half_edges[4] ) , .Y ( n36 ) ) ; -XOR2X1_RVT U44 ( .A1 ( n45 ) , .A2 ( half_edges[2] ) , .Y ( n35 ) ) ; -AND2X1_RVT U45 ( .A1 ( Enable ) , .A2 ( n2 ) , .Y ( n34 ) ) ; -MUX21X1_RVT U46 ( .A1 ( n18 ) , .A2 ( n46 ) , .S0 ( n27 ) , .Y ( n23 ) ) ; -NAND4X0_RVT U47 ( .A1 ( n47 ) , .A2 ( n48 ) , .A3 ( n49 ) , .A4 ( n50 ) , - .Y ( n27 ) ) ; -AND3X1_RVT U48 ( .A1 ( n51 ) , .A2 ( n28 ) , .A3 ( n52 ) , .Y ( n50 ) ) ; -XOR2X1_RVT U49 ( .A1 ( n45 ) , .A2 ( half_edges_n1[2] ) , .Y ( n52 ) ) ; -INVX0_RVT U50 ( .A ( edge_count[2] ) , .Y ( n45 ) ) ; -INVX0_RVT U51 ( .A ( edge_count[5] ) , .Y ( n28 ) ) ; -XOR2X1_RVT U52 ( .A1 ( n43 ) , .A2 ( half_edges_n1[3] ) , .Y ( n51 ) ) ; -INVX0_RVT U53 ( .A ( edge_count[3] ) , .Y ( n43 ) ) ; -XOR2X1_RVT U54 ( .A1 ( n41 ) , .A2 ( Prescale[1] ) , .Y ( n49 ) ) ; -INVX0_RVT U55 ( .A ( edge_count[0] ) , .Y ( n41 ) ) ; -XOR2X1_RVT U56 ( .A1 ( n42 ) , .A2 ( half_edges_n1[1] ) , .Y ( n48 ) ) ; -INVX0_RVT U57 ( .A ( edge_count[1] ) , .Y ( n42 ) ) ; -XOR2X1_RVT U58 ( .A1 ( n44 ) , .A2 ( half_edges_n1[4] ) , .Y ( n47 ) ) ; -INVX0_RVT U59 ( .A ( edge_count[4] ) , .Y ( n44 ) ) ; -AND2X1_RVT U60 ( .A1 ( Enable ) , .A2 ( n1 ) , .Y ( n46 ) ) ; -AND2X1_RVT U61 ( .A1 ( S_DATA ) , .A2 ( Enable ) , .Y ( n18 ) ) ; -AND2X1_RVT U62 ( .A1 ( Enable ) , .A2 ( n53 ) , .Y ( N58 ) ) ; -AO22X1_RVT U63 ( .A1 ( n2 ) , .A2 ( n1 ) , .A3 ( n54 ) , .A4 ( n33 ) , - .Y ( n53 ) ) ; -NAND2X0_RVT U64 ( .A1 ( dftopt6 ) , .A2 ( dftopt1 ) , .Y ( n54 ) ) ; -endmodule - - -module edge_bit_counter_test_1 ( CLK , RST , Enable , Prescale , bit_count , - edge_count , test_si , test_so , test_se , dftopt0 , dftopt4 , dftopt1 , - dftopt2 , dftopt3 , dftopt5 , dftopt6 , HFSNET_0 , HFSNET_1 , dftopt14 , - dftopt7 , dftopt8 , dftopt9 , dftopt16 , dftopt10 , dftopt11 , dftopt12 , - dftopt13 ) ; -input CLK ; -input RST ; -input Enable ; -input [5:0] Prescale ; -output [3:0] bit_count ; -output [5:0] edge_count ; -input test_si ; -output test_so ; -input test_se ; -input dftopt0 ; -input dftopt4 ; -output dftopt1 ; -input dftopt2 ; -output dftopt3 ; -input dftopt5 ; -output dftopt6 ; -input HFSNET_0 ; -input HFSNET_1 ; -input dftopt14 ; -output dftopt7 ; -output dftopt8 ; -output dftopt9 ; -input dftopt16 ; -output dftopt10 ; -input dftopt11 ; -output dftopt12 ; -output dftopt13 ; - -wire N8 ; -wire N9 ; -wire N10 ; -wire N11 ; -wire N12 ; -wire N19 ; -wire N20 ; -wire N21 ; -wire N22 ; -wire N23 ; -wire N24 ; -wire N26 ; -wire N27 ; -wire N28 ; -wire N29 ; -wire N30 ; -wire N31 ; -wire dftopt7_gOb13 ; -wire dftopt8_gOb14 ; -wire n18 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n32 ; -wire n1 ; -wire n13 ; -wire n17 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n36 ; -wire n37 ; -wire n38 ; -wire n39 ; -wire n40 ; -wire n41 ; -wire n42 ; -wire n43 ; -wire n44 ; -wire n45 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire dftopt3_gOb5 ; -wire n53 ; -wire [5:2] add_31_carry ; - -SDFFARX1_RVT edge_count_reg_0_ ( .D ( N19 ) , .SI ( dftopt8_gOb14 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[0] ) , .QN ( n1 ) ) ; -SDFFARX1_RVT edge_count_reg_5_ ( .D ( N24 ) , .SI ( dftopt0 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[5] ) , .QN ( dftopt9 ) ) ; -SDFFARX1_RVT edge_count_reg_1_ ( .D ( N20 ) , .SI ( dftopt7_gOb13 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[1] ) , .QN ( dftopt13 ) ) ; -SDFFARX1_RVT edge_count_reg_2_ ( .D ( N21 ) , .SI ( n53 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , .Q ( edge_count[2] ) , - .QN ( dftopt12 ) ) ; -SDFFARX1_RVT edge_count_reg_3_ ( .D ( N22 ) , .SI ( dftopt3_gOb5 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[3] ) , .QN ( n53 ) ) ; -SDFFARX1_RVT edge_count_reg_4_ ( .D ( N23 ) , .SI ( dftopt11 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( edge_count[4] ) , .QN ( dftopt3_gOb5 ) ) ; -SDFFARX1_RVT bit_count_reg_0_ ( .D ( n32 ) , .SI ( dftopt5 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , - .Q ( bit_count[0] ) , .QN ( dftopt8_gOb14 ) ) ; -SDFFARX1_RVT bit_count_reg_1_ ( .D ( n31 ) , .SI ( n1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( HFSNET_1 ) , .Q ( bit_count[1] ) , - .QN ( dftopt7_gOb13 ) ) ; -SDFFARX1_RVT bit_count_reg_2_ ( .D ( n30 ) , .SI ( dftopt4 ) , - .SE ( HFSNET_0 ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( bit_count[2] ) , - .QN ( dftopt1 ) ) ; -SDFFARX1_RVT bit_count_reg_3_ ( .D ( n29 ) , .SI ( dftopt16 ) , - .SE ( HFSNET_0 ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( bit_count[3] ) , - .QN ( dftopt10 ) ) ; -NAND2X0_RVT U16 ( .A1 ( n18 ) , .A2 ( n19 ) , .Y ( n29 ) ) ; -NAND4X0_RVT U17 ( .A1 ( Enable ) , .A2 ( n20 ) , .A3 ( n21 ) , - .A4 ( bit_count[2] ) , .Y ( n19 ) ) ; -AND2X1_RVT U18 ( .A1 ( N31 ) , .A2 ( dftopt10 ) , .Y ( n21 ) ) ; -AO21X1_RVT U19 ( .A1 ( n22 ) , .A2 ( n23 ) , .A3 ( dftopt10 ) , .Y ( n18 ) ) ; -AO21X1_RVT U20 ( .A1 ( n20 ) , .A2 ( bit_count[2] ) , .A3 ( n49 ) , - .Y ( n23 ) ) ; -AND2X1_RVT U21 ( .A1 ( bit_count[1] ) , .A2 ( bit_count[0] ) , .Y ( n20 ) ) ; -AO22X1_RVT U22 ( .A1 ( bit_count[2] ) , .A2 ( n24 ) , .A3 ( n25 ) , - .A4 ( n26 ) , .Y ( n30 ) ) ; -NOR2X0_RVT U23 ( .A1 ( dftopt7_gOb13 ) , .A2 ( bit_count[2] ) , .Y ( n25 ) ) ; -AO21X1_RVT U24 ( .A1 ( Enable ) , .A2 ( dftopt7_gOb13 ) , .A3 ( n27 ) , - .Y ( n24 ) ) ; -AO22X1_RVT U25 ( .A1 ( bit_count[1] ) , .A2 ( n27 ) , .A3 ( n26 ) , - .A4 ( dftopt7_gOb13 ) , .Y ( n31 ) ) ; -AND3X1_RVT U26 ( .A1 ( bit_count[0] ) , .A2 ( n22 ) , .A3 ( Enable ) , - .Y ( n26 ) ) ; -AO21X1_RVT U27 ( .A1 ( Enable ) , .A2 ( dftopt8_gOb14 ) , .A3 ( n48 ) , - .Y ( n27 ) ) ; -AO22X1_RVT U28 ( .A1 ( n48 ) , .A2 ( bit_count[0] ) , .A3 ( n28 ) , - .A4 ( Enable ) , .Y ( n32 ) ) ; -AND2X1_RVT U29 ( .A1 ( n22 ) , .A2 ( dftopt8_gOb14 ) , .Y ( n28 ) ) ; -AND2X1_RVT U30 ( .A1 ( N12 ) , .A2 ( n48 ) , .Y ( N24 ) ) ; -AND2X1_RVT U31 ( .A1 ( N11 ) , .A2 ( n48 ) , .Y ( N23 ) ) ; -AND2X1_RVT U32 ( .A1 ( N10 ) , .A2 ( n48 ) , .Y ( N22 ) ) ; -AND2X1_RVT U33 ( .A1 ( N9 ) , .A2 ( n48 ) , .Y ( N21 ) ) ; -AND2X1_RVT U34 ( .A1 ( N8 ) , .A2 ( n48 ) , .Y ( N20 ) ) ; -AND2X1_RVT U35 ( .A1 ( n1 ) , .A2 ( n48 ) , .Y ( N19 ) ) ; -OR2X1_RVT U36 ( .A1 ( n49 ) , .A2 ( N31 ) , .Y ( n22 ) ) ; -HADDX1_RVT add_31_U1_1_1 ( .A0 ( edge_count[1] ) , .B0 ( edge_count[0] ) , - .C1 ( add_31_carry[2] ) , .SO ( N8 ) ) ; -HADDX1_RVT add_31_U1_1_2 ( .A0 ( edge_count[2] ) , .B0 ( add_31_carry[2] ) , - .C1 ( add_31_carry[3] ) , .SO ( N9 ) ) ; -HADDX1_RVT add_31_U1_1_3 ( .A0 ( edge_count[3] ) , .B0 ( add_31_carry[3] ) , - .C1 ( add_31_carry[4] ) , .SO ( N10 ) ) ; -HADDX1_RVT add_31_U1_1_4 ( .A0 ( edge_count[4] ) , .B0 ( add_31_carry[4] ) , - .C1 ( add_31_carry[5] ) , .SO ( N11 ) ) ; -INVX1_RVT U6 ( .A ( n22 ) , .Y ( n48 ) ) ; -INVX1_RVT U14 ( .A ( Enable ) , .Y ( n49 ) ) ; -INVX1_RVT U15 ( .A ( N26 ) , .Y ( n47 ) ) ; -INVX1_RVT U37 ( .A ( n13 ) , .Y ( n35 ) ) ; -INVX1_RVT U38 ( .A ( n17 ) , .Y ( n36 ) ) ; -INVX1_RVT U39 ( .A ( Prescale[4] ) , .Y ( n37 ) ) ; -OR2X1_RVT U40 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .Y ( n13 ) ) ; -AO21X1_RVT U41 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .A3 ( n35 ) , - .Y ( N26 ) ) ; -OR2X1_RVT U42 ( .A1 ( n13 ) , .A2 ( Prescale[2] ) , .Y ( n17 ) ) ; -AO21X1_RVT U43 ( .A1 ( Prescale[2] ) , .A2 ( n13 ) , .A3 ( n36 ) , - .Y ( N27 ) ) ; -NOR2X0_RVT U44 ( .A1 ( n17 ) , .A2 ( Prescale[3] ) , .Y ( n33 ) ) ; -AO21X1_RVT U45 ( .A1 ( Prescale[3] ) , .A2 ( n17 ) , .A3 ( n33 ) , - .Y ( N28 ) ) ; -XNOR2X1_RVT U46 ( .A1 ( n37 ) , .A2 ( n33 ) , .Y ( N29 ) ) ; -NAND2X0_RVT U47 ( .A1 ( n33 ) , .A2 ( n37 ) , .Y ( n34 ) ) ; -XNOR2X1_RVT U48 ( .A1 ( n34 ) , .A2 ( Prescale[5] ) , .Y ( N30 ) ) ; -XOR2X1_RVT U49 ( .A1 ( add_31_carry[5] ) , .A2 ( edge_count[5] ) , - .Y ( N12 ) ) ; -XNOR2X1_RVT U50 ( .A1 ( N28 ) , .A2 ( edge_count[3] ) , .Y ( n40 ) ) ; -XNOR2X1_RVT U51 ( .A1 ( N27 ) , .A2 ( edge_count[2] ) , .Y ( n39 ) ) ; -XNOR2X1_RVT U52 ( .A1 ( N29 ) , .A2 ( edge_count[4] ) , .Y ( n38 ) ) ; -NAND3X0_RVT U53 ( .A1 ( n40 ) , .A2 ( n39 ) , .A3 ( n38 ) , .Y ( n46 ) ) ; -XOR2X1_RVT U54 ( .A1 ( N30 ) , .A2 ( edge_count[5] ) , .Y ( n45 ) ) ; -NOR2X0_RVT U55 ( .A1 ( Prescale[0] ) , .A2 ( edge_count[0] ) , .Y ( n41 ) ) ; -OA22X1_RVT U56 ( .A1 ( N26 ) , .A2 ( n41 ) , .A3 ( n41 ) , .A4 ( dftopt13 ) , - .Y ( n44 ) ) ; -AND2X1_RVT U57 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[0] ) , .Y ( n42 ) ) ; -OA22X1_RVT U58 ( .A1 ( n42 ) , .A2 ( n47 ) , .A3 ( edge_count[1] ) , - .A4 ( n42 ) , .Y ( n43 ) ) ; -NOR4X0_RVT U59 ( .A1 ( n46 ) , .A2 ( n45 ) , .A3 ( n44 ) , .A4 ( n43 ) , - .Y ( N31 ) ) ; -endmodule - - -module uart_rx_fsm_DATA_WIDTH8_test_1 ( CLK , RST , S_DATA , Prescale , - parity_enable , bit_count , edge_count , par_err , stp_err , strt_glitch , - strt_chk_en , edge_bit_en , deser_en , par_chk_en , stp_chk_en , - dat_samp_en , data_valid , test_si , test_so , test_se , dftopt1 , - dftopt0 , dftopt7 , dftopt8 , dftopt2 ) ; -input CLK ; -input RST ; -input S_DATA ; -input [5:0] Prescale ; -input parity_enable ; -input [3:0] bit_count ; -input [5:0] edge_count ; -input par_err ; -input stp_err ; -input strt_glitch ; -output strt_chk_en ; -output edge_bit_en ; -output deser_en ; -output par_chk_en ; -output stp_chk_en ; -output dat_samp_en ; -output data_valid ; -input test_si ; -output test_so ; -input test_se ; -input dftopt1 ; -output dftopt0 ; -input dftopt7 ; -input dftopt8 ; -input dftopt2 ; - -wire error_check_edge_5_ ; -wire error_check_edge_4_ ; -wire error_check_edge_3_ ; -wire error_check_edge_2_ ; -wire error_check_edge_1_ ; -wire n18 ; -wire n1 ; -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n6 ; -wire n7 ; -wire n8 ; -wire n9 ; -wire n13 ; -wire n14 ; -wire n16 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n32 ; -wire n33 ; -wire n34 ; -wire n35 ; -wire n36 ; -wire n37 ; -wire n38 ; -wire n39 ; -wire n40 ; -wire n41 ; -wire n42 ; -wire n43 ; -wire n44 ; -wire n45 ; -wire n46 ; -wire n47 ; -wire n48 ; -wire n49 ; -wire n50 ; -wire n51 ; -wire n52 ; -wire n53 ; -wire n54 ; -wire n55 ; -wire n56 ; -wire n57 ; -wire n58 ; -wire n59 ; -wire [5:0] check_edge ; -wire [2:0] next_state ; -wire [5:3] sub_40_carry ; - -SDFFARX1_RVT current_state_reg_0_ ( .D ( next_state[0] ) , .SI ( dftopt2 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n2 ) , .QN ( n18 ) ) ; -SDFFARX1_RVT current_state_reg_2_ ( .D ( next_state[2] ) , .SI ( stp_err ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n1 ) , - .QN ( test_so ) ) ; -SDFFARX1_RVT current_state_reg_1_ ( .D ( next_state[1] ) , .SI ( n2 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n28 ) , - .QN ( dftopt0 ) ) ; -INVX1_RVT U4 ( .A ( n3 ) , .Y ( n7 ) ) ; -INVX1_RVT U5 ( .A ( n4 ) , .Y ( n8 ) ) ; -INVX1_RVT U6 ( .A ( Prescale[4] ) , .Y ( n9 ) ) ; -INVX1_RVT U9 ( .A ( Prescale[1] ) , .Y ( error_check_edge_1_ ) ) ; -XNOR2X1_RVT U10 ( .A1 ( Prescale[5] ) , .A2 ( sub_40_carry[5] ) , - .Y ( error_check_edge_5_ ) ) ; -OR2X1_RVT U11 ( .A1 ( Prescale[4] ) , .A2 ( sub_40_carry[4] ) , - .Y ( sub_40_carry[5] ) ) ; -XNOR2X1_RVT U12 ( .A1 ( sub_40_carry[4] ) , .A2 ( Prescale[4] ) , - .Y ( error_check_edge_4_ ) ) ; -OR2X1_RVT U13 ( .A1 ( Prescale[3] ) , .A2 ( sub_40_carry[3] ) , - .Y ( sub_40_carry[4] ) ) ; -XNOR2X1_RVT U14 ( .A1 ( sub_40_carry[3] ) , .A2 ( Prescale[3] ) , - .Y ( error_check_edge_3_ ) ) ; -OR2X1_RVT U15 ( .A1 ( Prescale[2] ) , .A2 ( Prescale[1] ) , - .Y ( sub_40_carry[3] ) ) ; -XNOR2X1_RVT U16 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[2] ) , - .Y ( error_check_edge_2_ ) ) ; -INVX0_RVT U17 ( .A ( Prescale[0] ) , .Y ( check_edge[0] ) ) ; -OR2X1_RVT U18 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .Y ( n3 ) ) ; -AO21X1_RVT U19 ( .A1 ( Prescale[1] ) , .A2 ( Prescale[0] ) , .A3 ( n7 ) , - .Y ( check_edge[1] ) ) ; -OR2X1_RVT U20 ( .A1 ( n3 ) , .A2 ( Prescale[2] ) , .Y ( n4 ) ) ; -AO21X1_RVT U21 ( .A1 ( Prescale[2] ) , .A2 ( n3 ) , .A3 ( n8 ) , - .Y ( check_edge[2] ) ) ; -NOR2X0_RVT U22 ( .A1 ( n4 ) , .A2 ( Prescale[3] ) , .Y ( n5 ) ) ; -AO21X1_RVT U23 ( .A1 ( Prescale[3] ) , .A2 ( n4 ) , .A3 ( n5 ) , - .Y ( check_edge[3] ) ) ; -XNOR2X1_RVT U24 ( .A1 ( n9 ) , .A2 ( n5 ) , .Y ( check_edge[4] ) ) ; -NAND2X0_RVT U25 ( .A1 ( n5 ) , .A2 ( n9 ) , .Y ( n6 ) ) ; -XNOR2X1_RVT U26 ( .A1 ( n6 ) , .A2 ( Prescale[5] ) , .Y ( check_edge[5] ) ) ; -INVX0_RVT U27 ( .A ( n13 ) , .Y ( strt_chk_en ) ) ; -AND2X1_RVT U28 ( .A1 ( n14 ) , .A2 ( test_so ) , .Y ( par_chk_en ) ) ; -NAND2X0_RVT U29 ( .A1 ( n16 ) , .A2 ( n19 ) , .Y ( next_state[2] ) ) ; -NAND3X0_RVT U30 ( .A1 ( bit_count[3] ) , .A2 ( n20 ) , .A3 ( n21 ) , - .Y ( n19 ) ) ; -MUX21X1_RVT U31 ( .A1 ( n14 ) , .A2 ( n22 ) , .S0 ( n23 ) , .Y ( n21 ) ) ; -AND2X1_RVT U32 ( .A1 ( deser_en ) , .A2 ( n24 ) , .Y ( n22 ) ) ; -AO21X1_RVT U33 ( .A1 ( test_so ) , .A2 ( n25 ) , .A3 ( n14 ) , - .Y ( next_state[1] ) ) ; -AO21X1_RVT U34 ( .A1 ( n26 ) , .A2 ( n27 ) , .A3 ( n28 ) , .Y ( n25 ) ) ; -INVX0_RVT U35 ( .A ( strt_glitch ) , .Y ( n27 ) ) ; -AO221X1_RVT U36 ( .A1 ( n29 ) , .A2 ( n30 ) , .A3 ( deser_en ) , .A4 ( n31 ) , - .A5 ( n32 ) , .Y ( next_state[0] ) ) ; -NAND2X0_RVT U37 ( .A1 ( n33 ) , .A2 ( n34 ) , .Y ( n32 ) ) ; -NAND4X0_RVT U38 ( .A1 ( n42 ) , .A2 ( n45 ) , .A3 ( n37 ) , .A4 ( n38 ) , - .Y ( n34 ) ) ; -AND4X1_RVT U39 ( .A1 ( n43 ) , .A2 ( n40 ) , .A3 ( n39 ) , .A4 ( n41 ) , - .Y ( n38 ) ) ; -AND3X1_RVT U40 ( .A1 ( bit_count[3] ) , .A2 ( stp_chk_en ) , .A3 ( n35 ) , - .Y ( n41 ) ) ; -NAND2X0_RVT U41 ( .A1 ( bit_count[1] ) , .A2 ( bit_count[0] ) , .Y ( n42 ) ) ; -XNOR2X1_RVT U42 ( .A1 ( edge_count[0] ) , .A2 ( Prescale[0] ) , .Y ( n40 ) ) ; -INVX0_RVT U43 ( .A ( n16 ) , .Y ( stp_chk_en ) ) ; -NAND2X0_RVT U44 ( .A1 ( n14 ) , .A2 ( n1 ) , .Y ( n16 ) ) ; -INVX0_RVT U45 ( .A ( n44 ) , .Y ( n14 ) ) ; -XNOR2X1_RVT U46 ( .A1 ( edge_count[1] ) , .A2 ( error_check_edge_1_ ) , - .Y ( n39 ) ) ; -AND3X1_RVT U47 ( .A1 ( n46 ) , .A2 ( n36 ) , .A3 ( n47 ) , .Y ( n37 ) ) ; -XNOR2X1_RVT U48 ( .A1 ( edge_count[3] ) , .A2 ( error_check_edge_3_ ) , - .Y ( n47 ) ) ; -XNOR2X1_RVT U49 ( .A1 ( edge_count[4] ) , .A2 ( error_check_edge_4_ ) , - .Y ( n46 ) ) ; -XNOR2X1_RVT U50 ( .A1 ( edge_count[2] ) , .A2 ( error_check_edge_2_ ) , - .Y ( n45 ) ) ; -XNOR2X1_RVT U51 ( .A1 ( edge_count[5] ) , .A2 ( error_check_edge_5_ ) , - .Y ( n36 ) ) ; -MUX21X1_RVT U52 ( .A1 ( bit_count[1] ) , .A2 ( bit_count[0] ) , .S0 ( n24 ) , - .Y ( n35 ) ) ; -INVX0_RVT U53 ( .A ( parity_enable ) , .Y ( n24 ) ) ; -AO21X1_RVT U54 ( .A1 ( strt_glitch ) , .A2 ( n26 ) , .A3 ( n13 ) , - .Y ( n33 ) ) ; -OR2X1_RVT U55 ( .A1 ( n28 ) , .A2 ( n48 ) , .Y ( n13 ) ) ; -AND4X1_RVT U56 ( .A1 ( n20 ) , .A2 ( n23 ) , .A3 ( n49 ) , .A4 ( n2 ) , - .Y ( n26 ) ) ; -INVX0_RVT U57 ( .A ( bit_count[3] ) , .Y ( n49 ) ) ; -NAND3X0_RVT U58 ( .A1 ( n20 ) , .A2 ( n23 ) , .A3 ( bit_count[3] ) , - .Y ( n31 ) ) ; -INVX0_RVT U59 ( .A ( bit_count[0] ) , .Y ( n23 ) ) ; -NOR2X0_RVT U60 ( .A1 ( n50 ) , .A2 ( n51 ) , .Y ( n20 ) ) ; -NAND4X0_RVT U61 ( .A1 ( n52 ) , .A2 ( n53 ) , .A3 ( n54 ) , .A4 ( n55 ) , - .Y ( n51 ) ) ; -XNOR2X1_RVT U62 ( .A1 ( edge_count[3] ) , .A2 ( check_edge[3] ) , .Y ( n55 ) ) ; -XNOR2X1_RVT U63 ( .A1 ( edge_count[4] ) , .A2 ( check_edge[4] ) , .Y ( n54 ) ) ; -XNOR2X1_RVT U64 ( .A1 ( edge_count[0] ) , .A2 ( check_edge[0] ) , .Y ( n53 ) ) ; -XNOR2X1_RVT U65 ( .A1 ( edge_count[1] ) , .A2 ( check_edge[1] ) , .Y ( n52 ) ) ; -NAND4X0_RVT U66 ( .A1 ( n56 ) , .A2 ( n57 ) , .A3 ( n58 ) , .A4 ( n43 ) , - .Y ( n50 ) ) ; -INVX0_RVT U67 ( .A ( bit_count[2] ) , .Y ( n43 ) ) ; -INVX0_RVT U68 ( .A ( bit_count[1] ) , .Y ( n58 ) ) ; -XNOR2X1_RVT U69 ( .A1 ( edge_count[5] ) , .A2 ( check_edge[5] ) , .Y ( n57 ) ) ; -XNOR2X1_RVT U70 ( .A1 ( edge_count[2] ) , .A2 ( check_edge[2] ) , .Y ( n56 ) ) ; -INVX0_RVT U71 ( .A ( S_DATA ) , .Y ( n30 ) ) ; -INVX0_RVT U72 ( .A ( n59 ) , .Y ( n29 ) ) ; -NAND2X0_RVT U73 ( .A1 ( n48 ) , .A2 ( n44 ) , .Y ( edge_bit_en ) ) ; -NAND2X0_RVT U74 ( .A1 ( n18 ) , .A2 ( n28 ) , .Y ( n44 ) ) ; -AND3X1_RVT U75 ( .A1 ( n28 ) , .A2 ( n2 ) , .A3 ( test_so ) , - .Y ( deser_en ) ) ; -NOR3X0_RVT U76 ( .A1 ( n59 ) , .A2 ( stp_err ) , .A3 ( par_err ) , - .Y ( data_valid ) ) ; -NAND3X0_RVT U77 ( .A1 ( n28 ) , .A2 ( n2 ) , .A3 ( n1 ) , .Y ( n59 ) ) ; -NAND2X0_RVT U78 ( .A1 ( dftopt0 ) , .A2 ( n48 ) , .Y ( dat_samp_en ) ) ; -AO21X1_RVT U79 ( .A1 ( n18 ) , .A2 ( S_DATA ) , .A3 ( n1 ) , .Y ( n48 ) ) ; -endmodule - - -module UART_RX_test_1 ( CLK , RST , RX_IN , parity_enable , parity_type , - Prescale , P_DATA , data_valid , parity_error , framing_error , test_si , - test_so , test_se , dftopt4 , dftopt8 , HFSNET_0 , HFSNET_2 , dftopt9 , - dftopt10 , dftopt14 , dftopt7 , dftopt16 , dftopt15 , dftopt20 ) ; -input CLK ; -input RST ; -input RX_IN ; -input parity_enable ; -input parity_type ; -input [5:0] Prescale ; -output [7:0] P_DATA ; -output data_valid ; -output parity_error ; -output framing_error ; -input test_si ; -output test_so ; -input test_se ; -input dftopt4 ; -output dftopt8 ; -input HFSNET_0 ; -input HFSNET_2 ; -output dftopt9 ; -output dftopt10 ; -input dftopt14 ; -output dftopt7 ; -input dftopt16 ; -output dftopt15 ; -output dftopt20 ; - -wire strt_glitch ; -wire strt_chk_en ; -wire edge_bit_en ; -wire deser_en ; -wire par_chk_en ; -wire stp_chk_en ; -wire dat_samp_en ; -wire sampled_bit ; -wire HFSNET_1 ; -wire n4 ; -wire dftopt9_gOb6 ; -wire dftopt2 ; -wire n7 ; -wire n8 ; -wire [3:0] bit_count ; -wire [5:0] edge_count ; -wire dftopt0 ; -wire dftopt1 ; -wire dftopt10_gOb10 ; -wire dftopt3 ; -wire dftopt6 ; -wire dftopt17 ; -wire dftopt18 ; -wire SYNOPSYS_UNCONNECTED_1 ; -wire SYNOPSYS_UNCONNECTED_2 ; -wire SYNOPSYS_UNCONNECTED_3 ; -wire SYNOPSYS_UNCONNECTED_4 ; -wire SYNOPSYS_UNCONNECTED_5 ; -wire SYNOPSYS_UNCONNECTED_6 ; -wire SYNOPSYS_UNCONNECTED_7 ; -wire SYNOPSYS_UNCONNECTED_8 ; -wire SYNOPSYS_UNCONNECTED_9 ; -wire SYNOPSYS_UNCONNECTED_10 ; -wire SYNOPSYS_UNCONNECTED_11 ; -wire SYNOPSYS_UNCONNECTED_12 ; -wire SYNOPSYS_UNCONNECTED_13 ; -wire SYNOPSYS_UNCONNECTED_14 ; -wire SYNOPSYS_UNCONNECTED_15 ; -wire SYNOPSYS_UNCONNECTED_16 ; -wire SYNOPSYS_UNCONNECTED_17 ; -wire SYNOPSYS_UNCONNECTED_18 ; -wire SYNOPSYS_UNCONNECTED_19 ; -wire SYNOPSYS_UNCONNECTED_20 ; - -NBUFFX8_RVT HFSBUF_432_1 ( .A ( HFSNET_2 ) , .Y ( HFSNET_1 ) ) ; -uart_rx_fsm_DATA_WIDTH8_test_1 U0_uart_fsm ( .CLK ( CLK ) , - .RST ( HFSNET_1 ) , .S_DATA ( RX_IN ) , .Prescale ( Prescale ) , - .parity_enable ( parity_enable ) , .bit_count ( bit_count ) , - .edge_count ( edge_count ) , .par_err ( parity_error ) , - .stp_err ( framing_error ) , .strt_glitch ( strt_glitch ) , - .strt_chk_en ( strt_chk_en ) , .edge_bit_en ( edge_bit_en ) , - .deser_en ( deser_en ) , .par_chk_en ( par_chk_en ) , - .stp_chk_en ( stp_chk_en ) , .dat_samp_en ( dat_samp_en ) , - .data_valid ( data_valid ) , .test_si ( SYNOPSYS_UNCONNECTED_1 ) , - .test_so ( dftopt7 ) , .test_se ( test_se ) , - .dftopt1 ( SYNOPSYS_UNCONNECTED_2 ) , .dftopt0 ( dftopt3 ) , - .dftopt7 ( SYNOPSYS_UNCONNECTED_3 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_4 ) , .dftopt2 ( dftopt10_gOb10 ) ) ; -edge_bit_counter_test_1 U0_edge_bit_counter ( .CLK ( CLK ) , .RST ( RST ) , - .Enable ( edge_bit_en ) , .Prescale ( Prescale ) , - .bit_count ( bit_count ) , .edge_count ( edge_count ) , - .test_si ( SYNOPSYS_UNCONNECTED_5 ) , - .test_so ( SYNOPSYS_UNCONNECTED_6 ) , .test_se ( test_se ) , - .dftopt0 ( test_si ) , .dftopt4 ( dftopt4 ) , - .dftopt1 ( dftopt10_gOb10 ) , .dftopt2 ( SYNOPSYS_UNCONNECTED_7 ) , - .dftopt3 ( SYNOPSYS_UNCONNECTED_8 ) , .dftopt5 ( dftopt6 ) , - .dftopt6 ( SYNOPSYS_UNCONNECTED_9 ) , .HFSNET_0 ( HFSNET_0 ) , - .HFSNET_1 ( HFSNET_1 ) , .dftopt14 ( SYNOPSYS_UNCONNECTED_10 ) , - .dftopt7 ( SYNOPSYS_UNCONNECTED_11 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_12 ) , .dftopt9 ( dftopt2 ) , - .dftopt16 ( dftopt16 ) , .dftopt10 ( dftopt15 ) , .dftopt11 ( dftopt17 ) , - .dftopt12 ( dftopt18 ) , .dftopt13 ( dftopt20 ) ) ; -data_sampling_test_1 U0_data_sampling ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .S_DATA ( RX_IN ) , - .Prescale ( { Prescale[5] , Prescale[4] , Prescale[3] , Prescale[2] , - Prescale[1] , SYNOPSYS_UNCONNECTED_13 } ) , - .edge_count ( edge_count ) , .Enable ( dat_samp_en ) , - .sampled_bit ( sampled_bit ) , .test_si ( SYNOPSYS_UNCONNECTED_14 ) , - .test_so ( n8 ) , .test_se ( test_se ) , - .dftopt0 ( SYNOPSYS_UNCONNECTED_15 ) , .dftopt1 ( dftopt0 ) , - .dftopt2 ( dftopt1 ) , .dftopt3 ( SYNOPSYS_UNCONNECTED_16 ) , - .dftopt4 ( dftopt6 ) , .dftopt5 ( n4 ) , .dftopt9 ( dftopt2 ) , - .dftopt6 ( dftopt17 ) , .dftopt12 ( dftopt18 ) ) ; -deserializer_DATA_WIDTH8_test_1 U0_deserializer ( .CLK ( CLK ) , - .RST ( HFSNET_1 ) , .sampled_bit ( sampled_bit ) , .Enable ( deser_en ) , - .edge_count ( edge_count ) , .Prescale ( Prescale ) , .P_DATA ( P_DATA ) , - .test_si ( n8 ) , .test_so ( n7 ) , .test_se ( test_se ) , - .dftopt1 ( dftopt0 ) , .dftopt0 ( dftopt1 ) ) ; -strt_chk_test_1 U0_strt_chk ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .sampled_bit ( sampled_bit ) , .Enable ( strt_chk_en ) , - .strt_glitch ( strt_glitch ) , .test_si ( SYNOPSYS_UNCONNECTED_17 ) , - .test_so ( n4 ) , .test_se ( test_se ) , .dftopt0 ( dftopt3 ) ) ; -par_chk_DATA_WIDTH8_test_1 U0_par_chk ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .parity_type ( parity_type ) , .sampled_bit ( sampled_bit ) , - .Enable ( par_chk_en ) , .P_DATA ( P_DATA ) , .par_err ( parity_error ) , - .test_si ( SYNOPSYS_UNCONNECTED_18 ) , .test_so ( dftopt9_gOb6 ) , - .test_se ( test_se ) , .dftopt0 ( n7 ) ) ; -stp_chk_test_1 U0_stp_chk ( .CLK ( CLK ) , .RST ( HFSNET_1 ) , - .sampled_bit ( sampled_bit ) , .Enable ( stp_chk_en ) , - .stp_err ( framing_error ) , .test_si ( SYNOPSYS_UNCONNECTED_19 ) , - .test_se ( test_se ) , .dftopt0 ( SYNOPSYS_UNCONNECTED_20 ) , - .dftopt1 ( dftopt9_gOb6 ) ) ; -endmodule - - -module parity_calc_WIDTH8_test_1 ( CLK , RST , parity_enable , parity_type , - Busy , DATA , Data_Valid , parity , test_si , test_so , test_se , - dftopt2 , dftopt0 , dftopt8 , dftopt1 , dftopt4 , dftopt3 , dftopt9 , - dftopt12 , dftopt5 , dftopt6 , dftopt17 , dftopt20 , dftopt7 ) ; -input CLK ; -input RST ; -input parity_enable ; -input parity_type ; -input Busy ; -input [7:0] DATA ; -input Data_Valid ; -output parity ; -input test_si ; -output test_so ; -input test_se ; -input dftopt2 ; -output dftopt0 ; -input dftopt8 ; -output dftopt1 ; -input dftopt4 ; -input dftopt3 ; -input dftopt9 ; -input dftopt12 ; -input dftopt5 ; -output dftopt6 ; -input dftopt17 ; -input dftopt20 ; -input dftopt7 ; - -wire n2 ; -wire n3 ; -wire n4 ; -wire n5 ; -wire n8 ; -wire n18 ; -wire n20 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n27 ; -wire n29 ; -wire n31 ; -wire n33 ; -wire n35 ; -wire n37 ; -wire n39 ; -wire n41 ; -wire n43 ; -wire n1 ; -wire n6 ; -wire n7 ; -wire n10 ; -wire n11 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n16 ; -wire n17 ; -wire n28 ; - -SDFFARX1_RVT DATA_V_reg_7_ ( .D ( n43 ) , .SI ( dftopt20 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n11 ) , .QN ( n25 ) ) ; -SDFFARX1_RVT DATA_V_reg_6_ ( .D ( n41 ) , .SI ( n1 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( dftopt6 ) , .QN ( n24 ) ) ; -SDFFARX1_RVT DATA_V_reg_5_ ( .D ( n39 ) , .SI ( n11 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n6 ) , .QN ( n23 ) ) ; -SDFFARX1_RVT DATA_V_reg_4_ ( .D ( n37 ) , .SI ( n6 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( dftopt1 ) , .QN ( n22 ) ) ; -SDFFARX1_RVT DATA_V_reg_3_ ( .D ( n35 ) , .SI ( dftopt17 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n13 ) , .QN ( dftopt0 ) ) ; -SDFFARX1_RVT DATA_V_reg_2_ ( .D ( n33 ) , .SI ( n28 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n1 ) , .QN ( n20 ) ) ; -SDFFARX1_RVT DATA_V_reg_1_ ( .D ( n31 ) , .SI ( n7 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n14 ) , .QN ( n28 ) ) ; -SDFFARX1_RVT DATA_V_reg_0_ ( .D ( n29 ) , .SI ( dftopt5 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( n7 ) , .QN ( n18 ) ) ; -SDFFARX1_RVT parity_reg ( .D ( n27 ) , .SI ( dftopt7 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( parity ) , .QN ( test_so ) ) ; -AO22X1_RVT U2 ( .A1 ( parity ) , .A2 ( n17 ) , .A3 ( parity_enable ) , - .A4 ( n2 ) , .Y ( n27 ) ) ; -XNOR3X1_RVT U3 ( .A1 ( parity_type ) , .A2 ( n3 ) , .A3 ( n4 ) , .Y ( n2 ) ) ; -XNOR3X1_RVT U4 ( .A1 ( n24 ) , .A2 ( n25 ) , .A3 ( n5 ) , .Y ( n4 ) ) ; -AO22X1_RVT U9 ( .A1 ( n8 ) , .A2 ( n7 ) , .A3 ( DATA[0] ) , .A4 ( n15 ) , - .Y ( n29 ) ) ; -AO22X1_RVT U11 ( .A1 ( n8 ) , .A2 ( n14 ) , .A3 ( DATA[1] ) , .A4 ( n15 ) , - .Y ( n31 ) ) ; -AO22X1_RVT U13 ( .A1 ( n8 ) , .A2 ( n1 ) , .A3 ( DATA[2] ) , .A4 ( n15 ) , - .Y ( n33 ) ) ; -AO22X1_RVT U15 ( .A1 ( n8 ) , .A2 ( n13 ) , .A3 ( DATA[3] ) , .A4 ( n15 ) , - .Y ( n35 ) ) ; -AO22X1_RVT U17 ( .A1 ( n8 ) , .A2 ( dftopt1 ) , .A3 ( DATA[4] ) , - .A4 ( n15 ) , .Y ( n37 ) ) ; -AO22X1_RVT U19 ( .A1 ( n8 ) , .A2 ( n6 ) , .A3 ( DATA[5] ) , .A4 ( n15 ) , - .Y ( n39 ) ) ; -AO22X1_RVT U21 ( .A1 ( n8 ) , .A2 ( dftopt6 ) , .A3 ( DATA[6] ) , - .A4 ( n15 ) , .Y ( n41 ) ) ; -AO22X1_RVT U23 ( .A1 ( n8 ) , .A2 ( n11 ) , .A3 ( DATA[7] ) , .A4 ( n15 ) , - .Y ( n43 ) ) ; -INVX1_RVT U5 ( .A ( n8 ) , .Y ( n15 ) ) ; -XNOR3X1_RVT U6 ( .A1 ( n13 ) , .A2 ( n20 ) , .A3 ( n10 ) , .Y ( n3 ) ) ; -XNOR2X1_RVT U7 ( .A1 ( n18 ) , .A2 ( n14 ) , .Y ( n10 ) ) ; -XOR2X1_RVT U8 ( .A1 ( n22 ) , .A2 ( n23 ) , .Y ( n5 ) ) ; -NAND2X0_RVT U10 ( .A1 ( Data_Valid ) , .A2 ( n16 ) , .Y ( n8 ) ) ; -INVX1_RVT U12 ( .A ( Busy ) , .Y ( n16 ) ) ; -INVX1_RVT U14 ( .A ( parity_enable ) , .Y ( n17 ) ) ; -endmodule - - -module mux_test_1 ( CLK , RST , IN_0 , IN_1 , IN_2 , IN_3 , SEL , OUT , - test_si , test_se , dftopt5 , p0 , p1 , dftopt0 , p2 , p3 ) ; -input CLK ; -input RST ; -input IN_0 ; -input IN_1 ; -input IN_2 ; -input IN_3 ; -input [1:0] SEL ; -output OUT ; -input test_si ; -input test_se ; -input dftopt5 ; -input p0 ; -input p1 ; -input dftopt0 ; -input p2 ; -input p3 ; - -wire mux_out ; -wire n4 ; -wire n5 ; -wire n2 ; -wire n3 ; -wire SYNOPSYS_UNCONNECTED_1 ; - -SDFFARX1_RVT OUT_reg ( .D ( mux_out ) , .SI ( dftopt0 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( OUT ) , - .QN ( SYNOPSYS_UNCONNECTED_1 ) ) ; -AO22X1_RVT U6 ( .A1 ( SEL[1] ) , .A2 ( n4 ) , .A3 ( n5 ) , .A4 ( n2 ) , - .Y ( mux_out ) ) ; -AO22X1_RVT U7 ( .A1 ( SEL[0] ) , .A2 ( IN_1 ) , .A3 ( p3 ) , .A4 ( n3 ) , - .Y ( n5 ) ) ; -AO22X1_RVT U8 ( .A1 ( p2 ) , .A2 ( SEL[0] ) , .A3 ( IN_2 ) , .A4 ( n3 ) , - .Y ( n4 ) ) ; -INVX1_RVT U4 ( .A ( SEL[0] ) , .Y ( n3 ) ) ; -INVX1_RVT U5 ( .A ( SEL[1] ) , .Y ( n2 ) ) ; -endmodule - - -module Serializer_WIDTH8_test_1 ( CLK , RST , DATA , Enable , Busy , - Data_Valid , ser_out , ser_done , test_si , test_so , test_se , dftopt0 , - dftopt1 , dftopt2 , dftopt3 , dftopt4 , dftopt9 , dftopt5 , dftopt6 , - dftopt7 , dftopt8 , dftopt10 , dftopt13 , dftopt11 , dftopt12 ) ; -input CLK ; -input RST ; -input [7:0] DATA ; -input Enable ; -input Busy ; -input Data_Valid ; -output ser_out ; -output ser_done ; -input test_si ; -output test_so ; -input test_se ; -output dftopt0 ; -input dftopt1 ; -output dftopt2 ; -input dftopt3 ; -output dftopt4 ; -input dftopt9 ; -output dftopt5 ; -input dftopt6 ; -input dftopt7 ; -output dftopt8 ; -output dftopt10 ; -input dftopt13 ; -output dftopt11 ; -input dftopt12 ; - -wire N23 ; -wire N24 ; -wire N25 ; -wire n13 ; -wire n18 ; -wire n19 ; -wire n20 ; -wire n21 ; -wire n22 ; -wire n23 ; -wire n24 ; -wire n25 ; -wire n26 ; -wire n27 ; -wire n28 ; -wire n29 ; -wire n30 ; -wire n31 ; -wire n15 ; -wire n16 ; -wire n17 ; -wire dftopt10_gOb12 ; -wire n34 ; -wire n35 ; -wire dftopt8_gOb9 ; -wire n37 ; -wire dftopt2_gOb8 ; -wire n39 ; -wire [7:1] DATA_V ; -wire [2:0] ser_count ; - -SDFFARX1_RVT DATA_V_reg_7_ ( .D ( n25 ) , .SI ( n35 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[7] ) , .QN ( dftopt10_gOb12 ) ) ; -SDFFARX1_RVT DATA_V_reg_6_ ( .D ( n26 ) , .SI ( dftopt10_gOb12 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[6] ) , - .QN ( n34 ) ) ; -SDFFARX1_RVT DATA_V_reg_5_ ( .D ( n27 ) , .SI ( dftopt3 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[5] ) , .QN ( n35 ) ) ; -SDFFARX1_RVT DATA_V_reg_4_ ( .D ( n28 ) , .SI ( n34 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[4] ) , .QN ( dftopt8_gOb9 ) ) ; -SDFFARX1_RVT DATA_V_reg_3_ ( .D ( n29 ) , .SI ( dftopt8_gOb9 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[3] ) , - .QN ( n37 ) ) ; -SDFFARX1_RVT DATA_V_reg_2_ ( .D ( n30 ) , .SI ( n37 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[2] ) , .QN ( dftopt2_gOb8 ) ) ; -SDFFARX1_RVT DATA_V_reg_1_ ( .D ( n31 ) , .SI ( dftopt2_gOb8 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( DATA_V[1] ) , - .QN ( n39 ) ) ; -SDFFARX1_RVT DATA_V_reg_0_ ( .D ( n24 ) , .SI ( n39 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_out ) , .QN ( dftopt0 ) ) ; -SDFFARX1_RVT ser_count_reg_0_ ( .D ( N23 ) , .SI ( n13 ) , .SE ( test_se ) , - .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_count[0] ) , .QN ( dftopt11 ) ) ; -SDFFARX1_RVT ser_count_reg_1_ ( .D ( N24 ) , .SI ( dftopt13 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_count[1] ) , - .QN ( n13 ) ) ; -SDFFARX1_RVT ser_count_reg_2_ ( .D ( N25 ) , .SI ( dftopt12 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( ser_count[2] ) , - .QN ( dftopt5 ) ) ; -AND3X1_RVT U18 ( .A1 ( ser_count[1] ) , .A2 ( ser_count[0] ) , - .A3 ( ser_count[2] ) , .Y ( ser_done ) ) ; -AO222X1_RVT U19 ( .A1 ( DATA[0] ) , .A2 ( n16 ) , .A3 ( DATA_V[1] ) , - .A4 ( n15 ) , .A5 ( ser_out ) , .A6 ( n18 ) , .Y ( n24 ) ) ; -AO22X1_RVT U20 ( .A1 ( DATA_V[7] ) , .A2 ( n18 ) , .A3 ( DATA[7] ) , - .A4 ( n16 ) , .Y ( n25 ) ) ; -AO222X1_RVT U21 ( .A1 ( DATA[6] ) , .A2 ( n16 ) , .A3 ( DATA_V[7] ) , - .A4 ( n15 ) , .A5 ( DATA_V[6] ) , .A6 ( n18 ) , .Y ( n26 ) ) ; -AO222X1_RVT U22 ( .A1 ( DATA[5] ) , .A2 ( n16 ) , .A3 ( DATA_V[6] ) , - .A4 ( n15 ) , .A5 ( DATA_V[5] ) , .A6 ( n18 ) , .Y ( n27 ) ) ; -AO222X1_RVT U23 ( .A1 ( DATA[4] ) , .A2 ( n16 ) , .A3 ( DATA_V[5] ) , - .A4 ( n15 ) , .A5 ( DATA_V[4] ) , .A6 ( n18 ) , .Y ( n28 ) ) ; -AO222X1_RVT U24 ( .A1 ( DATA[3] ) , .A2 ( n16 ) , .A3 ( DATA_V[4] ) , - .A4 ( n15 ) , .A5 ( DATA_V[3] ) , .A6 ( n18 ) , .Y ( n29 ) ) ; -AO222X1_RVT U25 ( .A1 ( DATA[2] ) , .A2 ( n16 ) , .A3 ( DATA_V[3] ) , - .A4 ( n15 ) , .A5 ( DATA_V[2] ) , .A6 ( n18 ) , .Y ( n30 ) ) ; -AO222X1_RVT U26 ( .A1 ( DATA[1] ) , .A2 ( n16 ) , .A3 ( DATA_V[2] ) , - .A4 ( n15 ) , .A5 ( n18 ) , .A6 ( DATA_V[1] ) , .Y ( n31 ) ) ; -AND2X1_RVT U27 ( .A1 ( n19 ) , .A2 ( n20 ) , .Y ( n18 ) ) ; -NAND2X0_RVT U28 ( .A1 ( Enable ) , .A2 ( n19 ) , .Y ( n20 ) ) ; -NAND2X0_RVT U29 ( .A1 ( Data_Valid ) , .A2 ( n17 ) , .Y ( n19 ) ) ; -AO21X1_RVT U30 ( .A1 ( ser_count[2] ) , .A2 ( n21 ) , .A3 ( n22 ) , - .Y ( N25 ) ) ; -AND4X1_RVT U31 ( .A1 ( Enable ) , .A2 ( ser_count[1] ) , - .A3 ( ser_count[0] ) , .A4 ( dftopt5 ) , .Y ( n22 ) ) ; -AO21X1_RVT U32 ( .A1 ( Enable ) , .A2 ( n13 ) , .A3 ( N23 ) , .Y ( n21 ) ) ; -AND2X1_RVT U33 ( .A1 ( Enable ) , .A2 ( n23 ) , .Y ( N24 ) ) ; -AND2X1_RVT U34 ( .A1 ( Enable ) , .A2 ( dftopt11 ) , .Y ( N23 ) ) ; -INVX1_RVT U14 ( .A ( n20 ) , .Y ( n15 ) ) ; -INVX1_RVT U15 ( .A ( n19 ) , .Y ( n16 ) ) ; -INVX1_RVT U16 ( .A ( Busy ) , .Y ( n17 ) ) ; -XNOR2X1_RVT U17 ( .A1 ( n13 ) , .A2 ( ser_count[0] ) , .Y ( n23 ) ) ; -endmodule - - -module uart_tx_fsm_test_1 ( CLK , RST , Data_Valid , ser_done , - parity_enable , Ser_enable , mux_sel , busy , test_si , test_so , - test_se , dftopt0 , dftopt1 , dftopt2 , dftopt3 , dftopt11 , dftopt4 ) ; -input CLK ; -input RST ; -input Data_Valid ; -input ser_done ; -input parity_enable ; -output Ser_enable ; -output [1:0] mux_sel ; -output busy ; -input test_si ; -output test_so ; -input test_se ; -input dftopt0 ; -output dftopt1 ; -output dftopt2 ; -input dftopt3 ; -input dftopt11 ; -output dftopt4 ; - -wire dftopt2_gOb7 ; -wire current_state_1_ ; -wire current_state_0_ ; -wire busy_c ; -wire n5 ; -wire n8 ; -wire n10 ; -wire n11 ; -wire n12 ; -wire n13 ; -wire n14 ; -wire n15 ; -wire n6 ; -wire n9 ; -wire dftopt1_gOb4 ; -wire [2:0] next_state ; - -SDFFARX1_RVT current_state_reg_0_ ( .D ( next_state[0] ) , - .SI ( dftopt1_gOb4 ) , .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , - .Q ( current_state_0_ ) , .QN ( n8 ) ) ; -SDFFARX1_RVT current_state_reg_1_ ( .D ( next_state[1] ) , .SI ( n8 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( current_state_1_ ) , - .QN ( dftopt4 ) ) ; -SDFFARX1_RVT current_state_reg_2_ ( .D ( next_state[2] ) , .SI ( dftopt11 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( dftopt2_gOb7 ) , - .QN ( n5 ) ) ; -SDFFARX1_RVT busy_reg ( .D ( busy_c ) , .SI ( dftopt2_gOb7 ) , - .SE ( test_se ) , .CLK ( CLK ) , .RSTB ( RST ) , .Q ( busy ) , - .QN ( dftopt1_gOb4 ) ) ; -NOR3X0_RVT U9 ( .A1 ( dftopt4 ) , .A2 ( dftopt2_gOb7 ) , .A3 ( n10 ) , - .Y ( next_state[2] ) ) ; -OA21X1_RVT U10 ( .A1 ( parity_enable ) , .A2 ( n6 ) , - .A3 ( current_state_0_ ) , .Y ( n10 ) ) ; -OA21X1_RVT U11 ( .A1 ( n11 ) , .A2 ( n12 ) , .A3 ( n5 ) , - .Y ( next_state[1] ) ) ; -AND2X1_RVT U12 ( .A1 ( n13 ) , .A2 ( n5 ) , .Y ( next_state[0] ) ) ; -AO22X1_RVT U13 ( .A1 ( current_state_0_ ) , .A2 ( n6 ) , .A3 ( n14 ) , - .A4 ( dftopt4 ) , .Y ( n13 ) ) ; -OR2X1_RVT U14 ( .A1 ( Data_Valid ) , .A2 ( current_state_0_ ) , .Y ( n14 ) ) ; -AO21X1_RVT U15 ( .A1 ( n8 ) , .A2 ( n5 ) , .A3 ( n15 ) , .Y ( mux_sel[1] ) ) ; -AO22X1_RVT U16 ( .A1 ( n9 ) , .A2 ( n5 ) , .A3 ( dftopt2_gOb7 ) , - .A4 ( n15 ) , .Y ( mux_sel[0] ) ) ; -AO21X1_RVT U17 ( .A1 ( current_state_0_ ) , .A2 ( n5 ) , .A3 ( n15 ) , - .Y ( busy_c ) ) ; -AND3X1_RVT U18 ( .A1 ( n5 ) , .A2 ( n6 ) , .A3 ( n11 ) , .Y ( Ser_enable ) ) ; -AND2X1_RVT U19 ( .A1 ( n9 ) , .A2 ( current_state_0_ ) , .Y ( n11 ) ) ; -AO21X1_RVT U20 ( .A1 ( current_state_0_ ) , .A2 ( dftopt4 ) , .A3 ( n15 ) , - .Y ( n12 ) ) ; -AND2X1_RVT U21 ( .A1 ( current_state_1_ ) , .A2 ( n8 ) , .Y ( n15 ) ) ; -INVX1_RVT U7 ( .A ( n12 ) , .Y ( n9 ) ) ; -INVX1_RVT U8 ( .A ( ser_done ) , .Y ( n6 ) ) ; -endmodule - - -module UART_TX_DATA_WIDTH8_test_1 ( CLK , RST , P_DATA , Data_Valid , - parity_enable , parity_type , TX_OUT , busy , test_si , test_se , - dftopt4 , dftopt8 , dftopt9 , dftopt12 , dftopt14 , p0 , p1 , dftopt13 , - dftopt16 , dftopt17 , dftopt20 , dftopt18 , p2 , p3 ) ; -input CLK ; -input RST ; -input [7:0] P_DATA ; -input Data_Valid ; -input parity_enable ; -input parity_type ; -output TX_OUT ; -output busy ; -input test_si ; -input test_se ; -output dftopt4 ; -input dftopt8 ; -input dftopt9 ; -input dftopt12 ; -output dftopt14 ; -input p0 ; -input p1 ; -input dftopt13 ; -output dftopt16 ; -input dftopt17 ; -input dftopt20 ; -output dftopt18 ; -input p2 ; -input p3 ; - -wire dftopt0 ; -wire seriz_done ; -wire seriz_en ; -wire ser_data ; -wire parity ; -wire n3 ; -wire [1:0] mux_sel ; -wire dftopt3 ; -wire dftopt5 ; -wire dftopt6 ; -wire SYNOPSYS_UNCONNECTED_1 ; -wire SYNOPSYS_UNCONNECTED_2 ; -wire SYNOPSYS_UNCONNECTED_3 ; -wire SYNOPSYS_UNCONNECTED_4 ; -wire SYNOPSYS_UNCONNECTED_5 ; -wire SYNOPSYS_UNCONNECTED_6 ; -wire SYNOPSYS_UNCONNECTED_7 ; -wire SYNOPSYS_UNCONNECTED_8 ; -wire SYNOPSYS_UNCONNECTED_9 ; -wire SYNOPSYS_UNCONNECTED_10 ; -wire SYNOPSYS_UNCONNECTED_11 ; -wire SYNOPSYS_UNCONNECTED_12 ; -wire SYNOPSYS_UNCONNECTED_13 ; -wire SYNOPSYS_UNCONNECTED_14 ; -wire SYNOPSYS_UNCONNECTED_15 ; -wire SYNOPSYS_UNCONNECTED_16 ; -wire SYNOPSYS_UNCONNECTED_17 ; -wire SYNOPSYS_UNCONNECTED_18 ; -wire SYNOPSYS_UNCONNECTED_19 ; -wire SYNOPSYS_UNCONNECTED_20 ; -wire SYNOPSYS_UNCONNECTED_21 ; -wire SYNOPSYS_UNCONNECTED_22 ; -wire SYNOPSYS_UNCONNECTED_23 ; -wire SYNOPSYS_UNCONNECTED_24 ; -wire SYNOPSYS_UNCONNECTED_25 ; -wire SYNOPSYS_UNCONNECTED_26 ; -wire SYNOPSYS_UNCONNECTED_27 ; -wire SYNOPSYS_UNCONNECTED_28 ; -wire SYNOPSYS_UNCONNECTED_29 ; - -uart_tx_fsm_test_1 U0_fsm ( .CLK ( CLK ) , .RST ( RST ) , - .Data_Valid ( Data_Valid ) , .ser_done ( seriz_done ) , - .parity_enable ( parity_enable ) , .Ser_enable ( seriz_en ) , - .mux_sel ( mux_sel ) , .busy ( busy ) , - .test_si ( SYNOPSYS_UNCONNECTED_1 ) , - .test_so ( SYNOPSYS_UNCONNECTED_2 ) , .test_se ( test_se ) , - .dftopt0 ( SYNOPSYS_UNCONNECTED_3 ) , - .dftopt1 ( SYNOPSYS_UNCONNECTED_4 ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_5 ) , - .dftopt3 ( SYNOPSYS_UNCONNECTED_6 ) , .dftopt11 ( dftopt3 ) , - .dftopt4 ( dftopt6 ) ) ; -Serializer_WIDTH8_test_1 U0_Serializer ( .CLK ( CLK ) , .RST ( RST ) , - .DATA ( P_DATA ) , .Enable ( seriz_en ) , .Busy ( busy ) , - .Data_Valid ( Data_Valid ) , .ser_out ( ser_data ) , - .ser_done ( seriz_done ) , .test_si ( SYNOPSYS_UNCONNECTED_7 ) , - .test_so ( SYNOPSYS_UNCONNECTED_8 ) , .test_se ( test_se ) , - .dftopt0 ( dftopt0 ) , .dftopt1 ( SYNOPSYS_UNCONNECTED_9 ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_10 ) , .dftopt3 ( dftopt5 ) , - .dftopt4 ( SYNOPSYS_UNCONNECTED_11 ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_12 ) , .dftopt5 ( dftopt18 ) , - .dftopt6 ( SYNOPSYS_UNCONNECTED_13 ) , - .dftopt7 ( SYNOPSYS_UNCONNECTED_14 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_15 ) , - .dftopt10 ( SYNOPSYS_UNCONNECTED_16 ) , .dftopt13 ( dftopt13 ) , - .dftopt11 ( dftopt3 ) , .dftopt12 ( TX_OUT ) ) ; -mux_test_1 U0_mux ( .CLK ( CLK ) , .RST ( RST ) , - .IN_0 ( SYNOPSYS_UNCONNECTED_17 ) , .IN_1 ( ser_data ) , - .IN_2 ( parity ) , .IN_3 ( SYNOPSYS_UNCONNECTED_18 ) , .SEL ( mux_sel ) , - .OUT ( TX_OUT ) , .test_si ( SYNOPSYS_UNCONNECTED_19 ) , - .test_se ( test_se ) , .dftopt5 ( SYNOPSYS_UNCONNECTED_20 ) , - .p0 ( SYNOPSYS_UNCONNECTED_21 ) , .p1 ( SYNOPSYS_UNCONNECTED_22 ) , - .dftopt0 ( n3 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; -parity_calc_WIDTH8_test_1 U0_parity_calc ( .CLK ( CLK ) , .RST ( RST ) , - .parity_enable ( parity_enable ) , .parity_type ( parity_type ) , - .Busy ( busy ) , .DATA ( P_DATA ) , .Data_Valid ( Data_Valid ) , - .parity ( parity ) , .test_si ( SYNOPSYS_UNCONNECTED_23 ) , - .test_so ( n3 ) , .test_se ( test_se ) , - .dftopt2 ( SYNOPSYS_UNCONNECTED_24 ) , .dftopt0 ( dftopt4 ) , - .dftopt8 ( SYNOPSYS_UNCONNECTED_25 ) , .dftopt1 ( dftopt5 ) , - .dftopt4 ( SYNOPSYS_UNCONNECTED_26 ) , - .dftopt3 ( SYNOPSYS_UNCONNECTED_27 ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_28 ) , - .dftopt12 ( SYNOPSYS_UNCONNECTED_29 ) , .dftopt5 ( dftopt6 ) , - .dftopt6 ( dftopt16 ) , .dftopt17 ( dftopt17 ) , .dftopt20 ( dftopt20 ) , - .dftopt7 ( dftopt0 ) ) ; -endmodule - - -module mux2X1_1 ( IN_0 , IN_1 , SEL , OUT ) ; -input IN_0 ; -input IN_1 ; -input SEL ; -output OUT ; - -MUX21X1_RVT U1 ( .A1 ( IN_0 ) , .A2 ( IN_1 ) , .S0 ( SEL ) , .Y ( OUT ) ) ; -endmodule - - -module mux2X1_2 ( IN_0 , IN_1 , SEL , OUT ) ; -input IN_0 ; -input IN_1 ; -input SEL ; -output OUT ; - -wire cts0 ; - -MUX21X2_RVT U1 ( .A1 ( cts0 ) , .A2 ( IN_1 ) , .S0 ( SEL ) , .Y ( OUT ) ) ; -NBUFFX2_RVT IN_0_btd306 ( .A ( IN_0 ) , .Y ( cts0 ) ) ; -endmodule - - -module mux2X1_0 ( IN_0 , IN_1 , SEL , OUT ) ; -input IN_0 ; -input IN_1 ; -input SEL ; -output OUT ; - -wire cts0 ; - -MUX21X2_RVT U1 ( .A1 ( cts0 ) , .A2 ( IN_1 ) , .S0 ( SEL ) , .Y ( OUT ) ) ; -NBUFFX2_RVT IN_0_btd307 ( .A ( IN_0 ) , .Y ( cts0 ) ) ; -endmodule - - -module UART ( RST , TX_CLK , RX_CLK , RX_IN_S , RX_OUT_P , RX_OUT_V , - TX_IN_P , TX_IN_V , TX_OUT_S , TX_OUT_V , Prescale , parity_enable , - parity_type , parity_error , framing_error , SI , SE , SO , scan_clk , - scan_rst , test_mode ) ; -input RST ; -input TX_CLK ; -input RX_CLK ; -input RX_IN_S ; -output [7:0] RX_OUT_P ; -output RX_OUT_V ; -input [7:0] TX_IN_P ; -input TX_IN_V ; -output TX_OUT_S ; -output TX_OUT_V ; -input [5:0] Prescale ; -input parity_enable ; -input parity_type ; -output parity_error ; -output framing_error ; -input SI ; -input SE ; -output SO ; -input scan_clk ; -input scan_rst ; -input test_mode ; - -wire dftopt3 ; -wire UART_RX_SCAN_CLK ; -wire UART_TX_SCAN_CLK ; -wire SCAN_RST ; -wire dftopt2 ; -wire dftopt15 ; -wire HFSNET_0 ; -wire HFSNET_1 ; -wire optlc_net_426 ; -wire optlc_net_427 ; -wire dftopt14 ; -wire dftopt19 ; -wire SYNOPSYS_UNCONNECTED_1 ; -wire SYNOPSYS_UNCONNECTED_2 ; -wire SYNOPSYS_UNCONNECTED_3 ; -wire SYNOPSYS_UNCONNECTED_4 ; -wire SYNOPSYS_UNCONNECTED_5 ; -wire SYNOPSYS_UNCONNECTED_6 ; -wire SYNOPSYS_UNCONNECTED_7 ; -wire SYNOPSYS_UNCONNECTED_8 ; -wire SYNOPSYS_UNCONNECTED_9 ; -wire SYNOPSYS_UNCONNECTED_10 ; -wire SYNOPSYS_UNCONNECTED_11 ; -wire SYNOPSYS_UNCONNECTED_12 ; - -NBUFFX8_RVT HFSBUF_156_0 ( .A ( SE ) , .Y ( HFSNET_0 ) ) ; -mux2X1_0 U0_mux2X1 ( .IN_0 ( RX_CLK ) , .IN_1 ( scan_clk ) , - .SEL ( test_mode ) , .OUT ( UART_RX_SCAN_CLK ) ) ; -mux2X1_2 U1_mux2X1 ( .IN_0 ( TX_CLK ) , .IN_1 ( scan_clk ) , - .SEL ( test_mode ) , .OUT ( UART_TX_SCAN_CLK ) ) ; -mux2X1_1 U2_mux2X1 ( .IN_0 ( RST ) , .IN_1 ( scan_rst ) , .SEL ( test_mode ) , - .OUT ( SCAN_RST ) ) ; -UART_TX_DATA_WIDTH8_test_1 U0_UART_TX ( .CLK ( UART_TX_SCAN_CLK ) , - .RST ( HFSNET_1 ) , .P_DATA ( TX_IN_P ) , .Data_Valid ( TX_IN_V ) , - .parity_enable ( parity_enable ) , .parity_type ( parity_type ) , - .TX_OUT ( TX_OUT_S ) , .busy ( TX_OUT_V ) , - .test_si ( SYNOPSYS_UNCONNECTED_1 ) , .test_se ( HFSNET_0 ) , - .dftopt4 ( dftopt3 ) , .dftopt8 ( SYNOPSYS_UNCONNECTED_2 ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_3 ) , - .dftopt12 ( SYNOPSYS_UNCONNECTED_4 ) , - .dftopt14 ( SYNOPSYS_UNCONNECTED_5 ) , .p0 ( SYNOPSYS_UNCONNECTED_6 ) , - .p1 ( SYNOPSYS_UNCONNECTED_7 ) , .dftopt13 ( dftopt2 ) , - .dftopt16 ( dftopt15 ) , .dftopt17 ( dftopt14 ) , .dftopt20 ( dftopt19 ) , - .dftopt18 ( SO ) , .p2 ( optlc_net_426 ) , .p3 ( optlc_net_427 ) ) ; -UART_RX_test_1 U0_UART_RX ( .CLK ( UART_RX_SCAN_CLK ) , .RST ( HFSNET_1 ) , - .RX_IN ( RX_IN_S ) , .parity_enable ( parity_enable ) , - .parity_type ( parity_type ) , .Prescale ( Prescale ) , - .P_DATA ( RX_OUT_P ) , .data_valid ( RX_OUT_V ) , - .parity_error ( parity_error ) , .framing_error ( framing_error ) , - .test_si ( SI ) , .test_so ( SYNOPSYS_UNCONNECTED_8 ) , .test_se ( SE ) , - .dftopt4 ( dftopt3 ) , .dftopt8 ( SYNOPSYS_UNCONNECTED_9 ) , - .HFSNET_0 ( HFSNET_0 ) , .HFSNET_2 ( SCAN_RST ) , - .dftopt9 ( SYNOPSYS_UNCONNECTED_10 ) , - .dftopt10 ( SYNOPSYS_UNCONNECTED_11 ) , - .dftopt14 ( SYNOPSYS_UNCONNECTED_12 ) , .dftopt7 ( dftopt2 ) , - .dftopt16 ( dftopt15 ) , .dftopt15 ( dftopt14 ) , .dftopt20 ( dftopt19 ) ) ; -NBUFFX8_RVT HFSBUF_223_2 ( .A ( SCAN_RST ) , .Y ( HFSNET_1 ) ) ; -TIEH_RVT optlc_1045 ( .Y ( optlc_net_426 ) ) ; -TIEL_RVT optlc_1046 ( .Y ( optlc_net_427 ) ) ; -endmodule - - diff --git a/pnr/pnr.tcl b/pnr/pnr.tcl deleted file mode 100644 index a8ce0f4..0000000 --- a/pnr/pnr.tcl +++ /dev/null @@ -1,384 +0,0 @@ -####################################################################################################### -########################################## Data Setup ################################################ -####################################################################################################### - -set_app_var search_path "../ref/UART_design_data " - -set TECH_FILE "../ref/tech/saed32nm_1p9m.tf" - -set REFERENCE_LIBRARY "../ref/CLIBs/saed32rvt_ss0p75v125c.ndm" - -################################################################################ -## Create the design library -## Load the netlist -################################################################################ - -create_lib -technology $TECH_FILE -ref_libs $REFERENCE_LIBRARY UART.dlib - -read_verilog -top UART UART_mapped.v - -read_sdc UART_mapped.sdc - -link_block -force - -################################################################################ -## RC parasitics, placement site -## and routing layer setup -################################################################################ - -read_parasitic_tech -layermap ../ref/tech/saed32nm_tf_itf_tluplus.map -tlup ../ref/tech/saed32nm_1p9m_Cmax.tluplus -name maxTLU -read_parasitic_tech -layermap ../ref/tech/saed32nm_tf_itf_tluplus.map -tlup ../ref/tech/saed32nm_1p9m_Cmin.tluplus -name minTLU - -report_lib -parasitic_tech [current_lib] - -#preferred routing direction -set_attribute [get_layers {M1 M3 M5 M7 M9}] routing_direction horizontal -set_attribute [get_layers {M2 M4 M6 M8}] routing_direction vertical - -set_ignored_layers -max_routing_layer M8 - -set_attribute [get_site_defs unit] symmetry Y -set_attribute [get_site_defs unit] is_default true - -########################################################################################################## -########################################## Floorplanning ################################################ -########################################################################################################## - -set_parasitic_parameters -late_spec minTLU -early_spec maxTLU - -initialize_floorplan -core_utilization 0.7 -core_offset {3} - -create_placement -floorplan -legalize_placement - -set_block_pin_constraints -self -allowed_layers {M3 M4 M5 M6} -pin_spacing_distance 2 - -place_pins -self - -########################################################################################################## -########################################## Power planning ############################################### -########################################################################################################## - -source -echo ./scripts/power_network.tcl - -################################# -## Reports and check -################################# - -set reports_dir "./reports/Powerplanning" - -file mkdir $reports_dir - -check_pg_missing_vias > ${reports_dir}/check_pg_missing_vias.rpt -report_qor -summary -include setup > ${reports_dir}/report_qor.summary.rpt -report_timing -max_paths 5 > ${reports_dir}/report_timing.rpt -check_pg_drc -ignore_std_cells > ${reports_dir}/check_pg_drc.rpt -check_pg_connectivity -check_std_cell_pins none > ${reports_dir}/check_pg_connectivity.rpt - -########################################################################################################## -############################################# Placement ################################################# -########################################################################################################## - -################################################ -################## Analysis #################### -################################################ -report_qor -summary -report_ignored_layers -report_design -summary -report_utilization - -check_design -checks pre_placement_stage -check_design -checks physical_constraints - -# Analyze high fanout nets -report_net_fanout -high_fanout - -# Enable tie-cells -set_lib_cell_purpose -include optimization [get_lib_cells */TIE*] -set_dont_touch [get_lib_cells */TIE*] false - -# Limit the fanout of each tie cell to 8 -set_app_options -name opt.tie_cell.max_fanout -value 8 - -################################################ -########### Read the SCAN-DEF file ############# -################################################ -read_def UART.def - -################################################ -############# Application options ############## -################################################ - -# Enable create_placement, place_opt and clock_opt to call dft optimization. -set_app_options -list {opt.dft.optimize_scan_chain {true}} - -# route-driven-extration (RDE) -set_app_options -name opt.common.enable_rde -value true - -################################################ -########## placement and optimization ########## -################################################ - -place_opt - -#Performs global routing on the design. -route_global -effort_level minimum -congestion_map_only true - -################################################ -############## Check and Reports ############### -################################################ - -set reports_dir "./reports/Placement" - -file mkdir $reports_dir - -check_legality -verbose > ${reports_dir}/check_legality.rpt -report_qor -summary > ${reports_dir}/report_qor.summary.rpt -report_timing -nosplit -transition_time -capacitance -input_pins -nets -derate -delay_type max -path_type full_clock_expanded -voltage -significant_digits 4 -nworst 1 -physical -max_paths 100 > ${reports_dir}/report_timing.full.rpt -report_timing -nosplit -transition_time -capacitance -input_pins -nets -derate -delay_type max -voltage -significant_digits 4 -nworst 1 -physical -max_paths 100 > ${reports_dir}/report_timing.data.rpt - -# create_utilization_configuration -report_utilization > ${reports_dir}/report_utilization.rpt -report_congestion > ${reports_dir}/report_congestion.rpt - -########################################################################################################## -################################################ CTS ################################################### -########################################################################################################## - -#################################### -## Analysis -#################################### -report_clock_qor -type structure - -#################################### -## Clock Tree Targets -#################################### -set_clock_tree_options -target_skew 0.05 - -report_clock_tree_options - -#################################### -## CTS Cell Selection -#################################### -derive_clock_cell_references -output cts_leq_set.tcl > /dev/null - -set CTS_CELLS [get_lib_cells "*/NBUFF* */INVX* */CGL* */*DFF*"] -set_dont_touch $CTS_CELLS false -set_lib_cell_purpose -exclude cts [get_lib_cells] -set_lib_cell_purpose -include cts $CTS_CELLS - -report_lib_cells -objects [get_lib_cells] -columns {name:20 valid_purposes dont_touch} - - -#################################### -## CTS NDRs -#################################### - -source -echo ./scripts/ndr.tcl - -report_routing_rules -verbose - -report_clock_routing_rules - -#################################### -## Timing and DRC Setup -#################################### - -# Ensure that driving cells are specified on clock port -set_driving_cell -lib_cell NBUFFX16_RVT [get_ports TX_CLK] -set_driving_cell -lib_cell NBUFFX16_RVT [get_ports RX_CLK] - -report_ports -verbose [get_ports *CLK] -report_clocks -skew - -# Change the uncertainty - set_clock_uncertainty 0.2 -setup [all_clocks] - - set_clock_uncertainty 0.05 -hold [all_clocks] - -# max transition -set_max_transition 0.25 -clock_path [all_clocks] - -#################################### -## CTS Application options -#################################### -set_app_options -name time.remove_clock_reconvergence_pessimism -value true - -set_app_options -name clock_opt.flow.enable_ccd -value true - -#Enable global routing for congestion estimation -set_app_options -list {cts.compile.enable_global_route true} - -#Ignore ports for boundary identification (reset, scan_en, ...) -set_app_options -list {ccd.ignore_scan_reset_for_boundary_identification {false}} - -#################################### -## Pre CTS Reports checks -#################################### - -# Report clock tree max_tran/cap/references/... in all clocks+modes: -report_clock_settings - -report_qor -summary - -# Report clock tree target skew/latency constraints: -report_clock_tree_options - -# Report non-default routing rules in a more compact way -report_clock_routing_rules - -######################################################################## -## Clock tree synthesis, clock tree routing, and data path optimization -######################################################################## -clock_opt - -#################################### -## Post CTS Reports checks -#################################### - -set reports_dir "./reports/CTS" - -file mkdir $reports_dir - -report_qor -summary > ${reports_dir}/report_qor.rpt -report_clock_qor -type summary > ${reports_dir}/report_clock_qor.rpt -report_clock_qor -clock [all_clocks] -type latency > ${reports_dir}/latency.rpt -report_clock_qor -clock [all_clocks] -type local_skew -largest 100 > ${reports_dir}/local_skew.rpt -report_constraints -max_transition -all_violators -significant_digits 3 -verbose > ${reports_dir}/report_constraints_max_transition.rpt -report_constraints -max_capacitance -all_violators -significant_digits 3 -verbose >> ${reports_dir}/report_constraints_max_capacitance.rpt -check_legality -verbose > ${reports_dir}/check_legality.rpt - -########################################################################################################## -############################################# Routing ################################################## -########################################################################################################## - -#################################### -## Pre_route checks -#################################### -check_design -checks pre_route_stage -check_routability - -### update design latency -compute_clock_latency -verbose - -#################################### -## Routing Application options -#################################### - -# Antenna rule file -source -echo ../ref/tech/saed32nm_ant_1p9m.tcl -report_app_options route.detail.*antenna* - -# global route -#Enable crosstalk only during track assignment -set_app_options -name route.global.crosstalk_driven -value false -set_app_options -name route.global.timing_driven -value true -set_app_options -name route.global.effort_level -value high -set_app_options -name route.global.timing_driven_effort_level -value high - -# track assignment -set_app_options -name route.track.crosstalk_driven -value true -set_app_options -name route.track.timing_driven -value true - -# detail route -set_app_options -name route.detail.antenna -value true -set_app_options -name route.detail.antenna_fixing_preference -value use_diodes -set_app_options -name route.detail.diode_libcell_names -value */ANTENNA_RVT -set_app_options -name route.detail.timing_driven -value true -set_app_options -name route.detail.save_after_iterations -value 2 -set_app_options -name route.detail.optimize_wire_via_effort_level -value high - -### route opt app options -set_app_options -name route_opt.flow.enable_ccd -value true -set_app_options -name route_opt.flow.enable_ccd_clock_drc_fixing -value auto -set_app_options -name route_opt.flow.enable_clock_power_recovery -value false - -#Post-Route Timing Analysis -set_app_options -name time.si_enable_analysis -value true -set_app_options -name time.enable_si_timing_windows -value true - - -#################################### -## Routing -#################################### - -#global routing + track assignment + detail routing - -route_auto - - -#################################### -## Post-Route Optimization -#################################### - -route_opt - -#################################### -## Post Routing Reports checks -#################################### - -set reports_dir "./reports/Routing" - -file mkdir $reports_dir - -report_qor -summary > ${reports_dir}/report_qor.rpt -check_legality -verbose > ${reports_dir}/check_legality.rpt -report_timing -max_paths 5 > ${reports_dir}/report_timing.rpt -report_constraints -max_transition -all_violators -significant_digits 3 -verbose > ${reports_dir}/report_constraints_max_transition.rpt -report_constraints -max_capacitance -all_violators -significant_digits 3 -verbose >> ${reports_dir}/report_constraints_max_capacitance.rpt -check_routes > ${reports_dir}/check_routes.rpt -check_lvs > ${reports_dir}/check_lvs.rpt - -#################################### -## insert filler cells -#################################### -create_stdcell_fillers -lib_cells {*/SHFILL128_RVT */SHFILL64_RVT */SHFILL3_RVT */SHFILL2_RVT */SHFILL1_RVT} -continue_on_error - -connect_pg_net -all_blocks -automatic - -remove_stdcell_fillers_with_violation - -#################################### -## gds -#################################### -set design "UART" - -set gds_file "output/${design}.gds" -set_app_options -name file.gds.contact_prefix -value "${design}_" -write_gds -long_names -design $design -hierarchy design_lib -lib_cell_view frame -keep_data_type -fill exclude $gds_file -#################################### -## netlist -#################################### -set netlist_name "output/${design}.v" -write_verilog $netlist_name -exclude {all_physical_cells analog_pg corner_cells cover_cells diode_cells empty_modules end_cap_cells physical_only_cells filler_cells pg_objects well_tap_cells leaf_module_declarations} - -#################################### -## lvs netlist -#################################### -set lvs_netlist "output/${design}.lvs.v" -write_verilog $lvs_netlist -exclude {empty_modules end_cap_cells well_tap_cells} - -#################################### -## def -#################################### -set def_name "output/${design}.def" -write_def -design $design -include_tech_via_definitions -include {blockages bounds cells nets ports routing_rules rows_tracks specialnets vias} $def_name - -#################################### -## lef -#################################### -set lef_name "output/${design}.lef" -# create_frame -create_frame -block_all auto -hierarchical true -merge_metal_blockage true -# write_lef -write_lef -design ${design}.frame $lef_name -include cell - -set techlef_name "output/${design}.tlef" -write_lef -design ${design}.frame $techlef_name -include tech - -#################################### -## Save Block -#################################### -save_block -save_lib -all - diff --git a/pnr/reports/CTS/check_legality.rpt b/pnr/reports/CTS/check_legality.rpt deleted file mode 100644 index 4052942..0000000 --- a/pnr/reports/CTS/check_legality.rpt +++ /dev/null @@ -1,110 +0,0 @@ - -************************ - -running check_legality - -Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -PDC app_options settings ========= - place.legalize.enable_prerouted_net_check: 1 - place.legalize.num_tracks_for_access_check: 1 - place.legalize.use_eol_spacing_for_access_check: 0 - place.legalize.allow_touch_track_for_access_check: 1 - place.legalize.reduce_conservatism_in_eol_check: 0 - place.legalize.preroute_shape_merge_distance: 0.0 - place.legalize.enable_non_preferred_direction_span_check: 0 - -Layer M1: cached 0 shapes out of 38 total shapes. -Layer M2: cached 0 shapes out of 99 total shapes. -Cached 0 vias out of 249 total vias. - -check_legality for block design UART ... -Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Design has no advanced rules -Checking legality -Checking cell legality: -0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% -Sorting rows. -Checking spacing rule legality. -0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% -Checking packing rule legality. - - -**************************************** - Report : Legality -**************************************** - -VIOLATIONS BY CATEGORY: - MOVABLE APP-FIXED USER-FIXED DESCRIPTION - 0 0 0 Two objects overlap. - 0 0 0 A cell violates a pnet. - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell is not aligned with a site. - 0 0 0 A cell has an illegal orientation. - 0 0 0 A cell spacing rule is violated. - 0 0 0 A layer rule is violated. - 0 0 0 A cell is in the wrong region. - 0 0 0 Two cells violate cts margins. - 0 0 0 Two cells violate coloring. - - 0 0 0 TOTAL - -TOTAL 0 Violations. - -VIOLATIONS BY SUBCATEGORY: - MOVABLE APP-FIXED USER-FIXED DESCRIPTION - - 0 0 0 Two objects overlap. - 0 0 0 Two cells overlap. - 0 0 0 Two cells have overlapping keepout margins. - 0 0 0 A cell overlaps a blockage. - 0 0 0 A cell keepout margin overlaps a blockage. - - 0 0 0 A cell violates a pnet. - - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell violates pin-track alignment rules. - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell violates legal index rule. - 0 0 0 A cell has the wrong variant for its location. - - 0 0 0 A cell is not aligned with a site. - 0 0 0 A cell is not aligned with the base site. - 0 0 0 A cell is not aligned with an overlaid site. - - 0 0 0 A cell has an illegal orientation. - - 0 0 0 A cell spacing rule is violated. - 0 0 0 A spacing rule is violated in a row. - 0 0 0 A spacing rule is violated between adjacent rows. - 0 0 0 A cell violates vertical abutment rule. - 0 0 0 A cell violates metal spacing rule. - - 0 0 0 A layer rule is violated. - 0 0 0 A layer VTH rule is violated. - 0 0 0 A layer OD rule is violated. - 0 0 0 A layer OD max-width rule is violated. - 0 0 0 A layer ALL_OD corner rule is violated. - 0 0 0 A layer max-vertical-length rule is violated. - 0 0 0 A layer TPO rule is violated. - 0 0 0 Filler cell insertion cannot satisfy layer rules. - - 0 0 0 A cell is in the wrong region. - 0 0 0 A cell is outside its hard bound. - 0 0 0 A cell is in the wrong voltage area. - 0 0 0 A cell violates an exclusive movebound. - - 0 0 0 Two cells violate cts margins. - - 0 0 0 Two cells violate coloring. - - -check_legality for block design UART succeeded! - - -check_legality succeeded. - -************************** - -1 diff --git a/pnr/reports/CTS/latency.rpt b/pnr/reports/CTS/latency.rpt deleted file mode 100644 index 685b857..0000000 --- a/pnr/reports/CTS/latency.rpt +++ /dev/null @@ -1,71 +0,0 @@ -Warning: Use -per_clock_root option along with -type latency option to split the reporting of a clock to per clock root, so that the clock trees associated with different root pins are reported separately - Info: Initializing timer in CLOCK_SYN_MODE -**************************************** -Report : clock qor - -type latency - -clocks SCAN_CLK - UART_CLK_RX - UART_CLK_TX -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:11:31 2024 -**************************************** - -Attributes -=========== -M Master Clock -G Generated Clock -& Internal Generated Clock -U User Defined Skew Group -D Default Skew Group -* Generated Clock Balanced Separately - -============================================== -==== Latency Reporting for Corner default ==== -============================================== - -=================================================== Summary Table for Corner default =================================================== -Clock / Attrs Sinks Target Global Target Max Min Median Latency Boundary -Skew Group Skew Skew Latency Latency Latency Latency Std Dev Skew ----------------------------------------------------------------------------------------------------------------------------------------- -### Mode: default, Scenario: default -SCAN_CLK M,D 53 10.00 0.02 -- 0.32 0.30 0.32 0.01 -- ----------------------------------------------------------------------------------------------------------------------------------------- -All Clocks 53 0.05 0.02 -- 0.32 0.30 -- -- -- - - - & = Offset derived from max_clock_tree_path / min_clock_tree_path - r = latency reported is for a rising edge triggered event at the sink - f = latency reported is for a falling edge triggered event at the sink - - -Showing 5 largest and 5 smallest datapoints per clock / skew group (L=largest, S=smallest) -========================================== Details Table for Corner default ========================================== -Clock / Sink Launch Capture Late Early -Skew Group Name Latency Latency Offset Offset ----------------------------------------------------------------------------------------------------------------------- -### Mode: default, Scenario: default -SCAN_CLK - L U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- - L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- - L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- - L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- - L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- - S U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - 0.30 r 0.30 r -- -- - S U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- - S U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- - S U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - 0.30 r 0.30 r -- -- - S U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - 0.30 r 0.30 r -- -- - - -1 diff --git a/pnr/reports/CTS/local_skew.rpt b/pnr/reports/CTS/local_skew.rpt deleted file mode 100644 index bd3dae4..0000000 --- a/pnr/reports/CTS/local_skew.rpt +++ /dev/null @@ -1,650 +0,0 @@ - Info: Initializing timer in CLOCK_SYN_MODE -**************************************** -Report : clock qor - -type local_skew - -largest 100 - -clocks SCAN_CLK - UART_CLK_RX - UART_CLK_TX -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:11:31 2024 -**************************************** - -Attributes -=========== -M Master Clock -G Generated Clock -& Internal Generated Clock -U User Defined Skew Group -D Default Skew Group -* Generated Clock Balanced Separately - -================================================= -==== Local Skew Reporting for Corner default ==== -================================================= - -======================================== Summary Table for Corner default ======================================== -Clock / Attrs Sinks Global Max Local Skew Max Setup Max Hold -Skew Group Skew Latency Pair Count Local Skew Local Skew ------------------------------------------------------------------------------------------------------------------- -### Mode: default, Scenario: default -SCAN_CLK M,D 53 0.02 0.32 457 0.02 0.02 ------------------------------------------------------------------------------------------------------------------- -All Clocks 53 0.02 0.32 0.02 0.02 - - - r = latency reported is for a rising edge triggered event at the sink - f = latency reported is for a falling edge triggered event at the sink - - -Showing 100 largest datapoints per clock / skew group (L=largest, S=smallest) -=============================================== Details Table for Corner default =============================================== -Clock / Launch Sink Capture Sink Launch Capture Late Early Local -Skew Group Name Name Latency Latency Offset Offset Skew --------------------------------------------------------------------------------------------------------------------------------- -### Mode: default, Scenario: default -SCAN_CLK - L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK - 0.32 r 0.30 r -- -- 0.02 - L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK - 0.32 r 0.30 r -- -- 0.02 - L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.32 r 0.30 r -- -- 0.02 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_fsm/busy_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_mux/OUT_reg/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_fsm/busy_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_fsm/busy_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/parity_reg/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK - U0_UART_TX/U0_parity_calc/parity_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/parity_reg/CLK - U0_UART_TX/U0_mux/OUT_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK - U0_UART_TX/U0_mux/OUT_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_mux/OUT_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_1_/CLK - U0_UART_TX/U0_mux/OUT_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_0_/CLK - U0_UART_TX/U0_mux/OUT_reg/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/current_state_reg_2_/CLK - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - L U0_UART_TX/U0_fsm/busy_reg/CLK - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK - 0.30 r 0.30 r -- -- 0.00 - (H) L U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK - 0.30 r 0.32 r -- -- 0.02 - (H) L U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK - 0.30 r 0.32 r -- -- 0.02 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - (H) L U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK - 0.32 r 0.32 r -- -- 0.00 - - -1 diff --git a/pnr/reports/CTS/report_clock_qor.rpt b/pnr/reports/CTS/report_clock_qor.rpt deleted file mode 100644 index 1dc09a9..0000000 --- a/pnr/reports/CTS/report_clock_qor.rpt +++ /dev/null @@ -1,42 +0,0 @@ - Info: Initializing timer in CLOCK_SYN_MODE -Information: The stitching and editing of coupling caps is turned OFF for design 'UART.dlib:UART.design'. (TIM-125) -Information: The RC mode used is CTO(RDE) for design 'UART'. (NEX-022) -Information: Update timing completed net estimation for all the timing graph nets (TIM-111) -Information: Net estimation statistics: timing graph nets = 439, routed nets = 5, across physical hierarchy nets = 0, parasitics cached nets = 5, delay annotated nets = 0, parasitics annotated nets = 0, multi-voltage nets = 0. (TIM-112) -Warning: The scenario default has max transition DRC fixing disabled using the set_scenario_status command. High DRC count may be expected. -Warning: The scenario default has max capacitance DRC fixing disabled using the set_scenario_status command. High DRC count may be expected. -**************************************** -Report : clock qor - -type summary -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:11:31 2024 -**************************************** - -Attributes -=========== -M Master Clock -G Generated Clock -& Internal Generated Clock -U User Defined Skew Group -D Default Skew Group -* Generated Clock Balanced Separately - -============================================== -==== Summary Reporting for Corner default ==== -============================================== - -================================================= Summary Table for Corner default ================================================= -Clock / Attrs Sinks Levels Clock Clock Clock Max Global Trans DRC Cap DRC -Skew Group Repeater Repeater Stdcell Latency Skew Count Count - Count Area Area ------------------------------------------------------------------------------------------------------------------------------------- -### Mode: default, Scenario: default -SCAN_CLK M,D 53 2 0 0.00 7.12 0.32 0.02 0 0 -UART_CLK_TX M,D 0 0 0 0.00 0.00 -- -- 0 0 -UART_CLK_RX M,D 0 0 0 0.00 0.00 -- -- 0 0 ------------------------------------------------------------------------------------------------------------------------------------- -All Clocks 53 2 0 0.00 7.12 0.32 0.02 0 0 - - -1 diff --git a/pnr/reports/CTS/report_constraints_max_capacitance.rpt b/pnr/reports/CTS/report_constraints_max_capacitance.rpt deleted file mode 100644 index 490b11f..0000000 --- a/pnr/reports/CTS/report_constraints_max_capacitance.rpt +++ /dev/null @@ -1,30 +0,0 @@ -**************************************** -Report : constraint - -verbose - -all_violators - -max_capacitance -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 17:46:09 2024 -**************************************** - - - - - Total number of violation(s): 0 -1 -**************************************** -Report : constraint - -verbose - -all_violators - -max_capacitance -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:11:31 2024 -**************************************** - - - - - Total number of violation(s): 0 -1 diff --git a/pnr/reports/CTS/report_constraints_max_transition.rpt b/pnr/reports/CTS/report_constraints_max_transition.rpt deleted file mode 100644 index bcb5501..0000000 --- a/pnr/reports/CTS/report_constraints_max_transition.rpt +++ /dev/null @@ -1,18 +0,0 @@ -**************************************** -Report : constraint - -verbose - -all_violators - -max_transition -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:11:31 2024 -**************************************** - - - -Information: The stitching and editing of coupling caps is turned OFF for design 'UART.dlib:UART.design'. (TIM-125) -Information: Update timing completed net estimation for all the timing graph nets (TIM-111) -Information: Net estimation statistics: timing graph nets = 439, routed nets = 5, across physical hierarchy nets = 0, parasitics cached nets = 9, delay annotated nets = 0, parasitics annotated nets = 0, multi-voltage nets = 0. (TIM-112) - - Total number of violation(s): 0 -1 diff --git a/pnr/reports/CTS/report_qor.rpt b/pnr/reports/CTS/report_qor.rpt deleted file mode 100644 index bd1d61d..0000000 --- a/pnr/reports/CTS/report_qor.rpt +++ /dev/null @@ -1,24 +0,0 @@ -**************************************** -Report : qor - -summary -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:11:31 2024 -**************************************** -Information: Timer using 'CRPR'. (TIM-050) - -Timing ---------------------------------------------------------------------------- -Context WNS TNS NVE ---------------------------------------------------------------------------- -Design (Setup) 97.26 0.00 0 - -Design (Hold) 0.29 0.00 0 ---------------------------------------------------------------------------- - -Miscellaneous ---------------------------------------------------------------------------- -Cell Area (netlist): 1279.87 -Cell Area (netlist and physical only): 1279.87 -Nets with DRC Violations: 0 -1 diff --git a/pnr/reports/Placement/check_legality.rpt b/pnr/reports/Placement/check_legality.rpt deleted file mode 100644 index 289aec3..0000000 --- a/pnr/reports/Placement/check_legality.rpt +++ /dev/null @@ -1,110 +0,0 @@ - -************************ - -running check_legality - -Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -PDC app_options settings ========= - place.legalize.enable_prerouted_net_check: 1 - place.legalize.num_tracks_for_access_check: 1 - place.legalize.use_eol_spacing_for_access_check: 0 - place.legalize.allow_touch_track_for_access_check: 1 - place.legalize.reduce_conservatism_in_eol_check: 0 - place.legalize.preroute_shape_merge_distance: 0.0 - place.legalize.enable_non_preferred_direction_span_check: 0 - -Layer M1: cached 0 shapes out of 26 total shapes. -Layer M2: cached 0 shapes out of 0 total shapes. -Cached 0 vias out of 61 total vias. - -check_legality for block design UART ... -Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Design has no advanced rules -Checking legality -Checking cell legality: -0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% -Sorting rows. -Checking spacing rule legality. -0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% -Checking packing rule legality. - - -**************************************** - Report : Legality -**************************************** - -VIOLATIONS BY CATEGORY: - MOVABLE APP-FIXED USER-FIXED DESCRIPTION - 0 0 0 Two objects overlap. - 0 0 0 A cell violates a pnet. - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell is not aligned with a site. - 0 0 0 A cell has an illegal orientation. - 0 0 0 A cell spacing rule is violated. - 0 0 0 A layer rule is violated. - 0 0 0 A cell is in the wrong region. - 0 0 0 Two cells violate cts margins. - 0 0 0 Two cells violate coloring. - - 0 0 0 TOTAL - -TOTAL 0 Violations. - -VIOLATIONS BY SUBCATEGORY: - MOVABLE APP-FIXED USER-FIXED DESCRIPTION - - 0 0 0 Two objects overlap. - 0 0 0 Two cells overlap. - 0 0 0 Two cells have overlapping keepout margins. - 0 0 0 A cell overlaps a blockage. - 0 0 0 A cell keepout margin overlaps a blockage. - - 0 0 0 A cell violates a pnet. - - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell violates pin-track alignment rules. - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell violates legal index rule. - 0 0 0 A cell has the wrong variant for its location. - - 0 0 0 A cell is not aligned with a site. - 0 0 0 A cell is not aligned with the base site. - 0 0 0 A cell is not aligned with an overlaid site. - - 0 0 0 A cell has an illegal orientation. - - 0 0 0 A cell spacing rule is violated. - 0 0 0 A spacing rule is violated in a row. - 0 0 0 A spacing rule is violated between adjacent rows. - 0 0 0 A cell violates vertical abutment rule. - 0 0 0 A cell violates metal spacing rule. - - 0 0 0 A layer rule is violated. - 0 0 0 A layer VTH rule is violated. - 0 0 0 A layer OD rule is violated. - 0 0 0 A layer OD max-width rule is violated. - 0 0 0 A layer ALL_OD corner rule is violated. - 0 0 0 A layer max-vertical-length rule is violated. - 0 0 0 A layer TPO rule is violated. - 0 0 0 Filler cell insertion cannot satisfy layer rules. - - 0 0 0 A cell is in the wrong region. - 0 0 0 A cell is outside its hard bound. - 0 0 0 A cell is in the wrong voltage area. - 0 0 0 A cell violates an exclusive movebound. - - 0 0 0 Two cells violate cts margins. - - 0 0 0 Two cells violate coloring. - - -check_legality for block design UART succeeded! - - -check_legality succeeded. - -************************** - -1 diff --git a/pnr/reports/Placement/report_congestion.rpt b/pnr/reports/Placement/report_congestion.rpt deleted file mode 100644 index 6199d29..0000000 --- a/pnr/reports/Placement/report_congestion.rpt +++ /dev/null @@ -1,16 +0,0 @@ -Warning: Layer MRDL does not have a preferred direction, skipped. -**************************************** -Report : congestion -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:09:16 2024 -**************************************** - -Layer | overflow | # GRCs has -Name | total | max | overflow (%) | max overflow ---------------------------------------------------------------- -Both Dirs | 2 | 1 | 2 ( 0.51%) | 2 -H routing | 2 | 1 | 2 ( 1.02%) | 2 -V routing | 0 | 0 | 0 ( 0.00%) | 0 - -1 diff --git a/pnr/reports/Placement/report_qor.summary.rpt b/pnr/reports/Placement/report_qor.summary.rpt deleted file mode 100644 index 87f60d8..0000000 --- a/pnr/reports/Placement/report_qor.summary.rpt +++ /dev/null @@ -1,23 +0,0 @@ -**************************************** -Report : qor - -summary -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:09:16 2024 -**************************************** - -Timing ---------------------------------------------------------------------------- -Context WNS TNS NVE ---------------------------------------------------------------------------- -Design (Setup) 97.24 0.00 0 - -Design (Hold) 0.21 0.00 0 ---------------------------------------------------------------------------- - -Miscellaneous ---------------------------------------------------------------------------- -Cell Area (netlist): 1275.80 -Cell Area (netlist and physical only): 1275.80 -Nets with DRC Violations: 0 -1 diff --git a/pnr/reports/Placement/report_timing.data.rpt b/pnr/reports/Placement/report_timing.data.rpt deleted file mode 100644 index a9f2f77..0000000 --- a/pnr/reports/Placement/report_timing.data.rpt +++ /dev/null @@ -1,4250 +0,0 @@ -**************************************** -Report : timing - -path_type full - -delay_type max - -nworst 1 - -max_paths 100 - -report_by design - -nosplit - -input_pins - -nets - -transition_time - -capacitance - -derate - -physical - -voltage -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:09:16 2024 -**************************************** - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 0.2075 1.0000 0.4391 0.4391 r (21.87,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[2] (net) 7 10.6520 - U0_UART_RX/U0_data_sampling/U50/A (INVX0_RVT) 0.2075 1.0000 0.0002 0.4393 r (9.05,37.36) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.1266 1.0000 0.1194 0.5586 f (8.84,37.32) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n45 (net) 2 2.5379 - U0_UART_RX/U0_data_sampling/U49/A1 (XOR2X1_RVT) 0.1266 1.0000 0.0000 0.5587 f (6.23,40.82) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.0719 1.0000 0.2412 0.7998 r (7.50,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n52 (net) 1 0.7964 - U0_UART_RX/U0_data_sampling/U48/A3 (AND3X1_RVT) 0.0719 1.0000 0.0000 0.7998 r (9.26,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.0549 1.0000 0.1409 0.9407 r (10.08,38.94) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n50 (net) 1 0.7079 - U0_UART_RX/U0_data_sampling/U47/A4 (NAND4X0_RVT) 0.0549 1.0000 0.0000 0.9407 r (11.18,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 0.2413 1.0000 0.2169 1.1577 f (10.88,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n27 (net) 3 3.2599 - U0_UART_RX/U0_data_sampling/U39/A3 (AND4X1_RVT) 0.2413 1.0000 0.0000 1.1577 f (11.24,37.05) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.0793 1.0000 0.3025 1.4602 f (12.06,37.28) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n38 (net) 1 0.6254 - U0_UART_RX/U0_data_sampling/U38/A4 (AND4X1_RVT) 0.0793 1.0000 0.0000 1.4602 f (11.85,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.1059 1.0000 0.2507 1.7109 f (12.82,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n22 (net) 2 2.8795 - U0_UART_RX/U0_data_sampling/U28/A3 (NOR4X0_RVT) 0.1059 1.0000 0.0000 1.7109 f (14.12,35.65) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U28/Y (NOR4X0_RVT) 0.0610 1.0000 0.2797 1.9906 r (15.10,35.60) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n19 (net) 1 1.8397 - U0_UART_RX/U0_data_sampling/U27/S0 (MUX21X1_RVT) 0.0610 1.0000 0.0000 1.9906 r (23.14,37.23) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U27/Y (MUX21X1_RVT) 0.0821 1.0000 0.2034 2.1940 f (22.21,37.26) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n25 (net) 1 0.7919 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/D (SDFFARX1_RVT) 0.0821 1.0000 0.0000 2.1940 f (23.09,35.51) 0.7500 (rail VDD) - data arrival time 2.1940 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.01,36.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3119 99.4381 - data required time 99.4381 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4381 - data arrival time -2.1940 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.2442 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 0.2075 1.0000 0.4391 0.4391 r (21.87,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[2] (net) 7 10.6520 - U0_UART_RX/U0_data_sampling/U50/A (INVX0_RVT) 0.2075 1.0000 0.0002 0.4393 r (9.05,37.36) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.1266 1.0000 0.1194 0.5586 f (8.84,37.32) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n45 (net) 2 2.5379 - U0_UART_RX/U0_data_sampling/U49/A1 (XOR2X1_RVT) 0.1266 1.0000 0.0000 0.5587 f (6.23,40.82) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.0719 1.0000 0.2412 0.7998 r (7.50,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n52 (net) 1 0.7964 - U0_UART_RX/U0_data_sampling/U48/A3 (AND3X1_RVT) 0.0719 1.0000 0.0000 0.7998 r (9.26,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.0549 1.0000 0.1409 0.9407 r (10.08,38.94) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n50 (net) 1 0.7079 - U0_UART_RX/U0_data_sampling/U47/A4 (NAND4X0_RVT) 0.0549 1.0000 0.0000 0.9407 r (11.18,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 0.2413 1.0000 0.2169 1.1577 f (10.88,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n27 (net) 3 3.2599 - U0_UART_RX/U0_data_sampling/U39/A3 (AND4X1_RVT) 0.2413 1.0000 0.0000 1.1577 f (11.24,37.05) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.0793 1.0000 0.3025 1.4602 f (12.06,37.28) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n38 (net) 1 0.6254 - U0_UART_RX/U0_data_sampling/U38/A4 (AND4X1_RVT) 0.0793 1.0000 0.0000 1.4602 f (11.85,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.1059 1.0000 0.2507 1.7109 f (12.82,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n22 (net) 2 2.8795 - U0_UART_RX/U0_data_sampling/U37/S0 (MUX21X1_RVT) 0.1059 1.0000 0.0000 1.7109 f (22.38,39.00) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U37/Y (MUX21X1_RVT) 0.0861 1.0000 0.2357 1.9466 f (23.31,38.96) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n24 (net) 1 1.0282 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/D (SDFFARX1_RVT) 0.0861 1.0000 0.0000 1.9467 f (24.15,44.06) 0.7500 (rail VDD) - data arrival time 1.9467 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (25.07,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3137 99.4363 - data required time 99.4363 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4363 - data arrival time -1.9467 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.4897 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U16/A4 (AO22X1_RVT) 0.2332 1.0000 0.0000 1.6994 r (36.31,34.16) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U16/Y (AO22X1_RVT) 0.0976 1.0000 0.2005 1.8999 r (36.90,33.91) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n32 (net) 1 1.0049 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/D (SDFFARX1_RVT) 0.0976 1.0000 0.0000 1.8999 r (41.02,32.16) 0.7500 (rail VDD) - data arrival time 1.8999 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.94,32.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2800 99.4700 - data required time 99.4700 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4700 - data arrival time -1.8999 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5701 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U27/A3 (AO21X1_RVT) 0.1206 1.0000 0.0000 1.4703 f (22.94,27.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U27/Y (AO21X1_RVT) 0.0654 1.0000 0.1430 1.6133 f (23.37,27.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n27 (net) 2 1.6571 - U0_UART_RX/U0_edge_bit_counter/U24/A3 (AO21X1_RVT) 0.0654 1.0000 0.0000 1.6133 f (26.23,27.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U24/Y (AO21X1_RVT) 0.0564 1.0000 0.1040 1.7173 f (25.80,27.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n24 (net) 1 0.7008 - U0_UART_RX/U0_edge_bit_counter/U22/A2 (AO22X1_RVT) 0.0564 1.0000 0.0000 1.7173 f (26.08,25.77) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U22/Y (AO22X1_RVT) 0.0491 1.0000 0.1598 1.8771 f (25.34,25.59) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n30 (net) 1 0.8101 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/D (SDFFARX1_RVT) 0.0491 1.0000 0.0000 1.8771 f (24.00,24.00) 0.7500 (rail VDD) - data arrival time 1.8771 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.92,23.24) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2982 99.4518 - data required time 99.4518 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4518 - data arrival time -1.8771 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5746 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U3/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (34.90,44.65) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U3/Y (AO22X1_RVT) 0.0992 1.0000 0.1827 1.8822 r (34.46,43.94) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n18 (net) 1 1.1386 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/D (SDFFARX1_RVT) 0.0992 1.0000 0.0000 1.8822 r (29.17,40.72) 0.7500 (rail VDD) - data arrival time 1.8822 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.09,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2808 99.4692 - data required time 99.4692 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4692 - data arrival time -1.8822 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5870 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U8/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (38.74,41.30) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U8/Y (AO22X1_RVT) 0.0974 1.0000 0.1804 1.8798 r (39.18,40.60) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n24 (net) 1 0.9929 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/D (SDFFARX1_RVT) 0.0974 1.0000 0.0000 1.8798 r (41.17,44.06) 0.7500 (rail VDD) - data arrival time 1.8798 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2799 99.4701 - data required time 99.4701 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4701 - data arrival time -1.8798 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5902 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U4/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (36.42,44.65) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U4/Y (AO22X1_RVT) 0.0970 1.0000 0.1797 1.8792 r (35.98,43.94) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n20 (net) 1 0.9589 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/D (SDFFARX1_RVT) 0.0970 1.0000 0.0000 1.8792 r (29.62,44.06) 0.7500 (rail VDD) - data arrival time 1.8792 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.54,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2797 99.4703 - data required time 99.4703 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4703 - data arrival time -1.8792 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5911 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U6/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (38.90,41.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U6/Y (AO22X1_RVT) 0.0956 1.0000 0.1776 1.8771 r (39.33,42.31) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n22 (net) 1 0.8460 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/D (SDFFARX1_RVT) 0.0956 1.0000 0.0000 1.8771 r (41.17,40.72) 0.7500 (rail VDD) - data arrival time 1.8771 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2791 99.4709 - data required time 99.4709 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4709 - data arrival time -1.8771 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5939 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U12/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (37.48,38.26) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U12/Y (AO22X1_RVT) 0.0946 1.0000 0.1762 1.8757 r (37.04,38.97) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n28 (net) 1 0.7739 - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/D (SDFFARX1_RVT) 0.0946 1.0000 0.0000 1.8757 r (36.31,37.37) 0.7500 (rail VDD) - data arrival time 1.8757 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (37.23,36.61) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2786 99.4714 - data required time 99.4714 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4714 - data arrival time -1.8757 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5957 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U14/A3 (AO22X1_RVT) 0.2332 1.0000 0.0000 1.6994 r (36.11,34.92) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U14/Y (AO22X1_RVT) 0.0945 1.0000 0.1760 1.8754 r (35.67,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n30 (net) 1 0.7607 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/D (SDFFARX1_RVT) 0.0945 1.0000 0.0000 1.8754 r (38.13,35.51) 0.7500 (rail VDD) - data arrival time 1.8754 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (39.06,36.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2785 99.4715 - data required time 99.4715 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4715 - data arrival time -1.8754 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5961 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U10/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (39.05,38.26) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U10/Y (AO22X1_RVT) 0.0936 1.0000 0.1747 1.8741 r (39.49,38.97) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n26 (net) 1 0.6919 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/D (SDFFARX1_RVT) 0.0936 1.0000 0.0000 1.8741 r (41.17,38.85) 0.7500 (rail VDD) - data arrival time 1.8741 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.61) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2781 99.4719 - data required time 99.4719 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4719 - data arrival time -1.8741 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5977 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U27/A3 (AO21X1_RVT) 0.1206 1.0000 0.0000 1.4703 f (22.94,27.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U27/Y (AO21X1_RVT) 0.0654 1.0000 0.1430 1.6133 f (23.37,27.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n27 (net) 2 1.6571 - U0_UART_RX/U0_edge_bit_counter/U25/A2 (AO22X1_RVT) 0.0654 1.0000 0.0000 1.6133 f (25.02,27.05) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U25/Y (AO22X1_RVT) 0.0491 1.0000 0.1655 1.7788 f (24.27,27.22) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n31 (net) 1 0.8143 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/D (SDFFARX1_RVT) 0.0491 1.0000 0.0000 1.7788 f (22.78,28.82) 0.7500 (rail VDD) - data arrival time 1.7788 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (23.70,29.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2983 99.4517 - data required time 99.4518 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4518 - data arrival time -1.7788 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.6730 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.1146 1.0000 0.3752 0.3752 r (32.36,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n28 (net) 5 4.5632 - U0_UART_RX/U0_uart_fsm/U74/A2 (NAND2X0_RVT) 0.1146 1.0000 0.0000 0.3752 r (30.85,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U74/Y (NAND2X0_RVT) 0.1035 1.0000 0.1209 0.4961 f (30.99,30.60) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n44 (net) 2 1.6947 - U0_UART_RX/U0_uart_fsm/U45/A (INVX0_RVT) 0.1035 1.0000 0.0000 0.4961 f (32.52,30.68) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U45/Y (INVX0_RVT) 0.1360 1.0000 0.1397 0.6358 r (32.73,30.63) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n14 (net) 4 3.9816 - U0_UART_RX/U0_uart_fsm/U44/A1 (NAND2X0_RVT) 0.1360 1.0000 0.0000 0.6358 r (37.02,25.80) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U44/Y (NAND2X0_RVT) 0.1191 1.0000 0.1158 0.7516 f (37.03,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n16 (net) 2 1.7340 - U0_UART_RX/U0_uart_fsm/U43/A (INVX0_RVT) 0.1191 1.0000 0.0000 0.7516 f (36.17,25.48) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U43/Y (INVX0_RVT) 0.1187 1.0000 0.1345 0.8861 r (36.38,25.53) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/stp_chk_en (net) 3 3.1127 - U0_UART_RX/U0_uart_fsm/U40/A2 (AND3X1_RVT) 0.1187 1.0000 0.0000 0.8861 r (29.72,23.67) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U40/Y (AND3X1_RVT) 0.0637 1.0000 0.1634 1.0495 r (29.05,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n41 (net) 1 1.2084 - U0_UART_RX/U0_uart_fsm/U39/A4 (AND4X1_RVT) 0.0637 1.0000 0.0000 1.0495 r (18.62,23.98) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U39/Y (AND4X1_RVT) 0.0738 1.0000 0.1887 1.2382 r (17.65,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n38 (net) 1 1.0330 - U0_UART_RX/U0_uart_fsm/U38/A4 (NAND4X0_RVT) 0.0738 1.0000 0.0000 1.2382 r (18.84,20.63) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U38/Y (NAND4X0_RVT) 0.1636 1.0000 0.1630 1.4013 f (19.13,20.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n34 (net) 1 1.5962 - U0_UART_RX/U0_uart_fsm/U37/A2 (NAND2X0_RVT) 0.1636 1.0000 0.0000 1.4013 f (29.18,25.50) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U37/Y (NAND2X0_RVT) 0.1129 1.0000 0.1520 1.5533 r (29.32,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n32 (net) 1 0.7907 - U0_UART_RX/U0_uart_fsm/U36/A5 (AO221X1_RVT) 0.1129 1.0000 0.0000 1.5533 r (29.42,27.32) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U36/Y (AO221X1_RVT) 0.0717 1.0000 0.1731 1.7264 r (28.98,27.22) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/next_state[0] (net) 1 0.7845 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/D (SDFFARX1_RVT) 0.0717 1.0000 0.0000 1.7264 r (28.41,28.82) 0.7500 (rail VDD) - data arrival time 1.7264 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.33,29.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2679 99.4821 - data required time 99.4821 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4821 - data arrival time -1.7264 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.7557 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U28/A1 (AO22X1_RVT) 0.1206 1.0000 0.0000 1.4703 f (22.78,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U28/Y (AO22X1_RVT) 0.0700 1.0000 0.1943 1.6646 f (23.68,30.57) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n32 (net) 1 0.7790 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/D (SDFFARX1_RVT) 0.0700 1.0000 0.0000 1.6646 f (22.78,32.16) 0.7500 (rail VDD) - data arrival time 1.6646 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (23.70,32.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3062 99.4438 - data required time 99.4438 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4438 - data arrival time -1.6646 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.7792 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U34/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (16.71,32.18) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U34/Y (AND2X1_RVT) 0.0493 1.0000 0.1548 1.6251 f (17.38,32.26) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N20 (net) 1 1.1021 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/D (SDFFARX1_RVT) 0.0493 1.0000 0.0000 1.6252 f (19.70,27.34) 0.7500 (rail VDD) - data arrival time 1.6252 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.78,26.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2983 99.4517 - data required time 99.4517 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4517 - data arrival time -1.6252 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8265 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U35/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (19.69,32.18) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U35/Y (AND2X1_RVT) 0.0464 1.0000 0.1509 1.6212 f (19.02,32.26) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N19 (net) 1 0.8163 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/D (SDFFARX1_RVT) 0.0464 1.0000 0.0000 1.6212 f (17.16,30.68) 0.7500 (rail VDD) - data arrival time 1.6212 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.08,29.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2973 99.4527 - data required time 99.4527 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4527 - data arrival time -1.6212 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8314 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U30/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (15.95,42.22) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U30/Y (AND2X1_RVT) 0.0460 1.0000 0.1504 1.6208 f (16.62,42.29) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N24 (net) 1 0.7808 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/D (SDFFARX1_RVT) 0.0460 1.0000 0.0000 1.6208 f (17.61,44.06) 0.7500 (rail VDD) - data arrival time 1.6208 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.53,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2972 99.4528 - data required time 99.4528 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4528 - data arrival time -1.6208 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8320 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U32/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (17.47,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U32/Y (AND2X1_RVT) 0.0460 1.0000 0.1502 1.6207 f (18.14,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N22 (net) 1 0.7729 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/D (SDFFARX1_RVT) 0.0460 1.0000 0.0000 1.6207 f (17.31,37.37) 0.7500 (rail VDD) - data arrival time 1.6207 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.23,36.61) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2972 99.4528 - data required time 99.4528 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4528 - data arrival time -1.6207 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8322 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U31/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (16.25,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U31/Y (AND2X1_RVT) 0.0454 1.0000 0.1494 1.6199 f (16.92,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N23 (net) 1 0.7168 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/D (SDFFARX1_RVT) 0.0454 1.0000 0.0000 1.6199 f (16.70,40.72) 0.7500 (rail VDD) - data arrival time 1.6199 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.62,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2970 99.4530 - data required time 99.4530 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4530 - data arrival time -1.6199 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8332 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U33/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (15.95,34.01) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U33/Y (AND2X1_RVT) 0.0445 1.0000 0.1481 1.6185 f (16.62,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N21 (net) 1 0.6237 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/D (SDFFARX1_RVT) 0.0445 1.0000 0.0000 1.6185 f (17.77,34.03) 0.7500 (rail VDD) - data arrival time 1.6185 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.69,33.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2966 99.4534 - data required time 99.4534 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4534 - data arrival time -1.6185 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8349 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U18/A1 (AND2X1_RVT) 0.0765 1.0000 0.0000 1.2105 r (23.18,20.48) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U18/Y (AND2X1_RVT) 0.0488 1.0000 0.1064 1.3169 r (22.67,20.55) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n21 (net) 1 0.9645 - U0_UART_RX/U0_edge_bit_counter/U17/A3 (NAND4X0_RVT) 0.0488 1.0000 0.0000 1.3169 r (21.12,22.30) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U17/Y (NAND4X0_RVT) 0.2005 1.0000 0.1187 1.4356 f (21.26,22.23) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n19 (net) 1 0.7523 - U0_UART_RX/U0_edge_bit_counter/U16/A2 (NAND2X0_RVT) 0.2005 1.0000 0.0000 1.4356 f (21.88,20.63) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U16/Y (NAND2X0_RVT) 0.1294 1.0000 0.1740 1.6097 r (22.02,20.56) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n29 (net) 1 0.8587 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/D (SDFFARX1_RVT) 0.1294 1.0000 0.0000 1.6097 r (23.39,22.13) 0.7500 (rail VDD) - data arrival time 1.6097 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.31,22.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2947 99.4553 - data required time 99.4553 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4553 - data arrival time -1.6097 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8456 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_uart_fsm/U63/A1 (XNOR2X1_RVT) 0.2178 1.0000 0.0005 0.4466 r (11.60,22.03) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U63/Y (XNOR2X1_RVT) 0.0824 1.0000 0.2745 0.7211 r (12.52,22.24) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n54 (net) 1 0.8104 - U0_UART_RX/U0_uart_fsm/U61/A3 (NAND4X0_RVT) 0.0824 1.0000 0.0000 0.7211 r (12.15,23.82) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U61/Y (NAND4X0_RVT) 0.1407 1.0000 0.1495 0.8706 f (12.29,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n51 (net) 1 1.2683 - U0_UART_RX/U0_uart_fsm/U60/A2 (NOR2X0_RVT) 0.1407 1.0000 0.0000 0.8706 f (17.86,25.38) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U60/Y (NOR2X0_RVT) 0.0789 1.0000 0.2087 1.0794 r (18.59,25.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n20 (net) 3 3.2435 - U0_UART_RX/U0_uart_fsm/U56/A1 (AND4X1_RVT) 0.0789 1.0000 0.0001 1.0794 r (32.52,25.80) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U56/Y (AND4X1_RVT) 0.0884 1.0000 0.1736 1.2531 r (33.03,25.57) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n26 (net) 2 1.9307 - U0_UART_RX/U0_uart_fsm/U34/A1 (AO21X1_RVT) 0.0884 1.0000 0.0000 1.2531 r (35.19,32.34) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U34/Y (AO21X1_RVT) 0.0574 1.0000 0.1477 1.4009 r (35.84,32.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n25 (net) 1 0.7188 - U0_UART_RX/U0_uart_fsm/U33/A2 (AO21X1_RVT) 0.0574 1.0000 0.0000 1.4009 r (35.50,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U33/Y (AO21X1_RVT) 0.0673 1.0000 0.1531 1.5540 r (34.61,30.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/next_state[1] (net) 1 1.3064 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/D (SDFFARX1_RVT) 0.0673 1.0000 0.0000 1.5540 r (28.25,34.03) 0.7500 (rail VDD) - data arrival time 1.5540 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,33.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2659 99.4841 - data required time 99.4841 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4841 - data arrival time -1.5540 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9301 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U21/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (22.73,8.44) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U21/Y (AO222X1_RVT) 0.0910 1.0000 0.2184 1.5198 r (22.30,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n26 (net) 1 1.1262 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/D (SDFFARX1_RVT) 0.0910 1.0000 0.0000 1.5198 r (15.64,7.28) 0.7500 (rail VDD) - data arrival time 1.5198 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (16.56,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2769 99.4731 - data required time 99.4731 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4731 - data arrival time -1.5198 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9533 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U22/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (22.58,10.94) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U22/Y (AO222X1_RVT) 0.0904 1.0000 0.2178 1.5192 r (22.14,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n27 (net) 1 1.0905 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/D (SDFFARX1_RVT) 0.0904 1.0000 0.0000 1.5192 r (16.85,8.76) 0.7500 (rail VDD) - data arrival time 1.5192 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.77,9.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2766 99.4734 - data required time 99.4734 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4734 - data arrival time -1.5192 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9541 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U24/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (28.96,8.44) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U24/Y (AO222X1_RVT) 0.0895 1.0000 0.2170 1.5183 r (28.53,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n29 (net) 1 1.0397 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/D (SDFFARX1_RVT) 0.0895 1.0000 0.0000 1.5184 r (27.80,3.93) 0.7500 (rail VDD) - data arrival time 1.5184 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.72,3.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2762 99.4738 - data required time 99.4738 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4738 - data arrival time -1.5184 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9554 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U19/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3013 r (32.21,10.94) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U19/Y (AO222X1_RVT) 0.0890 1.0000 0.2164 1.5178 r (32.65,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n24 (net) 1 1.0065 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/D (SDFFARX1_RVT) 0.0890 1.0000 0.0000 1.5178 r (34.18,13.96) 0.7500 (rail VDD) - data arrival time 1.5178 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.10,13.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2760 99.4740 - data required time 99.4740 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4740 - data arrival time -1.5178 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9562 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U23/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (25.83,8.44) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U23/Y (AO222X1_RVT) 0.0853 1.0000 0.2123 1.5137 r (26.26,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n28 (net) 1 0.7955 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/D (SDFFARX1_RVT) 0.0853 1.0000 0.0000 1.5137 r (25.52,7.28) 0.7500 (rail VDD) - data arrival time 1.5137 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.44,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2743 99.4757 - data required time 99.4758 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4758 - data arrival time -1.5137 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9621 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U25/A6 (AO222X1_RVT) 0.1556 1.0000 0.0000 1.3013 r (32.06,7.60) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U25/Y (AO222X1_RVT) 0.0841 1.0000 0.2110 1.5123 r (32.50,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n30 (net) 1 0.7277 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/D (SDFFARX1_RVT) 0.0841 1.0000 0.0000 1.5123 r (34.49,7.28) 0.7500 (rail VDD) - data arrival time 1.5123 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.41,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2737 99.4763 - data required time 99.4763 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4763 - data arrival time -1.5123 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9640 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 0.2075 1.0000 0.4391 0.4391 r (21.87,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[2] (net) 7 10.6520 - U0_UART_RX/U0_data_sampling/U50/A (INVX0_RVT) 0.2075 1.0000 0.0002 0.4393 r (9.05,37.36) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.1266 1.0000 0.1194 0.5586 f (8.84,37.32) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n45 (net) 2 2.5379 - U0_UART_RX/U0_data_sampling/U49/A1 (XOR2X1_RVT) 0.1266 1.0000 0.0000 0.5587 f (6.23,40.82) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.0719 1.0000 0.2412 0.7998 r (7.50,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n52 (net) 1 0.7964 - U0_UART_RX/U0_data_sampling/U48/A3 (AND3X1_RVT) 0.0719 1.0000 0.0000 0.7998 r (9.26,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.0549 1.0000 0.1409 0.9407 r (10.08,38.94) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n50 (net) 1 0.7079 - U0_UART_RX/U0_data_sampling/U47/A4 (NAND4X0_RVT) 0.0549 1.0000 0.0000 0.9407 r (11.18,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 0.2413 1.0000 0.2169 1.1577 f (10.88,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n27 (net) 3 3.2599 - U0_UART_RX/U0_data_sampling/U46/S0 (MUX21X1_RVT) 0.2413 1.0000 0.0000 1.1577 f (20.40,39.00) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U46/Y (MUX21X1_RVT) 0.0833 1.0000 0.3131 1.4708 f (21.33,38.96) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n23 (net) 1 0.8555 - U0_UART_RX/U0_data_sampling/Samples_reg_0_/D (SDFFARX1_RVT) 0.0833 1.0000 0.0000 1.4708 f (23.54,40.72) 0.7500 (rail VDD) - data arrival time 1.4708 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.46,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3124 99.4376 - data required time 99.4376 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4376 - data arrival time -1.4708 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9668 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U26/A5 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3013 r (32.06,8.78) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U26/Y (AO222X1_RVT) 0.0862 1.0000 0.1991 1.5004 r (32.65,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n31 (net) 1 0.8489 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/D (SDFFARX1_RVT) 0.0862 1.0000 0.0000 1.5004 r (34.03,10.62) 0.7500 (rail VDD) - data arrival time 1.5004 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (34.95,9.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2747 99.4753 - data required time 99.4753 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4753 - data arrival time -1.5004 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9749 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U20/A2 (AO22X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (23.39,5.71) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U20/Y (AO22X1_RVT) 0.0698 1.0000 0.2064 1.5078 r (24.13,5.53) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n25 (net) 1 1.2997 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/D (SDFFARX1_RVT) 0.0698 1.0000 0.0000 1.5078 r (14.88,3.93) 0.7500 (rail VDD) - data arrival time 1.5078 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (15.80,3.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2671 99.4829 - data required time 99.4829 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4829 - data arrival time -1.5078 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9751 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_par_chk/par_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/Q (SDFFARX1_RVT) 0.1175 1.0000 0.3772 0.3772 r (45.28,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA[2] (net) 4 4.7533 - U0_UART_RX/U0_par_chk/U6/A2 (XNOR2X1_RVT) 0.1175 1.0000 0.0001 0.3772 r (38.78,44.02) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U6/Y (XNOR2X1_RVT) 0.0827 1.0000 0.2716 0.6488 r (37.56,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n6 (net) 1 1.6553 - U0_UART_RX/U0_par_chk/U5/A3 (XNOR3X1_RVT) 0.0827 1.0000 0.0000 0.6488 r (36.43,41.06) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U5/Y (XNOR3X1_RVT) 0.1289 1.0000 0.1783 0.8271 f (37.14,40.62) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n4 (net) 1 1.8228 - U0_UART_RX/U0_par_chk/U3/A2 (XNOR3X1_RVT) 0.1289 1.0000 0.0000 0.8271 f (37.58,32.21) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U3/Y (XNOR3X1_RVT) 0.1264 1.0000 0.4443 1.2715 f (39.88,32.26) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n2 (net) 1 0.9994 - U0_UART_RX/U0_par_chk/U2/A4 (AO22X1_RVT) 0.1264 1.0000 0.0000 1.2715 f (40.83,28.69) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U2/Y (AO22X1_RVT) 0.0490 1.0000 0.1512 1.4227 f (40.24,28.94) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n9 (net) 1 0.7960 - U0_UART_RX/U0_par_chk/par_err_reg/D (SDFFARX1_RVT) 0.0490 1.0000 0.0000 1.4227 f (41.17,30.68) 0.7500 (rail VDD) - data arrival time 1.4227 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,29.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2982 99.4518 - data required time 99.4518 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4518 - data arrival time -1.4227 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.0291 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/parity_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.87,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/Q (SDFFARX1_RVT) 0.0795 1.0000 0.3472 0.3472 r (32.05,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n14 (net) 2 2.1642 - U0_UART_TX/U0_parity_calc/U7/A2 (XNOR2X1_RVT) 0.0795 1.0000 0.0000 0.3472 r (32.73,12.14) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U7/Y (XNOR2X1_RVT) 0.0830 1.0000 0.2515 0.5987 r (33.95,12.21) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n10 (net) 1 1.6747 - U0_UART_TX/U0_parity_calc/U6/A3 (XNOR3X1_RVT) 0.0830 1.0000 0.0000 0.5987 r (33.70,15.10) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U6/Y (XNOR3X1_RVT) 0.1281 1.0000 0.1727 0.7714 f (34.40,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n3 (net) 1 1.4615 - U0_UART_TX/U0_parity_calc/U3/A2 (XNOR3X1_RVT) 0.1281 1.0000 0.0000 0.7714 f (33.93,18.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U3/Y (XNOR3X1_RVT) 0.1265 1.0000 0.4394 1.2108 f (36.23,18.89) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n2 (net) 1 0.7865 - U0_UART_TX/U0_parity_calc/U2/A4 (AO22X1_RVT) 0.1265 1.0000 0.0000 1.2108 f (38.24,18.66) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U2/Y (AO22X1_RVT) 0.0494 1.0000 0.1517 1.3625 f (37.65,18.90) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n27 (net) 1 0.8312 - U0_UART_TX/U0_parity_calc/parity_reg/D (SDFFARX1_RVT) 0.0494 1.0000 0.0000 1.3625 f (35.70,17.31) 0.7500 (rail VDD) - data arrival time 1.3625 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.62,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2984 99.4516 - data required time 99.4516 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4516 - data arrival time -1.3625 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.0891 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U34/A1 (AND2X1_RVT) 0.1093 1.0000 0.0001 0.9462 f (40.12,22.30) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U34/Y (AND2X1_RVT) 0.0581 1.0000 0.1519 1.0980 f (40.63,22.23) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N23 (net) 2 2.0417 - U0_UART_TX/U0_Serializer/U32/A3 (AO21X1_RVT) 0.0581 1.0000 0.0000 1.0980 f (42.70,24.58) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U32/Y (AO21X1_RVT) 0.0512 1.0000 0.1014 1.1994 f (43.13,23.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n21 (net) 1 0.7766 - U0_UART_TX/U0_Serializer/U30/A2 (AO21X1_RVT) 0.0512 1.0000 0.0000 1.1994 f (44.53,22.15) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U30/Y (AO21X1_RVT) 0.0532 1.0000 0.1570 1.3564 f (45.41,22.24) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N25 (net) 1 0.9550 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/D (SDFFARX1_RVT) 0.0532 1.0000 0.0000 1.3564 f (41.17,20.65) 0.7500 (rail VDD) - data arrival time 1.3564 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,19.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2997 99.4503 - data required time 99.4503 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4503 - data arrival time -1.3564 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.0939 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_uart_fsm/U63/A1 (XNOR2X1_RVT) 0.2178 1.0000 0.0005 0.4466 r (11.60,22.03) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U63/Y (XNOR2X1_RVT) 0.0824 1.0000 0.2745 0.7211 r (12.52,22.24) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n54 (net) 1 0.8104 - U0_UART_RX/U0_uart_fsm/U61/A3 (NAND4X0_RVT) 0.0824 1.0000 0.0000 0.7211 r (12.15,23.82) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U61/Y (NAND4X0_RVT) 0.1407 1.0000 0.1495 0.8706 f (12.29,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n51 (net) 1 1.2683 - U0_UART_RX/U0_uart_fsm/U60/A2 (NOR2X0_RVT) 0.1407 1.0000 0.0000 0.8706 f (17.86,25.38) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U60/Y (NOR2X0_RVT) 0.0789 1.0000 0.2087 1.0794 r (18.59,25.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n20 (net) 3 3.2435 - U0_UART_RX/U0_uart_fsm/U30/A2 (NAND3X0_RVT) 0.0789 1.0000 0.0001 1.0794 r (33.74,25.65) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U30/Y (NAND3X0_RVT) 0.0948 1.0000 0.0981 1.1776 f (33.61,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n19 (net) 1 0.5918 - U0_UART_RX/U0_uart_fsm/U29/A2 (NAND2X0_RVT) 0.0948 1.0000 0.0000 1.1776 f (34.65,25.50) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U29/Y (NAND2X0_RVT) 0.0892 1.0000 0.1110 1.2886 r (34.79,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/next_state[2] (net) 1 0.7317 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/D (SDFFARX1_RVT) 0.0892 1.0000 0.0000 1.2886 r (34.79,27.34) 0.7500 (rail VDD) - data arrival time 1.2886 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.71,26.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2761 99.4739 - data required time 99.4739 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4739 - data arrival time -1.2886 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.1853 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U17/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (23.65,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U17/Y (AO22X1_RVT) 0.0727 1.0000 0.2094 1.1295 f (23.06,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n37 (net) 1 1.1030 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/D (SDFFARX1_RVT) 0.0727 1.0000 0.0000 1.1295 f (16.40,10.62) 0.7500 (rail VDD) - data arrival time 1.1295 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.32,9.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3075 99.4425 - data required time 99.4426 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4426 - data arrival time -1.1295 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3131 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U15/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (29.73,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U15/Y (AO22X1_RVT) 0.0718 1.0000 0.2079 1.1279 f (29.14,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n35 (net) 1 1.0007 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/D (SDFFARX1_RVT) 0.0718 1.0000 0.0000 1.1279 f (29.01,20.65) 0.7500 (rail VDD) - data arrival time 1.1279 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.93,19.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3070 99.4430 - data required time 99.4430 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4430 - data arrival time -1.1279 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3151 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_mux/OUT_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U16/A1 (AO22X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.87,13.94) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U16/Y (AO22X1_RVT) 0.0694 1.0000 0.1752 0.8097 f (42.97,13.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/mux_sel[0] (net) 3 2.5610 - U0_UART_TX/U0_mux/U4/A (INVX1_RVT) 0.0694 1.0000 0.0000 0.8097 f (42.79,15.44) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/U4/Y (INVX1_RVT) 0.0585 1.0000 0.0708 0.8805 r (42.66,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/n3 (net) 2 1.7661 - U0_UART_TX/U0_mux/U8/A4 (AO22X1_RVT) 0.0585 1.0000 0.0000 0.8805 r (40.87,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/U8/Y (AO22X1_RVT) 0.0601 1.0000 0.1309 1.0115 r (41.46,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/n4 (net) 1 0.7758 - U0_UART_TX/U0_mux/U6/A2 (AO22X1_RVT) 0.0601 1.0000 0.0000 1.0115 r (44.32,15.74) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/U6/Y (AO22X1_RVT) 0.0623 1.0000 0.1588 1.1703 r (43.58,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/mux_out (net) 1 0.8944 - U0_UART_TX/U0_mux/OUT_reg/D (SDFFARX1_RVT) 0.0623 1.0000 0.0000 1.1703 r (41.17,17.31) 0.7500 (rail VDD) - data arrival time 1.1703 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2640 99.4860 - data required time 99.4860 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4860 - data arrival time -1.1703 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3158 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U21/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (26.23,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U21/Y (AO22X1_RVT) 0.0715 1.0000 0.2072 1.1272 f (25.64,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n41 (net) 1 0.9661 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/D (SDFFARX1_RVT) 0.0715 1.0000 0.0000 1.1272 f (22.02,17.31) 0.7500 (rail VDD) - data arrival time 1.1272 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (22.94,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3069 99.4431 - data required time 99.4431 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4431 - data arrival time -1.1272 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3159 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U19/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (22.13,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U19/Y (AO22X1_RVT) 0.0714 1.0000 0.2070 1.1271 f (21.54,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n39 (net) 1 0.9580 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/D (SDFFARX1_RVT) 0.0714 1.0000 0.0000 1.1271 f (18.07,13.96) 0.7500 (rail VDD) - data arrival time 1.1271 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.99,13.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3069 99.4431 - data required time 99.4431 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4431 - data arrival time -1.1271 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3161 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U23/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (24.71,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U23/Y (AO22X1_RVT) 0.0712 1.0000 0.2064 1.1264 f (24.12,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n43 (net) 1 0.9258 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/D (SDFFARX1_RVT) 0.0712 1.0000 0.0000 1.1264 f (18.83,15.44) 0.7500 (rail VDD) - data arrival time 1.1264 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.75,16.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3067 99.4433 - data required time 99.4433 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4433 - data arrival time -1.1264 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3169 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U11/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (30.79,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U11/Y (AO22X1_RVT) 0.0707 1.0000 0.2052 1.1252 f (30.20,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n31 (net) 1 0.8646 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/D (SDFFARX1_RVT) 0.0707 1.0000 0.0000 1.1252 f (27.95,13.96) 0.7500 (rail VDD) - data arrival time 1.1252 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.87,13.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3065 99.4435 - data required time 99.4435 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4435 - data arrival time -1.1252 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3183 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U13/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (28.21,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U13/Y (AO22X1_RVT) 0.0700 1.0000 0.2034 1.1234 f (27.62,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n33 (net) 1 0.7749 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/D (SDFFARX1_RVT) 0.0700 1.0000 0.0000 1.1234 f (28.25,17.31) 0.7500 (rail VDD) - data arrival time 1.1234 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3062 99.4438 - data required time 99.4438 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4438 - data arrival time -1.1234 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3204 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U9/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (26.54,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U9/Y (AO22X1_RVT) 0.0694 1.0000 0.2021 1.1221 f (25.95,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n29 (net) 1 0.7065 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/D (SDFFARX1_RVT) 0.0694 1.0000 0.0000 1.1221 f (25.67,10.62) 0.7500 (rail VDD) - data arrival time 1.1221 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.59,9.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3059 99.4441 - data required time 99.4441 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4441 - data arrival time -1.1221 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3220 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U34/A1 (AND2X1_RVT) 0.1093 1.0000 0.0001 0.9462 f (40.12,22.30) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U34/Y (AND2X1_RVT) 0.0581 1.0000 0.1519 1.0980 f (40.63,22.23) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N23 (net) 2 2.0417 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/D (SDFFARX1_RVT) 0.0581 1.0000 0.0000 1.0981 f (35.40,20.65) 0.7500 (rail VDD) - data arrival time 1.0981 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.32,19.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3014 99.4486 - data required time 99.4486 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4486 - data arrival time -1.0981 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3506 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_stp_chk/stp_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0931 1.0000 0.3359 0.3359 f (32.36,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n28 (net) 5 4.4847 - U0_UART_RX/U0_uart_fsm/U74/A2 (NAND2X0_RVT) 0.0931 1.0000 0.0000 0.3359 f (30.85,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U74/Y (NAND2X0_RVT) 0.1332 1.0000 0.1397 0.4756 r (30.99,30.60) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n44 (net) 2 1.7193 - U0_UART_RX/U0_uart_fsm/U45/A (INVX0_RVT) 0.1332 1.0000 0.0000 0.4756 r (32.52,30.68) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U45/Y (INVX0_RVT) 0.1161 1.0000 0.1232 0.5988 f (32.73,30.63) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n14 (net) 4 3.8766 - U0_UART_RX/U0_uart_fsm/U44/A1 (NAND2X0_RVT) 0.1161 1.0000 0.0000 0.5988 f (37.02,25.80) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U44/Y (NAND2X0_RVT) 0.1330 1.0000 0.1504 0.7492 r (37.03,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n16 (net) 2 1.7542 - U0_UART_RX/U0_uart_fsm/U43/A (INVX0_RVT) 0.1330 1.0000 0.0000 0.7492 r (36.17,25.48) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U43/Y (INVX0_RVT) 0.1044 1.0000 0.1090 0.8582 f (36.38,25.53) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/stp_chk_en (net) 3 3.0486 - U0_UART_RX/U0_stp_chk/U3/A (INVX1_RVT) 0.1044 1.0000 0.0000 0.8583 f (38.14,25.47) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/U3/Y (INVX1_RVT) 0.0616 1.0000 0.0715 0.9298 r (38.28,25.58) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/n1 (net) 1 0.7590 - U0_UART_RX/U0_stp_chk/U2/A2 (OAI22X1_RVT) 0.0616 1.0000 0.0000 0.9298 r (39.36,26.25) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/U2/Y (OAI22X1_RVT) 0.0367 1.0000 0.1615 1.0913 f (40.50,25.54) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/n4 (net) 1 0.7608 - U0_UART_RX/U0_stp_chk/stp_err_reg/D (SDFFARX1_RVT) 0.0367 1.0000 0.0000 1.0913 f (40.87,27.34) 0.7500 (rail VDD) - data arrival time 1.0913 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_stp_chk/stp_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.79,26.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2940 99.4560 - data required time 99.4560 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4560 - data arrival time -1.0913 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3647 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U33/A1 (AND2X1_RVT) 0.1093 1.0000 0.0001 0.9462 f (41.42,23.82) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U33/Y (AND2X1_RVT) 0.0455 1.0000 0.1382 1.0844 f (40.91,23.90) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N24 (net) 1 0.8874 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/D (SDFFARX1_RVT) 0.0455 1.0000 0.0000 1.0844 f (36.16,24.00) 0.7500 (rail VDD) - data arrival time 1.0844 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (37.08,23.24) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2970 99.4530 - data required time 99.4530 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4530 - data arrival time -1.0844 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3686 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U11/A1 (OA21X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (44.31,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U11/Y (OA21X1_RVT) 0.0552 1.0000 0.1586 0.9062 f (43.33,10.55) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/next_state[1] (net) 1 0.9738 - U0_UART_TX/U0_fsm/current_state_reg_1_/D (SDFFARX1_RVT) 0.0552 1.0000 0.0000 0.9062 f (41.17,7.28) 0.7500 (rail VDD) - data arrival time 0.9062 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3004 99.4496 - data required time 99.4496 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4496 - data arrival time -0.9062 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.5434 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/sampled_bit_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/Q (SDFFARX1_RVT) 0.0949 1.0000 0.3600 0.3600 r (38.89,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n1 (net) 3 3.2333 - U0_UART_RX/U0_uart_fsm/U79/A3 (AO21X1_RVT) 0.0949 1.0000 0.0000 0.3601 r (28.50,31.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U79/Y (AO21X1_RVT) 0.0889 1.0000 0.1329 0.4930 r (28.08,30.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n48 (net) 3 2.6978 - U0_UART_RX/U0_uart_fsm/U78/A2 (NAND2X0_RVT) 0.0889 1.0000 0.0000 0.4930 r (27.66,32.18) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U78/Y (NAND2X0_RVT) 0.2096 1.0000 0.1849 0.6779 f (27.80,32.25) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/dat_samp_en (net) 5 4.6254 - U0_UART_RX/U0_data_sampling/U62/A1 (AND2X1_RVT) 0.2096 1.0000 0.0001 0.6779 f (29.63,39.02) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U62/Y (AND2X1_RVT) 0.0588 1.0000 0.1831 0.8611 f (30.15,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/N58 (net) 1 0.6270 - U0_UART_RX/U0_data_sampling/sampled_bit_reg/D (SDFFARX1_RVT) 0.0588 1.0000 0.0000 0.8611 f (31.29,38.85) 0.7500 (rail VDD) - data arrival time 0.8611 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_data_sampling/sampled_bit_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (32.22,39.61) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3016 99.4484 - data required time 99.4484 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4484 - data arrival time -0.8611 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.5873 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_0_/Q (SDFFARX1_RVT) 0.0908 1.0000 0.3566 0.3566 r (39.50,20.55) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count[0] (net) 3 2.9485 - U0_UART_TX/U0_Serializer/U18/A2 (AND3X1_RVT) 0.0908 1.0000 0.0000 0.3567 r (42.03,22.46) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U18/Y (AND3X1_RVT) 0.0666 1.0000 0.1573 0.5140 r (41.37,22.22) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_done (net) 1 1.5158 - U0_UART_TX/U0_fsm/U8/A (INVX1_RVT) 0.0666 1.0000 0.0000 0.5140 r (39.66,15.44) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U8/Y (INVX1_RVT) 0.0606 1.0000 0.0635 0.5775 f (39.80,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n6 (net) 3 2.7404 - U0_UART_TX/U0_fsm/U10/A2 (OA21X1_RVT) 0.0606 1.0000 0.0000 0.5775 f (39.36,13.19) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U10/Y (OA21X1_RVT) 0.0553 1.0000 0.1414 0.7189 f (40.19,13.90) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n10 (net) 1 0.9833 - U0_UART_TX/U0_fsm/U9/A3 (NOR3X0_RVT) 0.0553 1.0000 0.0000 0.7189 f (41.02,12.01) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U9/Y (NOR3X0_RVT) 0.0452 1.0000 0.1770 0.8959 r (40.30,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/next_state[2] (net) 1 0.9437 - U0_UART_TX/U0_fsm/current_state_reg_2_/D (SDFFARX1_RVT) 0.0452 1.0000 0.0000 0.8959 r (35.09,12.10) 0.7500 (rail VDD) - data arrival time 0.8959 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.01,12.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2601 99.4899 - data required time 99.4899 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4899 - data arrival time -0.8959 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.5939 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_0_/Q (SDFFARX1_RVT) 0.0908 1.0000 0.3566 0.3566 r (39.50,20.55) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count[0] (net) 3 2.9485 - U0_UART_TX/U0_Serializer/U18/A2 (AND3X1_RVT) 0.0908 1.0000 0.0000 0.3567 r (42.03,22.46) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U18/Y (AND3X1_RVT) 0.0666 1.0000 0.1573 0.5140 r (41.37,22.22) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_done (net) 1 1.5158 - U0_UART_TX/U0_fsm/U8/A (INVX1_RVT) 0.0666 1.0000 0.0000 0.5140 r (39.66,15.44) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U8/Y (INVX1_RVT) 0.0606 1.0000 0.0635 0.5775 f (39.80,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n6 (net) 3 2.7404 - U0_UART_TX/U0_fsm/U13/A2 (AO22X1_RVT) 0.0606 1.0000 0.0000 0.5775 f (39.76,9.05) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U13/Y (AO22X1_RVT) 0.0485 1.0000 0.1617 0.7392 f (39.02,8.87) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n13 (net) 1 0.7607 - U0_UART_TX/U0_fsm/U12/A1 (AND2X1_RVT) 0.0485 1.0000 0.0000 0.7392 f (40.73,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U12/Y (AND2X1_RVT) 0.0482 1.0000 0.1031 0.8423 f (41.24,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/next_state[0] (net) 1 0.9643 - U0_UART_TX/U0_fsm/current_state_reg_0_/D (SDFFARX1_RVT) 0.0482 1.0000 0.0000 0.8423 f (41.17,3.93) 0.7500 (rail VDD) - data arrival time 0.8423 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,3.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2979 99.4521 - data required time 99.4521 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4521 - data arrival time -0.8423 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.6097 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_strt_chk/strt_glitch_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/Q (SDFFARX1_RVT) 0.0949 1.0000 0.3600 0.3600 r (38.89,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n1 (net) 3 3.2333 - U0_UART_RX/U0_uart_fsm/U79/A3 (AO21X1_RVT) 0.0949 1.0000 0.0000 0.3601 r (28.50,31.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U79/Y (AO21X1_RVT) 0.0889 1.0000 0.1329 0.4930 r (28.08,30.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n48 (net) 3 2.6978 - U0_UART_RX/U0_uart_fsm/U55/A2 (OR2X1_RVT) 0.0889 1.0000 0.0000 0.4930 r (31.25,32.15) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U55/Y (OR2X1_RVT) 0.0625 1.0000 0.1241 0.6171 r (31.67,32.30) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n13 (net) 2 1.7359 - U0_UART_RX/U0_uart_fsm/U27/A (INVX0_RVT) 0.0625 1.0000 0.0000 0.6171 r (33.74,34.02) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U27/Y (INVX0_RVT) 0.0563 1.0000 0.0614 0.6785 f (33.95,33.97) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/strt_chk_en (net) 2 1.6902 - U0_UART_RX/U0_strt_chk/U2/A2 (AO22X1_RVT) 0.0563 1.0000 0.0000 0.6785 f (34.90,35.80) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/U2/Y (AO22X1_RVT) 0.0500 1.0000 0.1611 0.8396 f (34.15,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/n3 (net) 1 0.8945 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/D (SDFFARX1_RVT) 0.0500 1.0000 0.0000 0.8396 f (29.32,35.51) 0.7500 (rail VDD) - data arrival time 0.8396 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.24,36.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2986 99.4514 - data required time 99.4514 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4514 - data arrival time -0.8396 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.6119 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0524 1.0000 0.2941 0.2941 f (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.7792 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0524 1.0000 0.0000 0.2941 f (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0734 1.0000 0.1304 0.4245 f (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3467 - U0_UART_TX/U0_fsm/U17/A3 (AO21X1_RVT) 0.0734 1.0000 0.0000 0.4245 f (42.19,8.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U17/Y (AO21X1_RVT) 0.0535 1.0000 0.1117 0.5362 f (41.76,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_c (net) 1 0.9834 - U0_UART_TX/U0_fsm/busy_reg/D (SDFFARX1_RVT) 0.0535 1.0000 0.0000 0.5362 f (39.76,5.41) 0.7500 (rail VDD) - data arrival time 0.5362 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (38.84,6.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2998 99.4502 - data required time 99.4502 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4502 - data arrival time -0.5362 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.9140 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.33,29.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/Q (SDFFARX1_RVT) 0.0955 1.0000 0.3605 0.3605 r (32.51,28.93) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n2 (net) 4 3.2740 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/SI (SDFFARX1_RVT) 0.0955 1.0000 0.0000 0.3605 r (35.10,26.75) 0.7500 (rail VDD) - data arrival time 0.3605 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.71,26.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2849 99.4651 - data required time 99.4651 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4651 - data arrival time -0.3605 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1045 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.01,12.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_2_/Q (SDFFARX1_RVT) 0.0910 1.0000 0.3567 0.3567 r (39.20,12.21) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/dftopt2 (net) 3 2.9593 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/SI (SDFFARX1_RVT) 0.0910 1.0000 0.0000 0.3568 r (34.34,10.03) 0.7500 (rail VDD) - data arrival time 0.3568 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (34.95,9.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2831 99.4669 - data required time 99.4669 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4669 - data arrival time -0.3568 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1102 - - - - Startpoint: U0_UART_TX/U0_mux/OUT_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/parity_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/OUT_reg/Q (SDFFARX1_RVT) 0.0890 1.0000 0.3551 0.3551 r (45.28,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/OUT (net) 2 2.8265 - U0_UART_TX/U0_parity_calc/parity_reg/SI (SDFFARX1_RVT) 0.0890 1.0000 0.0000 0.3552 r (36.02,16.72) 0.7500 (rail VDD) - data arrival time 0.3552 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.62,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2823 99.4677 - data required time 99.4677 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4677 - data arrival time -0.3552 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1125 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/Q (SDFFARX1_RVT) 0.0786 1.0000 0.3465 0.3465 r (32.36,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n1 (net) 2 2.1027 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/SI (SDFFARX1_RVT) 0.0786 1.0000 0.0000 0.3465 r (22.34,16.72) 0.7500 (rail VDD) - data arrival time 0.3465 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (22.94,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2781 99.4719 - data required time 99.4719 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4719 - data arrival time -0.3465 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1255 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.99,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/Q (SDFFARX1_RVT) 0.0773 1.0000 0.3454 0.3454 r (22.17,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n6 (net) 2 2.0150 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/SI (SDFFARX1_RVT) 0.0773 1.0000 0.0000 0.3454 r (16.71,10.03) 0.7500 (rail VDD) - data arrival time 0.3454 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.32,9.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2775 99.4725 - data required time 99.4725 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4725 - data arrival time -0.3454 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1270 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.32,9.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/Q (SDFFARX1_RVT) 0.0757 1.0000 0.3439 0.3439 r (20.50,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/dftopt1 (net) 2 1.9034 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/SI (SDFFARX1_RVT) 0.0757 1.0000 0.0000 0.3439 r (17.17,9.35) 0.7500 (rail VDD) - data arrival time 0.3439 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.77,9.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2769 99.4731 - data required time 99.4731 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4731 - data arrival time -0.3439 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1292 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (22.94,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/Q (SDFFARX1_RVT) 0.0753 1.0000 0.3434 0.3434 r (26.12,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n12 (net) 2 1.8732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/SI (SDFFARX1_RVT) 0.0753 1.0000 0.0000 0.3435 r (19.14,16.03) 0.7500 (rail VDD) - data arrival time 0.3435 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.75,16.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2767 99.4733 - data required time 99.4733 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4733 - data arrival time -0.3435 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1298 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.75,16.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/Q (SDFFARX1_RVT) 0.0745 1.0000 0.3427 0.3427 r (22.93,15.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n11 (net) 2 1.8173 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/SI (SDFFARX1_RVT) 0.0745 1.0000 0.0000 0.3427 r (18.38,13.37) 0.7500 (rail VDD) - data arrival time 0.3427 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.99,13.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2764 99.4736 - data required time 99.4736 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4736 - data arrival time -0.3427 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1309 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (26.59,9.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/Q (SDFFARX1_RVT) 0.0739 1.0000 0.3420 0.3420 r (29.77,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n7 (net) 2 1.7718 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/SI (SDFFARX1_RVT) 0.0739 1.0000 0.0000 0.3420 r (28.26,13.37) 0.7500 (rail VDD) - data arrival time 0.3420 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.87,13.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2762 99.4738 - data required time 99.4738 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4738 - data arrival time -0.3420 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1318 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/QN (SDFFARX1_RVT) 0.1168 1.0000 0.2394 0.2394 f (45.49,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n7 (net) 4 3.6771 - U0_UART_TX/U0_fsm/current_state_reg_0_/SI (SDFFARX1_RVT) 0.1168 1.0000 0.0000 0.2394 f (41.49,3.34) 0.7500 (rail VDD) - data arrival time 0.2394 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,3.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3248 99.4252 - data required time 99.4252 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4252 - data arrival time -0.2394 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1858 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (23.70,29.58) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/QN (SDFFARX1_RVT) 0.1140 1.0000 0.2364 0.2364 f (27.10,28.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/dftopt7 (net) 4 3.4747 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/SI (SDFFARX1_RVT) 0.1140 1.0000 0.0000 0.2364 f (28.57,33.44) 0.7500 (rail VDD) - data arrival time 0.2364 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,33.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3236 99.4264 - data required time 99.4264 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4264 - data arrival time -0.2364 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1899 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_stp_chk/stp_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/QN (SDFFARX1_RVT) 0.1128 1.0000 0.2351 0.2351 f (39.11,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/test_so (net) 4 3.3892 - U0_UART_RX/U0_stp_chk/stp_err_reg/SI (SDFFARX1_RVT) 0.1128 1.0000 0.0000 0.2351 f (41.18,26.75) 0.7500 (rail VDD) - data arrival time 0.2351 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_stp_chk/stp_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.79,26.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3232 99.4268 - data required time 99.4268 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4268 - data arrival time -0.2351 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1917 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (37.08,23.24) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_1_/QN (SDFFARX1_RVT) 0.1125 1.0000 0.2348 0.2348 f (40.47,23.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n13 (net) 3 3.3672 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/SI (SDFFARX1_RVT) 0.1125 1.0000 0.0000 0.2348 f (35.71,20.06) 0.7500 (rail VDD) - data arrival time 0.2348 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.32,19.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3230 99.4270 - data required time 99.4270 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4270 - data arrival time -0.2348 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1922 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (23.70,32.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/QN (SDFFARX1_RVT) 0.1099 1.0000 0.2321 0.2321 f (27.10,32.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/dftopt8 (net) 3 3.1848 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/SI (SDFFARX1_RVT) 0.1099 1.0000 0.0000 0.2321 f (28.72,29.41) 0.7500 (rail VDD) - data arrival time 0.2321 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.33,29.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3220 99.4280 - data required time 99.4280 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4280 - data arrival time -0.2321 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1959 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.31,22.89) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/QN (SDFFARX1_RVT) 0.1043 1.0000 0.2260 0.2260 f (27.71,22.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n14 (net) 3 2.7807 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/SI (SDFFARX1_RVT) 0.1043 1.0000 0.0000 0.2260 f (24.31,23.41) 0.7500 (rail VDD) - data arrival time 0.2260 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.92,23.24) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3197 99.4303 - data required time 99.4303 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4303 - data arrival time -0.2260 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2042 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (15.80,3.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/QN (SDFFARX1_RVT) 0.1027 1.0000 0.2242 0.2242 f (19.19,3.82) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt10 (net) 1 2.6620 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/SI (SDFFARX1_RVT) 0.1027 1.0000 0.0001 0.2243 f (19.38,26.75) 0.7500 (rail VDD) - data arrival time 0.2243 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.78,26.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3198 99.4302 - data required time 99.4303 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4303 - data arrival time -0.2243 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2059 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,3.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_0_/QN (SDFFARX1_RVT) 0.1030 1.0000 0.2246 0.2246 f (45.49,3.82) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n8 (net) 3 2.6857 - U0_UART_TX/U0_fsm/busy_reg/SI (SDFFARX1_RVT) 0.1030 1.0000 0.0000 0.2246 f (39.45,6.00) 0.7500 (rail VDD) - data arrival time 0.2246 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (38.84,6.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3192 99.4308 - data required time 99.4308 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4308 - data arrival time -0.2246 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2062 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.78,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/QN (SDFFARX1_RVT) 0.1022 1.0000 0.2238 0.2238 f (15.38,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n2 (net) 2 2.6308 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/SI (SDFFARX1_RVT) 0.1022 1.0000 0.0000 0.2238 f (17.47,30.09) 0.7500 (rail VDD) - data arrival time 0.2238 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.08,29.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3189 99.4311 - data required time 99.4311 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4311 - data arrival time -0.2238 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2073 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_strt_chk/strt_glitch_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/QN (SDFFARX1_RVT) 0.0915 1.0000 0.2121 0.2121 f (32.57,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/dftopt0 (net) 2 1.8759 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/SI (SDFFARX1_RVT) 0.0915 1.0000 0.0000 0.2121 f (29.63,36.10) 0.7500 (rail VDD) - data arrival time 0.2121 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.24,36.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3145 99.4355 - data required time 99.4355 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4355 - data arrival time -0.2121 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2234 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_mux/OUT_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_2_/QN (SDFFARX1_RVT) 0.0909 1.0000 0.2114 0.2114 f (45.49,20.54) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt5 (net) 2 1.8411 - U0_UART_TX/U0_mux/OUT_reg/SI (SDFFARX1_RVT) 0.0909 1.0000 0.0000 0.2114 f (41.49,16.72) 0.7500 (rail VDD) - data arrival time 0.2114 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3143 99.4357 - data required time 99.4357 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4357 - data arrival time -0.2114 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2243 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.08,29.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/QN (SDFFARX1_RVT) 0.0904 1.0000 0.2107 0.2107 f (21.48,30.57) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n1 (net) 2 1.8051 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/SI (SDFFARX1_RVT) 0.0904 1.0000 0.0000 0.2107 f (23.10,29.41) 0.7500 (rail VDD) - data arrival time 0.2107 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (23.70,29.58) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3141 99.4359 - data required time 99.4359 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4359 - data arrival time -0.2107 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2252 - - - - Startpoint: U0_UART_RX/U0_data_sampling/Samples_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.46,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/Samples_reg_0_/QN (SDFFARX1_RVT) 0.0879 1.0000 0.2078 0.2078 f (27.86,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n55 (net) 2 1.6462 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/SI (SDFFARX1_RVT) 0.0879 1.0000 0.0000 0.2078 f (24.46,43.47) 0.7500 (rail VDD) - data arrival time 0.2078 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (25.07,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3131 99.4369 - data required time 99.4369 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4369 - data arrival time -0.2078 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2291 - - - - Startpoint: U0_UART_RX/U0_par_chk/par_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,29.92) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/par_err_reg/QN (SDFFARX1_RVT) 0.0877 1.0000 0.2076 0.2076 f (45.49,30.57) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/test_so (net) 1 1.6360 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/SI (SDFFARX1_RVT) 0.0877 1.0000 0.0000 0.2076 f (36.47,23.41) 0.7500 (rail VDD) - data arrival time 0.2076 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (37.08,23.24) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3130 99.4370 - data required time 99.4370 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4370 - data arrival time -0.2076 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2293 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_0_/QN (SDFFARX1_RVT) 0.0871 1.0000 0.2068 0.2068 f (39.72,20.54) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n14 (net) 2 1.5926 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/SI (SDFFARX1_RVT) 0.0871 1.0000 0.0000 0.2068 f (41.49,20.06) 0.7500 (rail VDD) - data arrival time 0.2068 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,19.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3127 99.4373 - data required time 99.4373 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4373 - data arrival time -0.2068 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2305 - - - - Startpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (25.07,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/Samples_reg_1_/QN (SDFFARX1_RVT) 0.0850 1.0000 0.2044 0.2044 f (28.47,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/dftopt1 (net) 2 1.4616 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/SI (SDFFARX1_RVT) 0.0850 1.0000 0.0000 0.2044 f (29.94,43.47) 0.7500 (rail VDD) - data arrival time 0.2044 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.54,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3119 99.4381 - data required time 99.4381 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4381 - data arrival time -0.2044 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2337 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.93,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/QN (SDFFARX1_RVT) 0.0837 1.0000 0.2028 0.2028 f (33.33,20.54) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/dftopt0 (net) 1 1.3767 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/SI (SDFFARX1_RVT) 0.0837 1.0000 0.0000 0.2028 f (23.70,22.72) 0.7500 (rail VDD) - data arrival time 0.2028 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.31,22.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3114 99.4386 - data required time 99.4386 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4386 - data arrival time -0.2028 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2358 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.87,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/QN (SDFFARX1_RVT) 0.0823 1.0000 0.2011 0.2011 f (32.27,13.85) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n28 (net) 1 1.2868 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/SI (SDFFARX1_RVT) 0.0823 1.0000 0.0000 0.2011 f (29.33,20.06) 0.7500 (rail VDD) - data arrival time 0.2011 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.93,19.89) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3108 99.4392 - data required time 99.4392 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4392 - data arrival time -0.2011 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2381 - - - - Startpoint: U0_UART_TX/U0_parity_calc/parity_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.62,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/parity_reg/QN (SDFFARX1_RVT) 0.0822 1.0000 0.2011 0.2011 f (40.02,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/test_so (net) 1 1.2843 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/SI (SDFFARX1_RVT) 0.0822 1.0000 0.0000 0.2011 f (34.50,13.37) 0.7500 (rail VDD) - data arrival time 0.2011 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.10,13.20) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3108 99.4392 - data required time 99.4392 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4392 - data arrival time -0.2011 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2381 - - - - Startpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.01,36.27) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/Samples_reg_2_/QN (SDFFARX1_RVT) 0.0821 1.0000 0.2010 0.2010 f (27.40,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/dftopt4 (net) 1 1.2783 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/SI (SDFFARX1_RVT) 0.0821 1.0000 0.0000 0.2010 f (17.62,36.78) 0.7500 (rail VDD) - data arrival time 0.2010 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.23,36.61) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3107 99.4393 - data required time 99.4393 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4393 - data arrival time -0.2010 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2383 - - - - Startpoint: U0_UART_RX/U0_strt_chk/strt_glitch_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (30.24,36.27) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/strt_glitch_reg/QN (SDFFARX1_RVT) 0.0817 1.0000 0.2004 0.2004 f (33.63,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/test_so (net) 1 1.2506 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/SI (SDFFARX1_RVT) 0.0817 1.0000 0.0000 0.2005 f (23.40,36.10) 0.7500 (rail VDD) - data arrival time 0.2005 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.01,36.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3106 99.4394 - data required time 99.4394 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4394 - data arrival time -0.2005 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2390 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/QN (SDFFARX1_RVT) 0.0816 1.0000 0.2004 0.2004 f (45.49,38.96) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n48 (net) 1 1.2461 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/SI (SDFFARX1_RVT) 0.0816 1.0000 0.0000 0.2004 f (38.45,36.10) 0.7500 (rail VDD) - data arrival time 0.2004 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (39.06,36.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3105 99.4395 - data required time 99.4395 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4395 - data arrival time -0.2004 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2391 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/QN (SDFFARX1_RVT) 0.0809 1.0000 0.1996 0.1996 f (35.44,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/dftopt1 (net) 1 1.2035 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/SI (SDFFARX1_RVT) 0.0809 1.0000 0.0000 0.1996 f (28.11,3.34) 0.7500 (rail VDD) - data arrival time 0.1996 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.72,3.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3103 99.4397 - data required time 99.4397 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4397 - data arrival time -0.1996 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2402 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.72,3.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/QN (SDFFARX1_RVT) 0.0804 1.0000 0.1989 0.1989 f (32.12,3.82) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n37 (net) 1 1.1695 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/SI (SDFFARX1_RVT) 0.0804 1.0000 0.0000 0.1990 f (25.83,6.69) 0.7500 (rail VDD) - data arrival time 0.1990 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.44,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3101 99.4399 - data required time 99.4400 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4400 - data arrival time -0.1990 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2410 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.92,23.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/QN (SDFFARX1_RVT) 0.0801 1.0000 0.1985 0.1985 f (28.32,23.89) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/dftopt1 (net) 1 1.1465 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/SI (SDFFARX1_RVT) 0.0801 1.0000 0.0000 0.1985 f (28.57,16.72) 0.7500 (rail VDD) - data arrival time 0.1985 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,16.55) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3099 99.4401 - data required time 99.4401 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4401 - data arrival time -0.1985 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2416 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (16.56,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/QN (SDFFARX1_RVT) 0.0798 1.0000 0.1982 0.1982 f (19.95,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n34 (net) 1 1.1278 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/SI (SDFFARX1_RVT) 0.0798 1.0000 0.0000 0.1982 f (15.19,3.34) 0.7500 (rail VDD) - data arrival time 0.1982 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (15.80,3.17) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3098 99.4402 - data required time 99.4402 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4402 - data arrival time -0.1982 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2420 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.53,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/QN (SDFFARX1_RVT) 0.0797 1.0000 0.1981 0.1981 f (21.93,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/test_so_gOb3 (net) 1 1.1261 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/SI (SDFFARX1_RVT) 0.0797 1.0000 0.0000 0.1982 f (17.02,40.13) 0.7500 (rail VDD) - data arrival time 0.1982 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.62,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3098 99.4402 - data required time 99.4402 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4402 - data arrival time -0.1982 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2421 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/QN (SDFFARX1_RVT) 0.0794 1.0000 0.1978 0.1978 f (45.49,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n49 (net) 1 1.1074 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/SI (SDFFARX1_RVT) 0.0794 1.0000 0.0000 0.1978 f (41.49,40.13) 0.7500 (rail VDD) - data arrival time 0.1978 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3097 99.4403 - data required time 99.4404 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4404 - data arrival time -0.1978 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2425 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (30.54,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/QN (SDFFARX1_RVT) 0.0793 1.0000 0.1976 0.1976 f (33.94,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n51 (net) 1 1.1000 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/SI (SDFFARX1_RVT) 0.0793 1.0000 0.0000 0.1977 f (29.48,40.13) 0.7500 (rail VDD) - data arrival time 0.1977 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.09,39.96) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3096 99.4404 - data required time 99.4404 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4404 - data arrival time -0.1977 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2427 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (37.23,36.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/QN (SDFFARX1_RVT) 0.0792 1.0000 0.1975 0.1975 f (40.63,37.26) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n47 (net) 1 1.0938 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/SI (SDFFARX1_RVT) 0.0792 1.0000 0.0000 0.1975 f (41.49,43.47) 0.7500 (rail VDD) - data arrival time 0.1975 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,43.30) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3096 99.4404 - data required time 99.4404 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4404 - data arrival time -0.1975 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2429 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.23,36.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/QN (SDFFARX1_RVT) 0.0790 1.0000 0.1973 0.1973 f (21.63,37.26) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n53 (net) 1 1.0812 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/SI (SDFFARX1_RVT) 0.0790 1.0000 0.0000 0.1973 f (18.08,33.44) 0.7500 (rail VDD) - data arrival time 0.1973 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.69,33.27) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3095 99.4405 - data required time 99.4405 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4405 - data arrival time -0.1973 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2432 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (34.95,9.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/QN (SDFFARX1_RVT) 0.0790 1.0000 0.1973 0.1973 f (38.35,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n39 (net) 1 1.0812 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/SI (SDFFARX1_RVT) 0.0790 1.0000 0.0000 0.1973 f (34.80,6.69) 0.7500 (rail VDD) - data arrival time 0.1973 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.41,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3095 99.4405 - data required time 99.4405 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4405 - data arrival time -0.1973 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2432 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.77,9.52) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/QN (SDFFARX1_RVT) 0.0790 1.0000 0.1972 0.1972 f (21.17,8.87) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n35 (net) 1 1.0784 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/SI (SDFFARX1_RVT) 0.0790 1.0000 0.0000 0.1973 f (15.95,6.69) 0.7500 (rail VDD) - data arrival time 0.1973 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (16.56,6.52) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3095 99.4405 - data required time 99.4405 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4405 - data arrival time -0.1973 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2433 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (26.44,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/QN (SDFFARX1_RVT) 0.0782 1.0000 0.1963 0.1963 f (29.83,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt8 (net) 1 1.0267 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/SI (SDFFARX1_RVT) 0.0782 1.0000 0.0000 0.1963 f (25.98,10.03) 0.7500 (rail VDD) - data arrival time 0.1963 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.59,9.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3091 99.4409 - data required time 99.4409 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4409 - data arrival time -0.1963 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2446 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_par_chk/par_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (41.94,32.92) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/QN (SDFFARX1_RVT) 0.0770 1.0000 0.1948 0.1948 f (45.34,32.27) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/test_so (net) 1 0.9558 - U0_UART_RX/U0_par_chk/par_err_reg/SI (SDFFARX1_RVT) 0.0770 1.0000 0.0000 0.1948 f (41.49,30.09) 0.7500 (rail VDD) - data arrival time 0.1948 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,29.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3087 99.4413 - data required time 99.4413 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4413 - data arrival time -0.1948 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2465 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/QN (SDFFARX1_RVT) 0.0760 1.0000 0.1934 0.1934 f (45.49,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n50 (net) 1 0.8931 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/SI (SDFFARX1_RVT) 0.0760 1.0000 0.0000 0.1934 f (41.49,39.44) 0.7500 (rail VDD) - data arrival time 0.1934 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.61) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3083 99.4417 - data required time 99.4417 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4417 - data arrival time -0.1934 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2483 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (39.06,36.27) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/QN (SDFFARX1_RVT) 0.0760 1.0000 0.1933 0.1933 f (42.45,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n46 (net) 1 0.8900 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/SI (SDFFARX1_RVT) 0.0760 1.0000 0.0000 0.1933 f (41.34,32.75) 0.7500 (rail VDD) - data arrival time 0.1933 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.94,32.92) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3083 99.4417 - data required time 99.4418 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4418 - data arrival time -0.1933 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2484 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - clock network delay (ideal) 0.0000 0.0000 - - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.10,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/QN (SDFFARX1_RVT) 0.0757 1.0000 0.1930 0.1930 f (38.50,13.85) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt0 (net) 1 0.8740 - U0_UART_TX/U0_fsm/current_state_reg_2_/SI (SDFFARX1_RVT) 0.0757 1.0000 0.0000 0.1930 f (35.41,12.69) 0.7500 (rail VDD) - data arrival time 0.1930 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - clock network delay (ideal) 0.0000 100.0000 - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.01,12.86) 0.7500 (rail VDD) - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3082 99.4418 - data required time 99.4418 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4418 - data arrival time -0.1930 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2489 - - -1 diff --git a/pnr/reports/Placement/report_timing.full.rpt b/pnr/reports/Placement/report_timing.full.rpt deleted file mode 100644 index 1417914..0000000 --- a/pnr/reports/Placement/report_timing.full.rpt +++ /dev/null @@ -1,5450 +0,0 @@ -**************************************** -Report : timing - -path_type full_clock_expanded - -delay_type max - -nworst 1 - -max_paths 100 - -report_by design - -nosplit - -input_pins - -nets - -transition_time - -capacitance - -derate - -physical - -voltage -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:09:16 2024 -**************************************** - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 0.2075 1.0000 0.4391 0.4391 r (21.87,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[2] (net) 7 10.6520 - U0_UART_RX/U0_data_sampling/U50/A (INVX0_RVT) 0.2075 1.0000 0.0002 0.4393 r (9.05,37.36) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.1266 1.0000 0.1194 0.5586 f (8.84,37.32) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n45 (net) 2 2.5379 - U0_UART_RX/U0_data_sampling/U49/A1 (XOR2X1_RVT) 0.1266 1.0000 0.0000 0.5587 f (6.23,40.82) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.0719 1.0000 0.2412 0.7998 r (7.50,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n52 (net) 1 0.7964 - U0_UART_RX/U0_data_sampling/U48/A3 (AND3X1_RVT) 0.0719 1.0000 0.0000 0.7998 r (9.26,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.0549 1.0000 0.1409 0.9407 r (10.08,38.94) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n50 (net) 1 0.7079 - U0_UART_RX/U0_data_sampling/U47/A4 (NAND4X0_RVT) 0.0549 1.0000 0.0000 0.9407 r (11.18,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 0.2413 1.0000 0.2169 1.1577 f (10.88,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n27 (net) 3 3.2599 - U0_UART_RX/U0_data_sampling/U39/A3 (AND4X1_RVT) 0.2413 1.0000 0.0000 1.1577 f (11.24,37.05) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.0793 1.0000 0.3025 1.4602 f (12.06,37.28) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n38 (net) 1 0.6254 - U0_UART_RX/U0_data_sampling/U38/A4 (AND4X1_RVT) 0.0793 1.0000 0.0000 1.4602 f (11.85,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.1059 1.0000 0.2507 1.7109 f (12.82,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n22 (net) 2 2.8795 - U0_UART_RX/U0_data_sampling/U28/A3 (NOR4X0_RVT) 0.1059 1.0000 0.0000 1.7109 f (14.12,35.65) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U28/Y (NOR4X0_RVT) 0.0610 1.0000 0.2797 1.9906 r (15.10,35.60) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n19 (net) 1 1.8397 - U0_UART_RX/U0_data_sampling/U27/S0 (MUX21X1_RVT) 0.0610 1.0000 0.0000 1.9906 r (23.14,37.23) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U27/Y (MUX21X1_RVT) 0.0821 1.0000 0.2034 2.1940 f (22.21,37.26) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n25 (net) 1 0.7919 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/D (SDFFARX1_RVT) 0.0821 1.0000 0.0000 2.1940 f (23.09,35.51) 0.7500 (rail VDD) - data arrival time 2.1940 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.01,36.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3119 99.4381 - data required time 99.4381 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4381 - data arrival time -2.1940 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.2442 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 0.2075 1.0000 0.4391 0.4391 r (21.87,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[2] (net) 7 10.6520 - U0_UART_RX/U0_data_sampling/U50/A (INVX0_RVT) 0.2075 1.0000 0.0002 0.4393 r (9.05,37.36) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.1266 1.0000 0.1194 0.5586 f (8.84,37.32) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n45 (net) 2 2.5379 - U0_UART_RX/U0_data_sampling/U49/A1 (XOR2X1_RVT) 0.1266 1.0000 0.0000 0.5587 f (6.23,40.82) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.0719 1.0000 0.2412 0.7998 r (7.50,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n52 (net) 1 0.7964 - U0_UART_RX/U0_data_sampling/U48/A3 (AND3X1_RVT) 0.0719 1.0000 0.0000 0.7998 r (9.26,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.0549 1.0000 0.1409 0.9407 r (10.08,38.94) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n50 (net) 1 0.7079 - U0_UART_RX/U0_data_sampling/U47/A4 (NAND4X0_RVT) 0.0549 1.0000 0.0000 0.9407 r (11.18,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 0.2413 1.0000 0.2169 1.1577 f (10.88,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n27 (net) 3 3.2599 - U0_UART_RX/U0_data_sampling/U39/A3 (AND4X1_RVT) 0.2413 1.0000 0.0000 1.1577 f (11.24,37.05) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.0793 1.0000 0.3025 1.4602 f (12.06,37.28) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n38 (net) 1 0.6254 - U0_UART_RX/U0_data_sampling/U38/A4 (AND4X1_RVT) 0.0793 1.0000 0.0000 1.4602 f (11.85,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.1059 1.0000 0.2507 1.7109 f (12.82,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n22 (net) 2 2.8795 - U0_UART_RX/U0_data_sampling/U37/S0 (MUX21X1_RVT) 0.1059 1.0000 0.0000 1.7109 f (22.38,39.00) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U37/Y (MUX21X1_RVT) 0.0861 1.0000 0.2357 1.9466 f (23.31,38.96) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n24 (net) 1 1.0282 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/D (SDFFARX1_RVT) 0.0861 1.0000 0.0000 1.9467 f (24.15,44.06) 0.7500 (rail VDD) - data arrival time 1.9467 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (25.07,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3137 99.4363 - data required time 99.4363 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4363 - data arrival time -1.9467 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.4897 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U16/A4 (AO22X1_RVT) 0.2332 1.0000 0.0000 1.6994 r (36.31,34.16) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U16/Y (AO22X1_RVT) 0.0976 1.0000 0.2005 1.8999 r (36.90,33.91) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n32 (net) 1 1.0049 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/D (SDFFARX1_RVT) 0.0976 1.0000 0.0000 1.8999 r (41.02,32.16) 0.7500 (rail VDD) - data arrival time 1.8999 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.94,32.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2800 99.4700 - data required time 99.4700 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4700 - data arrival time -1.8999 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5701 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U27/A3 (AO21X1_RVT) 0.1206 1.0000 0.0000 1.4703 f (22.94,27.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U27/Y (AO21X1_RVT) 0.0654 1.0000 0.1430 1.6133 f (23.37,27.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n27 (net) 2 1.6571 - U0_UART_RX/U0_edge_bit_counter/U24/A3 (AO21X1_RVT) 0.0654 1.0000 0.0000 1.6133 f (26.23,27.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U24/Y (AO21X1_RVT) 0.0564 1.0000 0.1040 1.7173 f (25.80,27.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n24 (net) 1 0.7008 - U0_UART_RX/U0_edge_bit_counter/U22/A2 (AO22X1_RVT) 0.0564 1.0000 0.0000 1.7173 f (26.08,25.77) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U22/Y (AO22X1_RVT) 0.0491 1.0000 0.1598 1.8771 f (25.34,25.59) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n30 (net) 1 0.8101 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/D (SDFFARX1_RVT) 0.0491 1.0000 0.0000 1.8771 f (24.00,24.00) 0.7500 (rail VDD) - data arrival time 1.8771 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.92,23.24) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2982 99.4518 - data required time 99.4518 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4518 - data arrival time -1.8771 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5746 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U3/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (34.90,44.65) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U3/Y (AO22X1_RVT) 0.0992 1.0000 0.1827 1.8822 r (34.46,43.94) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n18 (net) 1 1.1386 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/D (SDFFARX1_RVT) 0.0992 1.0000 0.0000 1.8822 r (29.17,40.72) 0.7500 (rail VDD) - data arrival time 1.8822 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.09,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2808 99.4692 - data required time 99.4692 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4692 - data arrival time -1.8822 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5870 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U8/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (38.74,41.30) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U8/Y (AO22X1_RVT) 0.0974 1.0000 0.1804 1.8798 r (39.18,40.60) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n24 (net) 1 0.9929 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/D (SDFFARX1_RVT) 0.0974 1.0000 0.0000 1.8798 r (41.17,44.06) 0.7500 (rail VDD) - data arrival time 1.8798 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2799 99.4701 - data required time 99.4701 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4701 - data arrival time -1.8798 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5902 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U4/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (36.42,44.65) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U4/Y (AO22X1_RVT) 0.0970 1.0000 0.1797 1.8792 r (35.98,43.94) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n20 (net) 1 0.9589 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/D (SDFFARX1_RVT) 0.0970 1.0000 0.0000 1.8792 r (29.62,44.06) 0.7500 (rail VDD) - data arrival time 1.8792 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.54,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2797 99.4703 - data required time 99.4703 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4703 - data arrival time -1.8792 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5911 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U6/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (38.90,41.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U6/Y (AO22X1_RVT) 0.0956 1.0000 0.1776 1.8771 r (39.33,42.31) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n22 (net) 1 0.8460 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/D (SDFFARX1_RVT) 0.0956 1.0000 0.0000 1.8771 r (41.17,40.72) 0.7500 (rail VDD) - data arrival time 1.8771 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2791 99.4709 - data required time 99.4709 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4709 - data arrival time -1.8771 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5939 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U12/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (37.48,38.26) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U12/Y (AO22X1_RVT) 0.0946 1.0000 0.1762 1.8757 r (37.04,38.97) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n28 (net) 1 0.7739 - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/D (SDFFARX1_RVT) 0.0946 1.0000 0.0000 1.8757 r (36.31,37.37) 0.7500 (rail VDD) - data arrival time 1.8757 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (37.23,36.61) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2786 99.4714 - data required time 99.4714 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4714 - data arrival time -1.8757 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5957 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U14/A3 (AO22X1_RVT) 0.2332 1.0000 0.0000 1.6994 r (36.11,34.92) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U14/Y (AO22X1_RVT) 0.0945 1.0000 0.1760 1.8754 r (35.67,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n30 (net) 1 0.7607 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/D (SDFFARX1_RVT) 0.0945 1.0000 0.0000 1.8754 r (38.13,35.51) 0.7500 (rail VDD) - data arrival time 1.8754 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (39.06,36.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2785 99.4715 - data required time 99.4715 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4715 - data arrival time -1.8754 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5961 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_deserializer/U37/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (10.54,10.58) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.0727 1.0000 0.3021 0.7487 r (11.76,10.51) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n9 (net) 1 0.9555 - U0_UART_RX/U0_deserializer/U38/A3 (NAND3X0_RVT) 0.0727 1.0000 0.0000 0.7487 r (13.06,13.79) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.0947 1.0000 0.1066 0.8554 f (13.43,13.88) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n33 (net) 1 0.7999 - U0_UART_RX/U0_deserializer/U44/A1 (NOR4X0_RVT) 0.0947 1.0000 0.0000 0.8554 f (14.27,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.0700 1.0000 0.3276 1.1830 r (15.56,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/N7 (net) 1 2.4514 - U0_UART_RX/U0_deserializer/U9/A1 (NAND2X0_RVT) 0.0700 1.0000 0.0001 1.1831 r (34.04,22.46) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.3371 1.0000 0.2511 1.4342 f (34.03,22.22) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n1 (net) 9 7.9582 - U0_UART_RX/U0_deserializer/U5/A (INVX1_RVT) 0.3371 1.0000 0.0002 1.4343 f (35.35,34.03) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.2332 1.0000 0.2650 1.6994 r (35.21,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n43 (net) 8 6.8195 - U0_UART_RX/U0_deserializer/U10/A3 (AO22X1_RVT) 0.2332 1.0000 0.0001 1.6995 r (39.05,38.26) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/U10/Y (AO22X1_RVT) 0.0936 1.0000 0.1747 1.8741 r (39.49,38.97) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n26 (net) 1 0.6919 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/D (SDFFARX1_RVT) 0.0936 1.0000 0.0000 1.8741 r (41.17,38.85) 0.7500 (rail VDD) - data arrival time 1.8741 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.61) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2781 99.4719 - data required time 99.4719 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4719 - data arrival time -1.8741 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.5977 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U27/A3 (AO21X1_RVT) 0.1206 1.0000 0.0000 1.4703 f (22.94,27.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U27/Y (AO21X1_RVT) 0.0654 1.0000 0.1430 1.6133 f (23.37,27.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n27 (net) 2 1.6571 - U0_UART_RX/U0_edge_bit_counter/U25/A2 (AO22X1_RVT) 0.0654 1.0000 0.0000 1.6133 f (25.02,27.05) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U25/Y (AO22X1_RVT) 0.0491 1.0000 0.1655 1.7788 f (24.27,27.22) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n31 (net) 1 0.8143 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/D (SDFFARX1_RVT) 0.0491 1.0000 0.0000 1.7788 f (22.78,28.82) 0.7500 (rail VDD) - data arrival time 1.7788 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (23.70,29.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2983 99.4517 - data required time 99.4518 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4518 - data arrival time -1.7788 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.6730 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.1146 1.0000 0.3752 0.3752 r (32.36,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n28 (net) 5 4.5632 - U0_UART_RX/U0_uart_fsm/U74/A2 (NAND2X0_RVT) 0.1146 1.0000 0.0000 0.3752 r (30.85,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U74/Y (NAND2X0_RVT) 0.1035 1.0000 0.1209 0.4961 f (30.99,30.60) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n44 (net) 2 1.6947 - U0_UART_RX/U0_uart_fsm/U45/A (INVX0_RVT) 0.1035 1.0000 0.0000 0.4961 f (32.52,30.68) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U45/Y (INVX0_RVT) 0.1360 1.0000 0.1397 0.6358 r (32.73,30.63) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n14 (net) 4 3.9816 - U0_UART_RX/U0_uart_fsm/U44/A1 (NAND2X0_RVT) 0.1360 1.0000 0.0000 0.6358 r (37.02,25.80) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U44/Y (NAND2X0_RVT) 0.1191 1.0000 0.1158 0.7516 f (37.03,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n16 (net) 2 1.7340 - U0_UART_RX/U0_uart_fsm/U43/A (INVX0_RVT) 0.1191 1.0000 0.0000 0.7516 f (36.17,25.48) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U43/Y (INVX0_RVT) 0.1187 1.0000 0.1345 0.8861 r (36.38,25.53) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/stp_chk_en (net) 3 3.1127 - U0_UART_RX/U0_uart_fsm/U40/A2 (AND3X1_RVT) 0.1187 1.0000 0.0000 0.8861 r (29.72,23.67) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U40/Y (AND3X1_RVT) 0.0637 1.0000 0.1634 1.0495 r (29.05,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n41 (net) 1 1.2084 - U0_UART_RX/U0_uart_fsm/U39/A4 (AND4X1_RVT) 0.0637 1.0000 0.0000 1.0495 r (18.62,23.98) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U39/Y (AND4X1_RVT) 0.0738 1.0000 0.1887 1.2382 r (17.65,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n38 (net) 1 1.0330 - U0_UART_RX/U0_uart_fsm/U38/A4 (NAND4X0_RVT) 0.0738 1.0000 0.0000 1.2382 r (18.84,20.63) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U38/Y (NAND4X0_RVT) 0.1636 1.0000 0.1630 1.4013 f (19.13,20.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n34 (net) 1 1.5962 - U0_UART_RX/U0_uart_fsm/U37/A2 (NAND2X0_RVT) 0.1636 1.0000 0.0000 1.4013 f (29.18,25.50) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U37/Y (NAND2X0_RVT) 0.1129 1.0000 0.1520 1.5533 r (29.32,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n32 (net) 1 0.7907 - U0_UART_RX/U0_uart_fsm/U36/A5 (AO221X1_RVT) 0.1129 1.0000 0.0000 1.5533 r (29.42,27.32) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U36/Y (AO221X1_RVT) 0.0717 1.0000 0.1731 1.7264 r (28.98,27.22) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/next_state[0] (net) 1 0.7845 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/D (SDFFARX1_RVT) 0.0717 1.0000 0.0000 1.7264 r (28.41,28.82) 0.7500 (rail VDD) - data arrival time 1.7264 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.33,29.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2679 99.4821 - data required time 99.4821 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4821 - data arrival time -1.7264 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.7557 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U28/A1 (AO22X1_RVT) 0.1206 1.0000 0.0000 1.4703 f (22.78,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U28/Y (AO22X1_RVT) 0.0700 1.0000 0.1943 1.6646 f (23.68,30.57) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n32 (net) 1 0.7790 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/D (SDFFARX1_RVT) 0.0700 1.0000 0.0000 1.6646 f (22.78,32.16) 0.7500 (rail VDD) - data arrival time 1.6646 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (23.70,32.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3062 99.4438 - data required time 99.4438 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4438 - data arrival time -1.6646 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.7792 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U34/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (16.71,32.18) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U34/Y (AND2X1_RVT) 0.0493 1.0000 0.1548 1.6251 f (17.38,32.26) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N20 (net) 1 1.1021 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/D (SDFFARX1_RVT) 0.0493 1.0000 0.0000 1.6252 f (19.70,27.34) 0.7500 (rail VDD) - data arrival time 1.6252 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.78,26.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2983 99.4517 - data required time 99.4517 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4517 - data arrival time -1.6252 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8265 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U35/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (19.69,32.18) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U35/Y (AND2X1_RVT) 0.0464 1.0000 0.1509 1.6212 f (19.02,32.26) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N19 (net) 1 0.8163 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/D (SDFFARX1_RVT) 0.0464 1.0000 0.0000 1.6212 f (17.16,30.68) 0.7500 (rail VDD) - data arrival time 1.6212 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.08,29.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2973 99.4527 - data required time 99.4527 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4527 - data arrival time -1.6212 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8314 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U30/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (15.95,42.22) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U30/Y (AND2X1_RVT) 0.0460 1.0000 0.1504 1.6208 f (16.62,42.29) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N24 (net) 1 0.7808 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/D (SDFFARX1_RVT) 0.0460 1.0000 0.0000 1.6208 f (17.61,44.06) 0.7500 (rail VDD) - data arrival time 1.6208 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.53,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2972 99.4528 - data required time 99.4528 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4528 - data arrival time -1.6208 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8320 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U32/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (17.47,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U32/Y (AND2X1_RVT) 0.0460 1.0000 0.1502 1.6207 f (18.14,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N22 (net) 1 0.7729 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/D (SDFFARX1_RVT) 0.0460 1.0000 0.0000 1.6207 f (17.31,37.37) 0.7500 (rail VDD) - data arrival time 1.6207 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.23,36.61) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2972 99.4528 - data required time 99.4528 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4528 - data arrival time -1.6207 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8322 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U31/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (16.25,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U31/Y (AND2X1_RVT) 0.0454 1.0000 0.1494 1.6199 f (16.92,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N23 (net) 1 0.7168 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/D (SDFFARX1_RVT) 0.0454 1.0000 0.0000 1.6199 f (16.70,40.72) 0.7500 (rail VDD) - data arrival time 1.6199 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.62,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2970 99.4530 - data required time 99.4530 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4530 - data arrival time -1.6199 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8332 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U36/A2 (OR2X1_RVT) 0.0765 1.0000 0.0001 1.2105 r (20.45,25.46) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) 0.1004 1.0000 0.1439 1.3544 r (20.88,25.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n22 (net) 4 4.0506 - U0_UART_RX/U0_edge_bit_counter/U6/A (INVX1_RVT) 0.1004 1.0000 0.0000 1.3544 r (20.97,28.82) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) 0.1206 1.0000 0.1159 1.4703 f (21.10,28.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n48 (net) 8 6.9438 - U0_UART_RX/U0_edge_bit_counter/U33/A2 (AND2X1_RVT) 0.1206 1.0000 0.0001 1.4704 f (15.95,34.01) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U33/Y (AND2X1_RVT) 0.0445 1.0000 0.1481 1.6185 f (16.62,33.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N21 (net) 1 0.6237 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/D (SDFFARX1_RVT) 0.0445 1.0000 0.0000 1.6185 f (17.77,34.03) 0.7500 (rail VDD) - data arrival time 1.6185 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.69,33.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2966 99.4534 - data required time 99.4534 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4534 - data arrival time -1.6185 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8349 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_edge_bit_counter/U52/A2 (XNOR2X1_RVT) 0.2178 1.0000 0.0006 0.4467 r (11.60,5.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) 0.0737 1.0000 0.3033 0.7500 r (12.82,5.52) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n38 (net) 1 1.0171 - U0_UART_RX/U0_edge_bit_counter/U53/A3 (NAND3X0_RVT) 0.0737 1.0000 0.0000 0.7500 r (12.76,10.45) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) 0.1105 1.0000 0.1193 0.8693 f (13.12,10.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n46 (net) 1 1.1632 - U0_UART_RX/U0_edge_bit_counter/U59/A1 (NOR4X0_RVT) 0.1105 1.0000 0.0000 0.8693 f (16.09,15.35) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) 0.0765 1.0000 0.3411 1.2105 r (17.38,15.53) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/N31 (net) 2 2.8831 - U0_UART_RX/U0_edge_bit_counter/U18/A1 (AND2X1_RVT) 0.0765 1.0000 0.0000 1.2105 r (23.18,20.48) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U18/Y (AND2X1_RVT) 0.0488 1.0000 0.1064 1.3169 r (22.67,20.55) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n21 (net) 1 0.9645 - U0_UART_RX/U0_edge_bit_counter/U17/A3 (NAND4X0_RVT) 0.0488 1.0000 0.0000 1.3169 r (21.12,22.30) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U17/Y (NAND4X0_RVT) 0.2005 1.0000 0.1187 1.4356 f (21.26,22.23) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n19 (net) 1 0.7523 - U0_UART_RX/U0_edge_bit_counter/U16/A2 (NAND2X0_RVT) 0.2005 1.0000 0.0000 1.4356 f (21.88,20.63) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/U16/Y (NAND2X0_RVT) 0.1294 1.0000 0.1740 1.6097 r (22.02,20.56) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n29 (net) 1 0.8587 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/D (SDFFARX1_RVT) 0.1294 1.0000 0.0000 1.6097 r (23.39,22.13) 0.7500 (rail VDD) - data arrival time 1.6097 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.31,22.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2947 99.4553 - data required time 99.4553 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4553 - data arrival time -1.6097 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.8456 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_uart_fsm/U63/A1 (XNOR2X1_RVT) 0.2178 1.0000 0.0005 0.4466 r (11.60,22.03) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U63/Y (XNOR2X1_RVT) 0.0824 1.0000 0.2745 0.7211 r (12.52,22.24) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n54 (net) 1 0.8104 - U0_UART_RX/U0_uart_fsm/U61/A3 (NAND4X0_RVT) 0.0824 1.0000 0.0000 0.7211 r (12.15,23.82) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U61/Y (NAND4X0_RVT) 0.1407 1.0000 0.1495 0.8706 f (12.29,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n51 (net) 1 1.2683 - U0_UART_RX/U0_uart_fsm/U60/A2 (NOR2X0_RVT) 0.1407 1.0000 0.0000 0.8706 f (17.86,25.38) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U60/Y (NOR2X0_RVT) 0.0789 1.0000 0.2087 1.0794 r (18.59,25.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n20 (net) 3 3.2435 - U0_UART_RX/U0_uart_fsm/U56/A1 (AND4X1_RVT) 0.0789 1.0000 0.0001 1.0794 r (32.52,25.80) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U56/Y (AND4X1_RVT) 0.0884 1.0000 0.1736 1.2531 r (33.03,25.57) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n26 (net) 2 1.9307 - U0_UART_RX/U0_uart_fsm/U34/A1 (AO21X1_RVT) 0.0884 1.0000 0.0000 1.2531 r (35.19,32.34) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U34/Y (AO21X1_RVT) 0.0574 1.0000 0.1477 1.4009 r (35.84,32.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n25 (net) 1 0.7188 - U0_UART_RX/U0_uart_fsm/U33/A2 (AO21X1_RVT) 0.0574 1.0000 0.0000 1.4009 r (35.50,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U33/Y (AO21X1_RVT) 0.0673 1.0000 0.1531 1.5540 r (34.61,30.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/next_state[1] (net) 1 1.3064 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/D (SDFFARX1_RVT) 0.0673 1.0000 0.0000 1.5540 r (28.25,34.03) 0.7500 (rail VDD) - data arrival time 1.5540 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,33.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2659 99.4841 - data required time 99.4841 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4841 - data arrival time -1.5540 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9301 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U21/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (22.73,8.44) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U21/Y (AO222X1_RVT) 0.0910 1.0000 0.2184 1.5198 r (22.30,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n26 (net) 1 1.1262 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/D (SDFFARX1_RVT) 0.0910 1.0000 0.0000 1.5198 r (15.64,7.28) 0.7500 (rail VDD) - data arrival time 1.5198 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (16.56,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2769 99.4731 - data required time 99.4731 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4731 - data arrival time -1.5198 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9533 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U22/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (22.58,10.94) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U22/Y (AO222X1_RVT) 0.0904 1.0000 0.2178 1.5192 r (22.14,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n27 (net) 1 1.0905 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/D (SDFFARX1_RVT) 0.0904 1.0000 0.0000 1.5192 r (16.85,8.76) 0.7500 (rail VDD) - data arrival time 1.5192 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.77,9.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2766 99.4734 - data required time 99.4734 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4734 - data arrival time -1.5192 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9541 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U24/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (28.96,8.44) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U24/Y (AO222X1_RVT) 0.0895 1.0000 0.2170 1.5183 r (28.53,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n29 (net) 1 1.0397 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/D (SDFFARX1_RVT) 0.0895 1.0000 0.0000 1.5184 r (27.80,3.93) 0.7500 (rail VDD) - data arrival time 1.5184 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.72,3.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2762 99.4738 - data required time 99.4738 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4738 - data arrival time -1.5184 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9554 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U19/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3013 r (32.21,10.94) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U19/Y (AO222X1_RVT) 0.0890 1.0000 0.2164 1.5178 r (32.65,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n24 (net) 1 1.0065 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/D (SDFFARX1_RVT) 0.0890 1.0000 0.0000 1.5178 r (34.18,13.96) 0.7500 (rail VDD) - data arrival time 1.5178 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.10,13.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2760 99.4740 - data required time 99.4740 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4740 - data arrival time -1.5178 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9562 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U23/A6 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (25.83,8.44) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U23/Y (AO222X1_RVT) 0.0853 1.0000 0.2123 1.5137 r (26.26,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n28 (net) 1 0.7955 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/D (SDFFARX1_RVT) 0.0853 1.0000 0.0000 1.5137 r (25.52,7.28) 0.7500 (rail VDD) - data arrival time 1.5137 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.44,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2743 99.4757 - data required time 99.4758 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4758 - data arrival time -1.5137 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9621 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U25/A6 (AO222X1_RVT) 0.1556 1.0000 0.0000 1.3013 r (32.06,7.60) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U25/Y (AO222X1_RVT) 0.0841 1.0000 0.2110 1.5123 r (32.50,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n30 (net) 1 0.7277 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/D (SDFFARX1_RVT) 0.0841 1.0000 0.0000 1.5123 r (34.49,7.28) 0.7500 (rail VDD) - data arrival time 1.5123 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.41,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2737 99.4763 - data required time 99.4763 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4763 - data arrival time -1.5123 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9640 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.69,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) 0.2075 1.0000 0.4391 0.4391 r (21.87,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[2] (net) 7 10.6520 - U0_UART_RX/U0_data_sampling/U50/A (INVX0_RVT) 0.2075 1.0000 0.0002 0.4393 r (9.05,37.36) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.1266 1.0000 0.1194 0.5586 f (8.84,37.32) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n45 (net) 2 2.5379 - U0_UART_RX/U0_data_sampling/U49/A1 (XOR2X1_RVT) 0.1266 1.0000 0.0000 0.5587 f (6.23,40.82) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.0719 1.0000 0.2412 0.7998 r (7.50,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n52 (net) 1 0.7964 - U0_UART_RX/U0_data_sampling/U48/A3 (AND3X1_RVT) 0.0719 1.0000 0.0000 0.7998 r (9.26,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.0549 1.0000 0.1409 0.9407 r (10.08,38.94) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n50 (net) 1 0.7079 - U0_UART_RX/U0_data_sampling/U47/A4 (NAND4X0_RVT) 0.0549 1.0000 0.0000 0.9407 r (11.18,38.87) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) 0.2413 1.0000 0.2169 1.1577 f (10.88,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n27 (net) 3 3.2599 - U0_UART_RX/U0_data_sampling/U46/S0 (MUX21X1_RVT) 0.2413 1.0000 0.0000 1.1577 f (20.40,39.00) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U46/Y (MUX21X1_RVT) 0.0833 1.0000 0.3131 1.4708 f (21.33,38.96) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n23 (net) 1 0.8555 - U0_UART_RX/U0_data_sampling/Samples_reg_0_/D (SDFFARX1_RVT) 0.0833 1.0000 0.0000 1.4708 f (23.54,40.72) 0.7500 (rail VDD) - data arrival time 1.4708 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.46,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3124 99.4376 - data required time 99.4376 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4376 - data arrival time -1.4708 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9668 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U26/A5 (AO222X1_RVT) 0.1556 1.0000 0.0001 1.3013 r (32.06,8.78) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U26/Y (AO222X1_RVT) 0.0862 1.0000 0.1991 1.5004 r (32.65,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n31 (net) 1 0.8489 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/D (SDFFARX1_RVT) 0.0862 1.0000 0.0000 1.5004 r (34.03,10.62) 0.7500 (rail VDD) - data arrival time 1.5004 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (34.95,9.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2747 99.4753 - data required time 99.4753 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4753 - data arrival time -1.5004 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9749 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U28/A1 (NAND2X0_RVT) 0.1093 1.0000 0.0000 0.9461 f (34.19,5.74) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U28/Y (NAND2X0_RVT) 0.1422 1.0000 0.1463 1.0925 r (34.18,5.50) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n20 (net) 2 1.7583 - U0_UART_TX/U0_Serializer/U27/A2 (AND2X1_RVT) 0.1422 1.0000 0.0000 1.0925 r (33.37,5.43) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U27/Y (AND2X1_RVT) 0.1556 1.0000 0.2088 1.3013 r (32.70,5.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n18 (net) 8 7.2693 - U0_UART_TX/U0_Serializer/U20/A2 (AO22X1_RVT) 0.1556 1.0000 0.0001 1.3014 r (23.39,5.71) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U20/Y (AO22X1_RVT) 0.0698 1.0000 0.2064 1.5078 r (24.13,5.53) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n25 (net) 1 1.2997 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/D (SDFFARX1_RVT) 0.0698 1.0000 0.0000 1.5078 r (14.88,3.93) 0.7500 (rail VDD) - data arrival time 1.5078 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (15.80,3.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2671 99.4829 - data required time 99.4829 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4829 - data arrival time -1.5078 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 97.9751 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_par_chk/par_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/Q (SDFFARX1_RVT) 0.1175 1.0000 0.3772 0.3772 r (45.28,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA[2] (net) 4 4.7533 - U0_UART_RX/U0_par_chk/U6/A2 (XNOR2X1_RVT) 0.1175 1.0000 0.0001 0.3772 r (38.78,44.02) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U6/Y (XNOR2X1_RVT) 0.0827 1.0000 0.2716 0.6488 r (37.56,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n6 (net) 1 1.6553 - U0_UART_RX/U0_par_chk/U5/A3 (XNOR3X1_RVT) 0.0827 1.0000 0.0000 0.6488 r (36.43,41.06) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U5/Y (XNOR3X1_RVT) 0.1289 1.0000 0.1783 0.8271 f (37.14,40.62) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n4 (net) 1 1.8228 - U0_UART_RX/U0_par_chk/U3/A2 (XNOR3X1_RVT) 0.1289 1.0000 0.0000 0.8271 f (37.58,32.21) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U3/Y (XNOR3X1_RVT) 0.1264 1.0000 0.4443 1.2715 f (39.88,32.26) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n2 (net) 1 0.9994 - U0_UART_RX/U0_par_chk/U2/A4 (AO22X1_RVT) 0.1264 1.0000 0.0000 1.2715 f (40.83,28.69) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/U2/Y (AO22X1_RVT) 0.0490 1.0000 0.1512 1.4227 f (40.24,28.94) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/n9 (net) 1 0.7960 - U0_UART_RX/U0_par_chk/par_err_reg/D (SDFFARX1_RVT) 0.0490 1.0000 0.0000 1.4227 f (41.17,30.68) 0.7500 (rail VDD) - data arrival time 1.4227 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,29.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2982 99.4518 - data required time 99.4518 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4518 - data arrival time -1.4227 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.0291 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/parity_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.87,13.20) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.87,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/Q (SDFFARX1_RVT) 0.0795 1.0000 0.3472 0.3472 r (32.05,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n14 (net) 2 2.1642 - U0_UART_TX/U0_parity_calc/U7/A2 (XNOR2X1_RVT) 0.0795 1.0000 0.0000 0.3472 r (32.73,12.14) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U7/Y (XNOR2X1_RVT) 0.0830 1.0000 0.2515 0.5987 r (33.95,12.21) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n10 (net) 1 1.6747 - U0_UART_TX/U0_parity_calc/U6/A3 (XNOR3X1_RVT) 0.0830 1.0000 0.0000 0.5987 r (33.70,15.10) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U6/Y (XNOR3X1_RVT) 0.1281 1.0000 0.1727 0.7714 f (34.40,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n3 (net) 1 1.4615 - U0_UART_TX/U0_parity_calc/U3/A2 (XNOR3X1_RVT) 0.1281 1.0000 0.0000 0.7714 f (33.93,18.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U3/Y (XNOR3X1_RVT) 0.1265 1.0000 0.4394 1.2108 f (36.23,18.89) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n2 (net) 1 0.7865 - U0_UART_TX/U0_parity_calc/U2/A4 (AO22X1_RVT) 0.1265 1.0000 0.0000 1.2108 f (38.24,18.66) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U2/Y (AO22X1_RVT) 0.0494 1.0000 0.1517 1.3625 f (37.65,18.90) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n27 (net) 1 0.8312 - U0_UART_TX/U0_parity_calc/parity_reg/D (SDFFARX1_RVT) 0.0494 1.0000 0.0000 1.3625 f (35.70,17.31) 0.7500 (rail VDD) - data arrival time 1.3625 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.62,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2984 99.4516 - data required time 99.4516 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4516 - data arrival time -1.3625 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.0891 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U34/A1 (AND2X1_RVT) 0.1093 1.0000 0.0001 0.9462 f (40.12,22.30) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U34/Y (AND2X1_RVT) 0.0581 1.0000 0.1519 1.0980 f (40.63,22.23) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N23 (net) 2 2.0417 - U0_UART_TX/U0_Serializer/U32/A3 (AO21X1_RVT) 0.0581 1.0000 0.0000 1.0980 f (42.70,24.58) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U32/Y (AO21X1_RVT) 0.0512 1.0000 0.1014 1.1994 f (43.13,23.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n21 (net) 1 0.7766 - U0_UART_TX/U0_Serializer/U30/A2 (AO21X1_RVT) 0.0512 1.0000 0.0000 1.1994 f (44.53,22.15) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U30/Y (AO21X1_RVT) 0.0532 1.0000 0.1570 1.3564 f (45.41,22.24) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N25 (net) 1 0.9550 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/D (SDFFARX1_RVT) 0.0532 1.0000 0.0000 1.3564 f (41.17,20.65) 0.7500 (rail VDD) - data arrival time 1.3564 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,19.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2997 99.4503 - data required time 99.4503 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4503 - data arrival time -1.3564 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.0939 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.62,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) 0.2178 1.0000 0.4461 0.4461 r (20.81,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count[4] (net) 7 11.3258 - U0_UART_RX/U0_uart_fsm/U63/A1 (XNOR2X1_RVT) 0.2178 1.0000 0.0005 0.4466 r (11.60,22.03) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U63/Y (XNOR2X1_RVT) 0.0824 1.0000 0.2745 0.7211 r (12.52,22.24) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n54 (net) 1 0.8104 - U0_UART_RX/U0_uart_fsm/U61/A3 (NAND4X0_RVT) 0.0824 1.0000 0.0000 0.7211 r (12.15,23.82) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U61/Y (NAND4X0_RVT) 0.1407 1.0000 0.1495 0.8706 f (12.29,23.90) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n51 (net) 1 1.2683 - U0_UART_RX/U0_uart_fsm/U60/A2 (NOR2X0_RVT) 0.1407 1.0000 0.0000 0.8706 f (17.86,25.38) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U60/Y (NOR2X0_RVT) 0.0789 1.0000 0.2087 1.0794 r (18.59,25.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n20 (net) 3 3.2435 - U0_UART_RX/U0_uart_fsm/U30/A2 (NAND3X0_RVT) 0.0789 1.0000 0.0001 1.0794 r (33.74,25.65) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U30/Y (NAND3X0_RVT) 0.0948 1.0000 0.0981 1.1776 f (33.61,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n19 (net) 1 0.5918 - U0_UART_RX/U0_uart_fsm/U29/A2 (NAND2X0_RVT) 0.0948 1.0000 0.0000 1.1776 f (34.65,25.50) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U29/Y (NAND2X0_RVT) 0.0892 1.0000 0.1110 1.2886 r (34.79,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/next_state[2] (net) 1 0.7317 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/D (SDFFARX1_RVT) 0.0892 1.0000 0.0000 1.2886 r (34.79,27.34) 0.7500 (rail VDD) - data arrival time 1.2886 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.71,26.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2761 99.4739 - data required time 99.4739 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4739 - data arrival time -1.2886 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.1853 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U17/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (23.65,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U17/Y (AO22X1_RVT) 0.0727 1.0000 0.2094 1.1295 f (23.06,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n37 (net) 1 1.1030 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/D (SDFFARX1_RVT) 0.0727 1.0000 0.0000 1.1295 f (16.40,10.62) 0.7500 (rail VDD) - data arrival time 1.1295 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.32,9.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3075 99.4425 - data required time 99.4426 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4426 - data arrival time -1.1295 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3131 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U15/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (29.73,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U15/Y (AO22X1_RVT) 0.0718 1.0000 0.2079 1.1279 f (29.14,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n35 (net) 1 1.0007 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/D (SDFFARX1_RVT) 0.0718 1.0000 0.0000 1.1279 f (29.01,20.65) 0.7500 (rail VDD) - data arrival time 1.1279 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.93,19.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3070 99.4430 - data required time 99.4430 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4430 - data arrival time -1.1279 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3151 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_mux/OUT_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U16/A1 (AO22X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.87,13.94) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U16/Y (AO22X1_RVT) 0.0694 1.0000 0.1752 0.8097 f (42.97,13.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/mux_sel[0] (net) 3 2.5610 - U0_UART_TX/U0_mux/U4/A (INVX1_RVT) 0.0694 1.0000 0.0000 0.8097 f (42.79,15.44) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/U4/Y (INVX1_RVT) 0.0585 1.0000 0.0708 0.8805 r (42.66,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/n3 (net) 2 1.7661 - U0_UART_TX/U0_mux/U8/A4 (AO22X1_RVT) 0.0585 1.0000 0.0000 0.8805 r (40.87,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/U8/Y (AO22X1_RVT) 0.0601 1.0000 0.1309 1.0115 r (41.46,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/n4 (net) 1 0.7758 - U0_UART_TX/U0_mux/U6/A2 (AO22X1_RVT) 0.0601 1.0000 0.0000 1.0115 r (44.32,15.74) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/U6/Y (AO22X1_RVT) 0.0623 1.0000 0.1588 1.1703 r (43.58,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/mux_out (net) 1 0.8944 - U0_UART_TX/U0_mux/OUT_reg/D (SDFFARX1_RVT) 0.0623 1.0000 0.0000 1.1703 r (41.17,17.31) 0.7500 (rail VDD) - data arrival time 1.1703 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2640 99.4860 - data required time 99.4860 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4860 - data arrival time -1.1703 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3158 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U21/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (26.23,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U21/Y (AO22X1_RVT) 0.0715 1.0000 0.2072 1.1272 f (25.64,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n41 (net) 1 0.9661 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/D (SDFFARX1_RVT) 0.0715 1.0000 0.0000 1.1272 f (22.02,17.31) 0.7500 (rail VDD) - data arrival time 1.1272 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (22.94,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3069 99.4431 - data required time 99.4431 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4431 - data arrival time -1.1272 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3159 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U19/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (22.13,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U19/Y (AO22X1_RVT) 0.0714 1.0000 0.2070 1.1271 f (21.54,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n39 (net) 1 0.9580 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/D (SDFFARX1_RVT) 0.0714 1.0000 0.0000 1.1271 f (18.07,13.96) 0.7500 (rail VDD) - data arrival time 1.1271 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.99,13.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3069 99.4431 - data required time 99.4431 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4431 - data arrival time -1.1271 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3161 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U23/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (24.71,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U23/Y (AO22X1_RVT) 0.0712 1.0000 0.2064 1.1264 f (24.12,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n43 (net) 1 0.9258 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/D (SDFFARX1_RVT) 0.0712 1.0000 0.0000 1.1264 f (18.83,15.44) 0.7500 (rail VDD) - data arrival time 1.1264 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.75,16.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3067 99.4433 - data required time 99.4433 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4433 - data arrival time -1.1264 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3169 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U11/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (30.79,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U11/Y (AO22X1_RVT) 0.0707 1.0000 0.2052 1.1252 f (30.20,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n31 (net) 1 0.8646 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/D (SDFFARX1_RVT) 0.0707 1.0000 0.0000 1.1252 f (27.95,13.96) 0.7500 (rail VDD) - data arrival time 1.1252 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.87,13.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3065 99.4435 - data required time 99.4435 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4435 - data arrival time -1.1252 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3183 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U13/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (28.21,15.31) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U13/Y (AO22X1_RVT) 0.0700 1.0000 0.2034 1.1234 f (27.62,15.56) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n33 (net) 1 0.7749 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/D (SDFFARX1_RVT) 0.0700 1.0000 0.0000 1.1234 f (28.25,17.31) 0.7500 (rail VDD) - data arrival time 1.1234 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3062 99.4438 - data required time 99.4438 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4438 - data arrival time -1.1234 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3204 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/Q (SDFFARX1_RVT) 0.1019 1.0000 0.3658 0.3658 r (35.66,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy (net) 3 3.7128 - U0_UART_TX/U0_parity_calc/U12/A (INVX1_RVT) 0.1019 1.0000 0.0000 0.3658 r (34.89,3.93) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U12/Y (INVX1_RVT) 0.0528 1.0000 0.0445 0.4103 f (34.75,3.83) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n16 (net) 1 0.6115 - U0_UART_TX/U0_parity_calc/U10/A2 (NAND2X0_RVT) 0.0528 1.0000 0.0000 0.4103 f (33.21,3.91) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U10/Y (NAND2X0_RVT) 0.4320 1.0000 0.2950 0.7053 r (33.08,3.84) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n8 (net) 9 7.7231 - U0_UART_TX/U0_parity_calc/U5/A (INVX1_RVT) 0.4320 1.0000 0.0002 0.7055 r (26.07,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U5/Y (INVX1_RVT) 0.2565 1.0000 0.2144 0.9200 f (25.94,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n15 (net) 8 7.3232 - U0_UART_TX/U0_parity_calc/U9/A4 (AO22X1_RVT) 0.2565 1.0000 0.0000 0.9200 f (26.54,11.97) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/U9/Y (AO22X1_RVT) 0.0694 1.0000 0.2021 1.1221 f (25.95,12.22) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n29 (net) 1 0.7065 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/D (SDFFARX1_RVT) 0.0694 1.0000 0.0000 1.1221 f (25.67,10.62) 0.7500 (rail VDD) - data arrival time 1.1221 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.59,9.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3059 99.4441 - data required time 99.4441 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4441 - data arrival time -1.1221 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3220 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U34/A1 (AND2X1_RVT) 0.1093 1.0000 0.0001 0.9462 f (40.12,22.30) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U34/Y (AND2X1_RVT) 0.0581 1.0000 0.1519 1.0980 f (40.63,22.23) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N23 (net) 2 2.0417 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/D (SDFFARX1_RVT) 0.0581 1.0000 0.0000 1.0981 f (35.40,20.65) 0.7500 (rail VDD) - data arrival time 1.0981 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.32,19.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3014 99.4486 - data required time 99.4486 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4486 - data arrival time -1.0981 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3506 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_stp_chk/stp_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0931 1.0000 0.3359 0.3359 f (32.36,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n28 (net) 5 4.4847 - U0_UART_RX/U0_uart_fsm/U74/A2 (NAND2X0_RVT) 0.0931 1.0000 0.0000 0.3359 f (30.85,30.66) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U74/Y (NAND2X0_RVT) 0.1332 1.0000 0.1397 0.4756 r (30.99,30.60) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n44 (net) 2 1.7193 - U0_UART_RX/U0_uart_fsm/U45/A (INVX0_RVT) 0.1332 1.0000 0.0000 0.4756 r (32.52,30.68) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U45/Y (INVX0_RVT) 0.1161 1.0000 0.1232 0.5988 f (32.73,30.63) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n14 (net) 4 3.8766 - U0_UART_RX/U0_uart_fsm/U44/A1 (NAND2X0_RVT) 0.1161 1.0000 0.0000 0.5988 f (37.02,25.80) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U44/Y (NAND2X0_RVT) 0.1330 1.0000 0.1504 0.7492 r (37.03,25.56) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n16 (net) 2 1.7542 - U0_UART_RX/U0_uart_fsm/U43/A (INVX0_RVT) 0.1330 1.0000 0.0000 0.7492 r (36.17,25.48) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U43/Y (INVX0_RVT) 0.1044 1.0000 0.1090 0.8582 f (36.38,25.53) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/stp_chk_en (net) 3 3.0486 - U0_UART_RX/U0_stp_chk/U3/A (INVX1_RVT) 0.1044 1.0000 0.0000 0.8583 f (38.14,25.47) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/U3/Y (INVX1_RVT) 0.0616 1.0000 0.0715 0.9298 r (38.28,25.58) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/n1 (net) 1 0.7590 - U0_UART_RX/U0_stp_chk/U2/A2 (OAI22X1_RVT) 0.0616 1.0000 0.0000 0.9298 r (39.36,26.25) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/U2/Y (OAI22X1_RVT) 0.0367 1.0000 0.1615 1.0913 f (40.50,25.54) 0.7500 (rail VDD) - U0_UART_RX/U0_stp_chk/n4 (net) 1 0.7608 - U0_UART_RX/U0_stp_chk/stp_err_reg/D (SDFFARX1_RVT) 0.0367 1.0000 0.0000 1.0913 f (40.87,27.34) 0.7500 (rail VDD) - data arrival time 1.0913 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_stp_chk/stp_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.79,26.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2940 99.4560 - data required time 99.4560 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4560 - data arrival time -1.0913 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3647 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U18/A3 (AND3X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (40.97,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U18/Y (AND3X1_RVT) 0.1093 1.0000 0.1985 0.9461 f (40.15,10.53) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/Ser_enable (net) 5 5.3027 - U0_UART_TX/U0_Serializer/U33/A1 (AND2X1_RVT) 0.1093 1.0000 0.0001 0.9462 f (41.42,23.82) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U33/Y (AND2X1_RVT) 0.0455 1.0000 0.1382 1.0844 f (40.91,23.90) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/N24 (net) 1 0.8874 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/D (SDFFARX1_RVT) 0.0455 1.0000 0.0000 1.0844 f (36.16,24.00) 0.7500 (rail VDD) - data arrival time 1.0844 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (37.08,23.24) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2970 99.4530 - data required time 99.4530 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4530 - data arrival time -1.0844 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.3686 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0603 1.0000 0.3280 0.3280 r (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.8071 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0603 1.0000 0.0000 0.3280 r (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0864 1.0000 0.1291 0.4571 r (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3898 - U0_UART_TX/U0_fsm/U20/A3 (AO21X1_RVT) 0.0864 1.0000 0.0000 0.4572 r (44.68,11.51) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U20/Y (AO21X1_RVT) 0.0787 1.0000 0.1216 0.5788 r (45.11,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n12 (net) 2 2.0040 - U0_UART_TX/U0_fsm/U7/A (INVX1_RVT) 0.0787 1.0000 0.0000 0.5788 r (44.62,13.97) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U7/Y (INVX1_RVT) 0.0547 1.0000 0.0557 0.6345 f (44.48,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n9 (net) 2 1.6645 - U0_UART_TX/U0_fsm/U19/A1 (AND2X1_RVT) 0.0547 1.0000 0.0000 0.6345 f (43.40,12.27) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U19/Y (AND2X1_RVT) 0.0530 1.0000 0.1131 0.7476 f (42.88,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n11 (net) 2 1.5088 - U0_UART_TX/U0_fsm/U11/A1 (OA21X1_RVT) 0.0530 1.0000 0.0000 0.7476 f (44.31,10.60) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U11/Y (OA21X1_RVT) 0.0552 1.0000 0.1586 0.9062 f (43.33,10.55) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/next_state[1] (net) 1 0.9738 - U0_UART_TX/U0_fsm/current_state_reg_1_/D (SDFFARX1_RVT) 0.0552 1.0000 0.0000 0.9062 f (41.17,7.28) 0.7500 (rail VDD) - data arrival time 0.9062 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3004 99.4496 - data required time 99.4496 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4496 - data arrival time -0.9062 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.5434 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/sampled_bit_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/Q (SDFFARX1_RVT) 0.0949 1.0000 0.3600 0.3600 r (38.89,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n1 (net) 3 3.2333 - U0_UART_RX/U0_uart_fsm/U79/A3 (AO21X1_RVT) 0.0949 1.0000 0.0000 0.3601 r (28.50,31.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U79/Y (AO21X1_RVT) 0.0889 1.0000 0.1329 0.4930 r (28.08,30.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n48 (net) 3 2.6978 - U0_UART_RX/U0_uart_fsm/U78/A2 (NAND2X0_RVT) 0.0889 1.0000 0.0000 0.4930 r (27.66,32.18) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U78/Y (NAND2X0_RVT) 0.2096 1.0000 0.1849 0.6779 f (27.80,32.25) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/dat_samp_en (net) 5 4.6254 - U0_UART_RX/U0_data_sampling/U62/A1 (AND2X1_RVT) 0.2096 1.0000 0.0001 0.6779 f (29.63,39.02) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/U62/Y (AND2X1_RVT) 0.0588 1.0000 0.1831 0.8611 f (30.15,38.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/N58 (net) 1 0.6270 - U0_UART_RX/U0_data_sampling/sampled_bit_reg/D (SDFFARX1_RVT) 0.0588 1.0000 0.0000 0.8611 f (31.29,38.85) 0.7500 (rail VDD) - data arrival time 0.8611 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_data_sampling/sampled_bit_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (32.22,39.61) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3016 99.4484 - data required time 99.4484 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4484 - data arrival time -0.8611 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.5873 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_0_/Q (SDFFARX1_RVT) 0.0908 1.0000 0.3566 0.3566 r (39.50,20.55) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count[0] (net) 3 2.9485 - U0_UART_TX/U0_Serializer/U18/A2 (AND3X1_RVT) 0.0908 1.0000 0.0000 0.3567 r (42.03,22.46) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U18/Y (AND3X1_RVT) 0.0666 1.0000 0.1573 0.5140 r (41.37,22.22) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_done (net) 1 1.5158 - U0_UART_TX/U0_fsm/U8/A (INVX1_RVT) 0.0666 1.0000 0.0000 0.5140 r (39.66,15.44) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U8/Y (INVX1_RVT) 0.0606 1.0000 0.0635 0.5775 f (39.80,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n6 (net) 3 2.7404 - U0_UART_TX/U0_fsm/U10/A2 (OA21X1_RVT) 0.0606 1.0000 0.0000 0.5775 f (39.36,13.19) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U10/Y (OA21X1_RVT) 0.0553 1.0000 0.1414 0.7189 f (40.19,13.90) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n10 (net) 1 0.9833 - U0_UART_TX/U0_fsm/U9/A3 (NOR3X0_RVT) 0.0553 1.0000 0.0000 0.7189 f (41.02,12.01) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U9/Y (NOR3X0_RVT) 0.0452 1.0000 0.1770 0.8959 r (40.30,12.20) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/next_state[2] (net) 1 0.9437 - U0_UART_TX/U0_fsm/current_state_reg_2_/D (SDFFARX1_RVT) 0.0452 1.0000 0.0000 0.8959 r (35.09,12.10) 0.7500 (rail VDD) - data arrival time 0.8959 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.01,12.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2601 99.4899 - data required time 99.4899 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4899 - data arrival time -0.8959 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.5939 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_0_/Q (SDFFARX1_RVT) 0.0908 1.0000 0.3566 0.3566 r (39.50,20.55) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count[0] (net) 3 2.9485 - U0_UART_TX/U0_Serializer/U18/A2 (AND3X1_RVT) 0.0908 1.0000 0.0000 0.3567 r (42.03,22.46) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/U18/Y (AND3X1_RVT) 0.0666 1.0000 0.1573 0.5140 r (41.37,22.22) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_done (net) 1 1.5158 - U0_UART_TX/U0_fsm/U8/A (INVX1_RVT) 0.0666 1.0000 0.0000 0.5140 r (39.66,15.44) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U8/Y (INVX1_RVT) 0.0606 1.0000 0.0635 0.5775 f (39.80,15.54) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n6 (net) 3 2.7404 - U0_UART_TX/U0_fsm/U13/A2 (AO22X1_RVT) 0.0606 1.0000 0.0000 0.5775 f (39.76,9.05) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U13/Y (AO22X1_RVT) 0.0485 1.0000 0.1617 0.7392 f (39.02,8.87) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n13 (net) 1 0.7607 - U0_UART_TX/U0_fsm/U12/A1 (AND2X1_RVT) 0.0485 1.0000 0.0000 0.7392 f (40.73,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U12/Y (AND2X1_RVT) 0.0482 1.0000 0.1031 0.8423 f (41.24,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/next_state[0] (net) 1 0.9643 - U0_UART_TX/U0_fsm/current_state_reg_0_/D (SDFFARX1_RVT) 0.0482 1.0000 0.0000 0.8423 f (41.17,3.93) 0.7500 (rail VDD) - data arrival time 0.8423 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,3.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2979 99.4521 - data required time 99.4521 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4521 - data arrival time -0.8423 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.6097 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_strt_chk/strt_glitch_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/Q (SDFFARX1_RVT) 0.0949 1.0000 0.3600 0.3600 r (38.89,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n1 (net) 3 3.2333 - U0_UART_RX/U0_uart_fsm/U79/A3 (AO21X1_RVT) 0.0949 1.0000 0.0000 0.3601 r (28.50,31.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U79/Y (AO21X1_RVT) 0.0889 1.0000 0.1329 0.4930 r (28.08,30.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n48 (net) 3 2.6978 - U0_UART_RX/U0_uart_fsm/U55/A2 (OR2X1_RVT) 0.0889 1.0000 0.0000 0.4930 r (31.25,32.15) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U55/Y (OR2X1_RVT) 0.0625 1.0000 0.1241 0.6171 r (31.67,32.30) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n13 (net) 2 1.7359 - U0_UART_RX/U0_uart_fsm/U27/A (INVX0_RVT) 0.0625 1.0000 0.0000 0.6171 r (33.74,34.02) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/U27/Y (INVX0_RVT) 0.0563 1.0000 0.0614 0.6785 f (33.95,33.97) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/strt_chk_en (net) 2 1.6902 - U0_UART_RX/U0_strt_chk/U2/A2 (AO22X1_RVT) 0.0563 1.0000 0.0000 0.6785 f (34.90,35.80) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/U2/Y (AO22X1_RVT) 0.0500 1.0000 0.1611 0.8396 f (34.15,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/n3 (net) 1 0.8945 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/D (SDFFARX1_RVT) 0.0500 1.0000 0.0000 0.8396 f (29.32,35.51) 0.7500 (rail VDD) - data arrival time 0.8396 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.24,36.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2986 99.4514 - data required time 99.4514 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4514 - data arrival time -0.8396 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.6119 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/Q (SDFFARX1_RVT) 0.0524 1.0000 0.2941 0.2941 f (45.28,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_1_ (net) 1 0.7792 - U0_UART_TX/U0_fsm/U21/A1 (AND2X1_RVT) 0.0524 1.0000 0.0000 0.2941 f (45.22,8.93) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U21/Y (AND2X1_RVT) 0.0734 1.0000 0.1304 0.4245 f (44.71,8.85) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n15 (net) 4 3.3467 - U0_UART_TX/U0_fsm/U17/A3 (AO21X1_RVT) 0.0734 1.0000 0.0000 0.4245 f (42.19,8.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/U17/Y (AO21X1_RVT) 0.0535 1.0000 0.1117 0.5362 f (41.76,8.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_c (net) 1 0.9834 - U0_UART_TX/U0_fsm/busy_reg/D (SDFFARX1_RVT) 0.0535 1.0000 0.0000 0.5362 f (39.76,5.41) 0.7500 (rail VDD) - data arrival time 0.5362 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (38.84,6.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2998 99.4502 - data required time 99.4502 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4502 - data arrival time -0.5362 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 98.9140 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.33,29.58) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.33,29.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/Q (SDFFARX1_RVT) 0.0955 1.0000 0.3605 0.3605 r (32.51,28.93) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/n2 (net) 4 3.2740 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/SI (SDFFARX1_RVT) 0.0955 1.0000 0.0000 0.3605 r (35.10,26.75) 0.7500 (rail VDD) - data arrival time 0.3605 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.71,26.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2849 99.4651 - data required time 99.4651 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4651 - data arrival time -0.3605 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1045 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.01,12.86) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.01,12.86) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_2_/Q (SDFFARX1_RVT) 0.0910 1.0000 0.3567 0.3567 r (39.20,12.21) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/dftopt2 (net) 3 2.9593 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/SI (SDFFARX1_RVT) 0.0910 1.0000 0.0000 0.3568 r (34.34,10.03) 0.7500 (rail VDD) - data arrival time 0.3568 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (34.95,9.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2831 99.4669 - data required time 99.4669 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4669 - data arrival time -0.3568 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1102 - - - - Startpoint: U0_UART_TX/U0_mux/OUT_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/parity_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,16.55) 0.7500 (rail VDD) - - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/OUT_reg/Q (SDFFARX1_RVT) 0.0890 1.0000 0.3551 0.3551 r (45.28,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_mux/OUT (net) 2 2.8265 - U0_UART_TX/U0_parity_calc/parity_reg/SI (SDFFARX1_RVT) 0.0890 1.0000 0.0000 0.3552 r (36.02,16.72) 0.7500 (rail VDD) - data arrival time 0.3552 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.62,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2823 99.4677 - data required time 99.4677 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4677 - data arrival time -0.3552 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1125 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,16.55) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/Q (SDFFARX1_RVT) 0.0786 1.0000 0.3465 0.3465 r (32.36,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n1 (net) 2 2.1027 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/SI (SDFFARX1_RVT) 0.0786 1.0000 0.0000 0.3465 r (22.34,16.72) 0.7500 (rail VDD) - data arrival time 0.3465 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (22.94,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2781 99.4719 - data required time 99.4719 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4719 - data arrival time -0.3465 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1255 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.99,13.20) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.99,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/Q (SDFFARX1_RVT) 0.0773 1.0000 0.3454 0.3454 r (22.17,13.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n6 (net) 2 2.0150 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/SI (SDFFARX1_RVT) 0.0773 1.0000 0.0000 0.3454 r (16.71,10.03) 0.7500 (rail VDD) - data arrival time 0.3454 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.32,9.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2775 99.4725 - data required time 99.4725 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4725 - data arrival time -0.3454 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1270 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.32,9.86) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.32,9.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_4_/Q (SDFFARX1_RVT) 0.0757 1.0000 0.3439 0.3439 r (20.50,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/dftopt1 (net) 2 1.9034 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/SI (SDFFARX1_RVT) 0.0757 1.0000 0.0000 0.3439 r (17.17,9.35) 0.7500 (rail VDD) - data arrival time 0.3439 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.77,9.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2769 99.4731 - data required time 99.4731 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4731 - data arrival time -0.3439 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1292 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (22.94,16.55) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (22.94,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_6_/Q (SDFFARX1_RVT) 0.0753 1.0000 0.3434 0.3434 r (26.12,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n12 (net) 2 1.8732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/SI (SDFFARX1_RVT) 0.0753 1.0000 0.0000 0.3435 r (19.14,16.03) 0.7500 (rail VDD) - data arrival time 0.3435 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.75,16.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2767 99.4733 - data required time 99.4733 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4733 - data arrival time -0.3435 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1298 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.75,16.20) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.75,16.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_7_/Q (SDFFARX1_RVT) 0.0745 1.0000 0.3427 0.3427 r (22.93,15.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n11 (net) 2 1.8173 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/SI (SDFFARX1_RVT) 0.0745 1.0000 0.0000 0.3427 r (18.38,13.37) 0.7500 (rail VDD) - data arrival time 0.3427 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.99,13.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2764 99.4736 - data required time 99.4736 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4736 - data arrival time -0.3427 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1309 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (26.59,9.86) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (26.59,9.86) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/Q (SDFFARX1_RVT) 0.0739 1.0000 0.3420 0.3420 r (29.77,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n7 (net) 2 1.7718 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/SI (SDFFARX1_RVT) 0.0739 1.0000 0.0000 0.3420 r (28.26,13.37) 0.7500 (rail VDD) - data arrival time 0.3420 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.87,13.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.2762 99.4738 - data required time 99.4738 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4738 - data arrival time -0.3420 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1318 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_1_/QN (SDFFARX1_RVT) 0.1168 1.0000 0.2394 0.2394 f (45.49,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n7 (net) 4 3.6771 - U0_UART_TX/U0_fsm/current_state_reg_0_/SI (SDFFARX1_RVT) 0.1168 1.0000 0.0000 0.2394 f (41.49,3.34) 0.7500 (rail VDD) - data arrival time 0.2394 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,3.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3248 99.4252 - data required time 99.4252 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4252 - data arrival time -0.2394 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1858 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (23.70,29.58) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (23.70,29.58) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/QN (SDFFARX1_RVT) 0.1140 1.0000 0.2364 0.2364 f (27.10,28.93) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/dftopt7 (net) 4 3.4747 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/SI (SDFFARX1_RVT) 0.1140 1.0000 0.0000 0.2364 f (28.57,33.44) 0.7500 (rail VDD) - data arrival time 0.2364 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,33.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3236 99.4264 - data required time 99.4264 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4264 - data arrival time -0.2364 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1899 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_stp_chk/stp_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.71,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_2_/QN (SDFFARX1_RVT) 0.1128 1.0000 0.2351 0.2351 f (39.11,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/test_so (net) 4 3.3892 - U0_UART_RX/U0_stp_chk/stp_err_reg/SI (SDFFARX1_RVT) 0.1128 1.0000 0.0000 0.2351 f (41.18,26.75) 0.7500 (rail VDD) - data arrival time 0.2351 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_stp_chk/stp_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.79,26.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3232 99.4268 - data required time 99.4268 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4268 - data arrival time -0.2351 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1917 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (37.08,23.24) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (37.08,23.24) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_1_/QN (SDFFARX1_RVT) 0.1125 1.0000 0.2348 0.2348 f (40.47,23.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n13 (net) 3 3.3672 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/SI (SDFFARX1_RVT) 0.1125 1.0000 0.0000 0.2348 f (35.71,20.06) 0.7500 (rail VDD) - data arrival time 0.2348 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.32,19.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3230 99.4270 - data required time 99.4270 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4270 - data arrival time -0.2348 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1922 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (23.70,32.92) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (23.70,32.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_0_/QN (SDFFARX1_RVT) 0.1099 1.0000 0.2321 0.2321 f (27.10,32.27) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/dftopt8 (net) 3 3.1848 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/SI (SDFFARX1_RVT) 0.1099 1.0000 0.0000 0.2321 f (28.72,29.41) 0.7500 (rail VDD) - data arrival time 0.2321 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_uart_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.33,29.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3220 99.4280 - data required time 99.4280 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4280 - data arrival time -0.2321 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.1959 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.31,22.89) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.31,22.89) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/QN (SDFFARX1_RVT) 0.1043 1.0000 0.2260 0.2260 f (27.71,22.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n14 (net) 3 2.7807 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/SI (SDFFARX1_RVT) 0.1043 1.0000 0.0000 0.2260 f (24.31,23.41) 0.7500 (rail VDD) - data arrival time 0.2260 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.92,23.24) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3197 99.4303 - data required time 99.4303 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4303 - data arrival time -0.2260 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2042 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (15.80,3.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (15.80,3.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/QN (SDFFARX1_RVT) 0.1027 1.0000 0.2242 0.2242 f (19.19,3.82) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt10 (net) 1 2.6620 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/SI (SDFFARX1_RVT) 0.1027 1.0000 0.0001 0.2243 f (19.38,26.75) 0.7500 (rail VDD) - data arrival time 0.2243 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.78,26.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3198 99.4302 - data required time 99.4303 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4303 - data arrival time -0.2243 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2059 - - - - Startpoint: U0_UART_TX/U0_fsm/current_state_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,3.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/current_state_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,3.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/current_state_reg_0_/QN (SDFFARX1_RVT) 0.1030 1.0000 0.2246 0.2246 f (45.49,3.82) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/n8 (net) 3 2.6857 - U0_UART_TX/U0_fsm/busy_reg/SI (SDFFARX1_RVT) 0.1030 1.0000 0.0000 0.2246 f (39.45,6.00) 0.7500 (rail VDD) - data arrival time 0.2246 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (38.84,6.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3192 99.4308 - data required time 99.4308 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4308 - data arrival time -0.2246 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2062 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.78,26.58) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.78,26.58) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_1_/QN (SDFFARX1_RVT) 0.1022 1.0000 0.2238 0.2238 f (15.38,27.23) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n2 (net) 2 2.6308 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/SI (SDFFARX1_RVT) 0.1022 1.0000 0.0000 0.2238 f (17.47,30.09) 0.7500 (rail VDD) - data arrival time 0.2238 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.08,29.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3189 99.4311 - data required time 99.4311 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4311 - data arrival time -0.2238 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2073 - - - - Startpoint: U0_UART_RX/U0_uart_fsm/current_state_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_strt_chk/strt_glitch_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.17,33.27) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/current_state_reg_1_/QN (SDFFARX1_RVT) 0.0915 1.0000 0.2121 0.2121 f (32.57,33.92) 0.7500 (rail VDD) - U0_UART_RX/U0_uart_fsm/dftopt0 (net) 2 1.8759 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/SI (SDFFARX1_RVT) 0.0915 1.0000 0.0000 0.2121 f (29.63,36.10) 0.7500 (rail VDD) - data arrival time 0.2121 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.24,36.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3145 99.4355 - data required time 99.4355 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4355 - data arrival time -0.2121 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2234 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_mux/OUT_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,19.89) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_2_/QN (SDFFARX1_RVT) 0.0909 1.0000 0.2114 0.2114 f (45.49,20.54) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt5 (net) 2 1.8411 - U0_UART_TX/U0_mux/OUT_reg/SI (SDFFARX1_RVT) 0.0909 1.0000 0.0000 0.2114 f (41.49,16.72) 0.7500 (rail VDD) - data arrival time 0.2114 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_mux/OUT_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3143 99.4357 - data required time 99.4357 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4357 - data arrival time -0.2114 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2243 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.08,29.92) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.08,29.92) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_0_/QN (SDFFARX1_RVT) 0.0904 1.0000 0.2107 0.2107 f (21.48,30.57) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n1 (net) 2 1.8051 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/SI (SDFFARX1_RVT) 0.0904 1.0000 0.0000 0.2107 f (23.10,29.41) 0.7500 (rail VDD) - data arrival time 0.2107 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (23.70,29.58) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3141 99.4359 - data required time 99.4359 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4359 - data arrival time -0.2107 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2252 - - - - Startpoint: U0_UART_RX/U0_data_sampling/Samples_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.46,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_data_sampling/Samples_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.46,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/Samples_reg_0_/QN (SDFFARX1_RVT) 0.0879 1.0000 0.2078 0.2078 f (27.86,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/n55 (net) 2 1.6462 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/SI (SDFFARX1_RVT) 0.0879 1.0000 0.0000 0.2078 f (24.46,43.47) 0.7500 (rail VDD) - data arrival time 0.2078 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (25.07,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3131 99.4369 - data required time 99.4369 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4369 - data arrival time -0.2078 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2291 - - - - Startpoint: U0_UART_RX/U0_par_chk/par_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,29.92) 0.7500 (rail VDD) - - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,29.92) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/par_err_reg/QN (SDFFARX1_RVT) 0.0877 1.0000 0.2076 0.2076 f (45.49,30.57) 0.7500 (rail VDD) - U0_UART_RX/U0_par_chk/test_so (net) 1 1.6360 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/SI (SDFFARX1_RVT) 0.0877 1.0000 0.0000 0.2076 f (36.47,23.41) 0.7500 (rail VDD) - data arrival time 0.2076 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/ser_count_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (37.08,23.24) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3130 99.4370 - data required time 99.4370 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4370 - data arrival time -0.2076 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2293 - - - - Startpoint: U0_UART_TX/U0_Serializer/ser_count_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/ser_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/ser_count_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.32,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/ser_count_reg_0_/QN (SDFFARX1_RVT) 0.0871 1.0000 0.2068 0.2068 f (39.72,20.54) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n14 (net) 2 1.5926 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/SI (SDFFARX1_RVT) 0.0871 1.0000 0.0000 0.2068 f (41.49,20.06) 0.7500 (rail VDD) - data arrival time 0.2068 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/ser_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,19.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3127 99.4373 - data required time 99.4373 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4373 - data arrival time -0.2068 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2305 - - - - Startpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (25.07,43.30) 0.7500 (rail VDD) - - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (25.07,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/Samples_reg_1_/QN (SDFFARX1_RVT) 0.0850 1.0000 0.2044 0.2044 f (28.47,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/dftopt1 (net) 2 1.4616 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/SI (SDFFARX1_RVT) 0.0850 1.0000 0.0000 0.2044 f (29.94,43.47) 0.7500 (rail VDD) - data arrival time 0.2044 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.54,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3119 99.4381 - data required time 99.4381 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4381 - data arrival time -0.2044 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2337 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.93,19.89) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (29.93,19.89) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/QN (SDFFARX1_RVT) 0.0837 1.0000 0.2028 0.2028 f (33.33,20.54) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/dftopt0 (net) 1 1.3767 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/SI (SDFFARX1_RVT) 0.0837 1.0000 0.0000 0.2028 f (23.70,22.72) 0.7500 (rail VDD) - data arrival time 0.2028 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.31,22.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3114 99.4386 - data required time 99.4386 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4386 - data arrival time -0.2028 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2358 - - - - Startpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.87,13.20) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.87,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/DATA_V_reg_1_/QN (SDFFARX1_RVT) 0.0823 1.0000 0.2011 0.2011 f (32.27,13.85) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/n28 (net) 1 1.2868 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/SI (SDFFARX1_RVT) 0.0823 1.0000 0.0000 0.2011 f (29.33,20.06) 0.7500 (rail VDD) - data arrival time 0.2011 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.93,19.89) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3108 99.4392 - data required time 99.4392 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4392 - data arrival time -0.2011 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2381 - - - - Startpoint: U0_UART_TX/U0_parity_calc/parity_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.62,16.55) 0.7500 (rail VDD) - - U0_UART_TX/U0_parity_calc/parity_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (36.62,16.55) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/parity_reg/QN (SDFFARX1_RVT) 0.0822 1.0000 0.2011 0.2011 f (40.02,17.20) 0.7500 (rail VDD) - U0_UART_TX/U0_parity_calc/test_so (net) 1 1.2843 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/SI (SDFFARX1_RVT) 0.0822 1.0000 0.0000 0.2011 f (34.50,13.37) 0.7500 (rail VDD) - data arrival time 0.2011 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.10,13.20) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3108 99.4392 - data required time 99.4392 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4392 - data arrival time -0.2011 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2381 - - - - Startpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.01,36.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.01,36.27) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/Samples_reg_2_/QN (SDFFARX1_RVT) 0.0821 1.0000 0.2010 0.2010 f (27.40,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_data_sampling/dftopt4 (net) 1 1.2783 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/SI (SDFFARX1_RVT) 0.0821 1.0000 0.0000 0.2010 f (17.62,36.78) 0.7500 (rail VDD) - data arrival time 0.2010 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.23,36.61) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3107 99.4393 - data required time 99.4393 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4393 - data arrival time -0.2010 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2383 - - - - Startpoint: U0_UART_RX/U0_strt_chk/strt_glitch_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (30.24,36.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_strt_chk/strt_glitch_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (30.24,36.27) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/strt_glitch_reg/QN (SDFFARX1_RVT) 0.0817 1.0000 0.2004 0.2004 f (33.63,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_strt_chk/test_so (net) 1 1.2506 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/SI (SDFFARX1_RVT) 0.0817 1.0000 0.0000 0.2005 f (23.40,36.10) 0.7500 (rail VDD) - data arrival time 0.2005 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (24.01,36.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3106 99.4394 - data required time 99.4394 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4394 - data arrival time -0.2005 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2390 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.61) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/QN (SDFFARX1_RVT) 0.0816 1.0000 0.2004 0.2004 f (45.49,38.96) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n48 (net) 1 1.2461 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/SI (SDFFARX1_RVT) 0.0816 1.0000 0.0000 0.2004 f (38.45,36.10) 0.7500 (rail VDD) - data arrival time 0.2004 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (39.06,36.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3105 99.4395 - data required time 99.4395 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4395 - data arrival time -0.2004 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2391 - - - - Startpoint: U0_UART_TX/U0_fsm/busy_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_fsm/busy_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (38.84,6.17) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/busy_reg/QN (SDFFARX1_RVT) 0.0809 1.0000 0.1996 0.1996 f (35.44,5.52) 0.7500 (rail VDD) - U0_UART_TX/U0_fsm/dftopt1 (net) 1 1.2035 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/SI (SDFFARX1_RVT) 0.0809 1.0000 0.0000 0.1996 f (28.11,3.34) 0.7500 (rail VDD) - data arrival time 0.1996 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (28.72,3.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3103 99.4397 - data required time 99.4397 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4397 - data arrival time -0.1996 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2402 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.72,3.17) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (28.72,3.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_3_/QN (SDFFARX1_RVT) 0.0804 1.0000 0.1989 0.1989 f (32.12,3.82) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n37 (net) 1 1.1695 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/SI (SDFFARX1_RVT) 0.0804 1.0000 0.0000 0.1990 f (25.83,6.69) 0.7500 (rail VDD) - data arrival time 0.1990 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.44,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3101 99.4399 - data required time 99.4400 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4400 - data arrival time -0.1990 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2410 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.92,23.24) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (24.92,23.24) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/QN (SDFFARX1_RVT) 0.0801 1.0000 0.1985 0.1985 f (28.32,23.89) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/dftopt1 (net) 1 1.1465 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/SI (SDFFARX1_RVT) 0.0801 1.0000 0.0000 0.1985 f (28.57,16.72) 0.7500 (rail VDD) - data arrival time 0.1985 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (29.17,16.55) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3099 99.4401 - data required time 99.4401 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4401 - data arrival time -0.1985 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2416 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (16.56,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (16.56,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/QN (SDFFARX1_RVT) 0.0798 1.0000 0.1982 0.1982 f (19.95,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n34 (net) 1 1.1278 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/SI (SDFFARX1_RVT) 0.0798 1.0000 0.0000 0.1982 f (15.19,3.34) 0.7500 (rail VDD) - data arrival time 0.1982 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (15.80,3.17) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3098 99.4402 - data required time 99.4402 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4402 - data arrival time -0.1982 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2420 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.53,43.30) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.53,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_5_/QN (SDFFARX1_RVT) 0.0797 1.0000 0.1981 0.1981 f (21.93,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/test_so_gOb3 (net) 1 1.1261 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/SI (SDFFARX1_RVT) 0.0797 1.0000 0.0000 0.1982 f (17.02,40.13) 0.7500 (rail VDD) - data arrival time 0.1982 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (17.62,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3098 99.4402 - data required time 99.4402 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4402 - data arrival time -0.1982 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2421 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,43.30) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/QN (SDFFARX1_RVT) 0.0794 1.0000 0.1978 0.1978 f (45.49,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n49 (net) 1 1.1074 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/SI (SDFFARX1_RVT) 0.0794 1.0000 0.0000 0.1978 f (41.49,40.13) 0.7500 (rail VDD) - data arrival time 0.1978 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3097 99.4403 - data required time 99.4404 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4404 - data arrival time -0.1978 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2425 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (30.54,43.30) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (30.54,43.30) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_1_/QN (SDFFARX1_RVT) 0.0793 1.0000 0.1976 0.1976 f (33.94,43.95) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n51 (net) 1 1.1000 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/SI (SDFFARX1_RVT) 0.0793 1.0000 0.0000 0.1977 f (29.48,40.13) 0.7500 (rail VDD) - data arrival time 0.1977 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (30.09,39.96) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3096 99.4404 - data required time 99.4404 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4404 - data arrival time -0.1977 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2427 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (37.23,36.61) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (37.23,36.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_5_/QN (SDFFARX1_RVT) 0.0792 1.0000 0.1975 0.1975 f (40.63,37.26) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n47 (net) 1 1.0938 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/SI (SDFFARX1_RVT) 0.0792 1.0000 0.0000 0.1975 f (41.49,43.47) 0.7500 (rail VDD) - data arrival time 0.1975 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,43.30) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3096 99.4404 - data required time 99.4404 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4404 - data arrival time -0.1975 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2429 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.23,36.61) 0.7500 (rail VDD) - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (18.23,36.61) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/QN (SDFFARX1_RVT) 0.0790 1.0000 0.1973 0.1973 f (21.63,37.26) 0.7500 (rail VDD) - U0_UART_RX/U0_edge_bit_counter/n53 (net) 1 1.0812 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/SI (SDFFARX1_RVT) 0.0790 1.0000 0.0000 0.1973 f (18.08,33.44) 0.7500 (rail VDD) - data arrival time 0.1973 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (18.69,33.27) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3095 99.4405 - data required time 99.4405 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4405 - data arrival time -0.1973 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2432 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (34.95,9.86) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (34.95,9.86) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_1_/QN (SDFFARX1_RVT) 0.0790 1.0000 0.1973 0.1973 f (38.35,10.51) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n39 (net) 1 1.0812 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/SI (SDFFARX1_RVT) 0.0790 1.0000 0.0000 0.1973 f (34.80,6.69) 0.7500 (rail VDD) - data arrival time 0.1973 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (35.41,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3095 99.4405 - data required time 99.4405 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4405 - data arrival time -0.1973 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2432 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_5_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.77,9.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (17.77,9.52) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_5_/QN (SDFFARX1_RVT) 0.0790 1.0000 0.1972 0.1972 f (21.17,8.87) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/n35 (net) 1 1.0784 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/SI (SDFFARX1_RVT) 0.0790 1.0000 0.0000 0.1973 f (15.95,6.69) 0.7500 (rail VDD) - data arrival time 0.1973 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_Serializer/DATA_V_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (16.56,6.52) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3095 99.4405 - data required time 99.4405 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4405 - data arrival time -0.1973 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2433 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_parity_calc/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (26.44,6.52) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (26.44,6.52) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_4_/QN (SDFFARX1_RVT) 0.0782 1.0000 0.1963 0.1963 f (29.83,7.17) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt8 (net) 1 1.0267 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/SI (SDFFARX1_RVT) 0.0782 1.0000 0.0000 0.1963 f (25.98,10.03) 0.7500 (rail VDD) - data arrival time 0.1963 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_parity_calc/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (26.59,9.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3091 99.4409 - data required time 99.4409 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4409 - data arrival time -0.1963 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2446 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_par_chk/par_err_reg (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (41.94,32.92) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (41.94,32.92) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/QN (SDFFARX1_RVT) 0.0770 1.0000 0.1948 0.1948 f (45.34,32.27) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/test_so (net) 1 0.9558 - U0_UART_RX/U0_par_chk/par_err_reg/SI (SDFFARX1_RVT) 0.0770 1.0000 0.0000 0.1948 f (41.49,30.09) 0.7500 (rail VDD) - data arrival time 0.1948 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_par_chk/par_err_reg/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,29.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3087 99.4413 - data required time 99.4413 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4413 - data arrival time -0.1948 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2465 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.96) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (42.10,39.96) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_2_/QN (SDFFARX1_RVT) 0.0760 1.0000 0.1934 0.1934 f (45.49,40.61) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n50 (net) 1 0.8931 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/SI (SDFFARX1_RVT) 0.0760 1.0000 0.0000 0.1934 f (41.49,39.44) 0.7500 (rail VDD) - data arrival time 0.1934 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_4_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (42.10,39.61) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3083 99.4417 - data required time 99.4417 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4417 - data arrival time -0.1934 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2483 - - - - Startpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 32.0677 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (39.06,36.27) 0.7500 (rail VDD) - - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (39.06,36.27) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/QN (SDFFARX1_RVT) 0.0760 1.0000 0.1933 0.1933 f (42.45,35.62) 0.7500 (rail VDD) - U0_UART_RX/U0_deserializer/n46 (net) 1 0.8900 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/SI (SDFFARX1_RVT) 0.0760 1.0000 0.0000 0.1933 f (41.34,32.75) 0.7500 (rail VDD) - data arrival time 0.1933 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U0_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.30,18.96) 0.7500 (rail VDD) - U0_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.80,18.89) 0.7500 (rail VDD) - U0_mux2X1/OUT (net) 28 27.8088 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (41.94,32.92) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3083 99.4417 - data required time 99.4418 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4418 - data arrival time -0.1933 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2484 - - - - Startpoint: U0_UART_TX/U0_Serializer/DATA_V_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_TX/U0_fsm/current_state_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Fanout Cap Trans Derate Incr Path Location Voltage - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - clock SCAN_CLK (rise edge) 0.0000 0.0000 - source latency 0.0000 0.0000 - scan_clk (in) 0.0000 1.0000 0.0000 0.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.9165 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 0.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 27.7732 - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.10,13.20) 0.7500 (rail VDD) - - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 0.0000 r (35.10,13.20) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/DATA_V_reg_0_/QN (SDFFARX1_RVT) 0.0757 1.0000 0.1930 0.1930 f (38.50,13.85) 0.7500 (rail VDD) - U0_UART_TX/U0_Serializer/dftopt0 (net) 1 0.8740 - U0_UART_TX/U0_fsm/current_state_reg_2_/SI (SDFFARX1_RVT) 0.0757 1.0000 0.0000 0.1930 f (35.41,12.69) 0.7500 (rail VDD) - data arrival time 0.1930 - - clock SCAN_CLK (rise edge) 100.0000 100.0000 - source latency 0.0000 100.0000 - scan_clk (in) 0.0000 1.0000 0.0000 100.0000 r (18.81,0.14) 0.7500 - scan_clk (net) 2 2.7844 - U1_mux2X1/U1/A2 (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (20.21,5.58) 0.7500 (rail VDD) - U1_mux2X1/U1/Y (MUX21X2_RVT) 0.0000 1.0000 0.0000 100.0000 r (19.70,5.51) 0.7500 (rail VDD) - U1_mux2X1/OUT (net) 25 23.8503 - U0_UART_TX/U0_fsm/current_state_reg_2_/CLK (SDFFARX1_RVT) 0.0000 1.0000 0.0000 100.0000 r (36.01,12.86) 0.7500 (rail VDD) - - clock uncertainty -0.2500 99.7500 - library setup time 1.0000 -0.3082 99.4418 - data required time 99.4418 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - data required time 99.4418 - data arrival time -0.1930 - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - slack (MET) 99.2489 - - -1 diff --git a/pnr/reports/Placement/report_utilization.rpt b/pnr/reports/Placement/report_utilization.rpt deleted file mode 100644 index 35fa35e..0000000 --- a/pnr/reports/Placement/report_utilization.rpt +++ /dev/null @@ -1,24 +0,0 @@ -**************************************** -Report : report_utilization -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:09:16 2024 -**************************************** -Utilization Ratio: 0.7146 -Utilization options: - - Area calculation based on: site_row of block UART - - Categories of objects excluded: hard_macros macro_keepouts soft_macros io_cells hard_blockages -Total Area: 1785.3616 -Total Capacity Area: 1785.3616 -Total Area of cells: 1275.8029 -Area of excluded objects: - - hard_macros : 0.0000 - - macro_keepouts : 0.0000 - - soft_macros : 0.0000 - - io_cells : 0.0000 - - hard_blockages : 0.0000 - -Utilization of site-rows with: - - Site 'unit': 0.7146 - -0.7146 diff --git a/pnr/reports/Powerplanning/check_pg_connectivity.rpt b/pnr/reports/Powerplanning/check_pg_connectivity.rpt deleted file mode 100644 index d467573..0000000 --- a/pnr/reports/Powerplanning/check_pg_connectivity.rpt +++ /dev/null @@ -1,32 +0,0 @@ -Loading cell instances... -Number of Standard Cells: 0 -Number of Macro Cells: 0 -Number of IO Pad Cells: 0 -Number of Blocks: 0 -Loading P/G wires and vias... -Number of VDD Wires: 23 -Number of VDD Vias: 25 -Number of VDD Terminals: 0 -Number of VSS Wires: 25 -Number of VSS Vias: 36 -Number of VSS Terminals: 0 -**************Verify net VDD connectivity***************** - Number of floating wires: 13 - Number of floating vias: 0 - Number of floating std cells: 0 - Number of floating hard macros: 0 - Number of floating I/O pads: 0 - Number of floating terminals: 0 - Number of floating hierarchical blocks: 0 -************************************************************ -**************Verify net VSS connectivity***************** - Number of floating wires: 13 - Number of floating vias: 0 - Number of floating std cells: 0 - Number of floating hard macros: 0 - Number of floating I/O pads: 0 - Number of floating terminals: 0 - Number of floating hierarchical blocks: 0 -************************************************************ -Overall runtime: 0 seconds. -{PATH_11_25 PATH_11_24 PATH_11_23 PATH_11_22 PATH_11_21 PATH_11_20 PATH_11_19 PATH_11_18 PATH_11_17 PATH_11_16 PATH_11_15 PATH_11_14 PATH_11_13 PATH_11_12 PATH_11_11 PATH_11_10 PATH_11_9 PATH_11_8 PATH_11_7 PATH_11_6 PATH_11_5 PATH_11_4 PATH_11_3 PATH_11_2 PATH_11_1 PATH_11_0} diff --git a/pnr/reports/Powerplanning/check_pg_drc.rpt b/pnr/reports/Powerplanning/check_pg_drc.rpt deleted file mode 100644 index c7a468c..0000000 --- a/pnr/reports/Powerplanning/check_pg_drc.rpt +++ /dev/null @@ -1,5 +0,0 @@ -Command check_pg_drc started at Wed Apr 24 18:08:00 2024 -Command check_pg_drc finished at Wed Apr 24 18:08:00 2024 -CPU usage for check_pg_drc: 0.00 seconds ( 0.00 hours) -Elapsed time for check_pg_drc: 0.00 seconds ( 0.00 hours) -No errors found. diff --git a/pnr/reports/Powerplanning/check_pg_missing_vias.rpt b/pnr/reports/Powerplanning/check_pg_missing_vias.rpt deleted file mode 100644 index 8b22b0a..0000000 --- a/pnr/reports/Powerplanning/check_pg_missing_vias.rpt +++ /dev/null @@ -1,7 +0,0 @@ -Check net VDD vias... -Number of missing vias: 0 -Checking net VDD vias took 0 seconds. -Check net VSS vias... -Number of missing vias: 0 -Checking net VSS vias took 0 seconds. -Overall runtime: 0 seconds. diff --git a/pnr/reports/Powerplanning/report_qor.summary.rpt b/pnr/reports/Powerplanning/report_qor.summary.rpt deleted file mode 100644 index 0d7eb7d..0000000 --- a/pnr/reports/Powerplanning/report_qor.summary.rpt +++ /dev/null @@ -1,26 +0,0 @@ -**************************************** -Report : qor - -summary - -include { setup } -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:08:00 2024 -**************************************** -Information: The stitching and editing of coupling caps is turned OFF for design 'UART.dlib:UART.design'. (TIM-125) -Warning: Technology layer 'MRDL' setting 'routing-direction' is not valid (NEX-001) -Information: Design Average RC for design UART (NEX-011) -Information: r = 1.791249 ohm/um, via_r = 0.506541 ohm/cut, c = 0.071288 ff/um, cc = 0.000000 ff/um (X dir) (NEX-017) -Information: r = 1.785715 ohm/um, via_r = 0.618909 ohm/cut, c = 0.081781 ff/um, cc = 0.000000 ff/um (Y dir) (NEX-017) -Information: The RC mode used is VR for design 'UART'. (NEX-022) -Information: Update timing completed net estimation for all the timing graph nets (TIM-111) -Information: Net estimation statistics: timing graph nets = 435, routed nets = 0, across physical hierarchy nets = 0, parasitics cached nets = 5, delay annotated nets = 0, parasitics annotated nets = 0, multi-voltage nets = 0. (TIM-112) - -Timing ---------------------------------------------------------------------------- -Context WNS TNS NVE ---------------------------------------------------------------------------- -Design (Setup) 97.27 0.00 0 - ---------------------------------------------------------------------------- - -1 diff --git a/pnr/reports/Powerplanning/report_timing.rpt b/pnr/reports/Powerplanning/report_timing.rpt deleted file mode 100644 index 464db4c..0000000 --- a/pnr/reports/Powerplanning/report_timing.rpt +++ /dev/null @@ -1,238 +0,0 @@ -**************************************** -Report : timing - -path_type full - -delay_type max - -max_paths 5 - -report_by design -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:08:00 2024 -**************************************** - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (ideal) 0.00 0.00 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) - 0.00 0.00 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) - 0.44 0.44 r - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.13 0.57 f - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.24 0.81 r - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.14 0.96 r - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) - 0.20 1.16 f - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.29 1.45 f - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.24 1.69 f - U0_UART_RX/U0_data_sampling/U28/Y (NOR4X0_RVT) 0.27 1.97 r - U0_UART_RX/U0_data_sampling/U27/Y (MUX21X1_RVT) - 0.21 2.17 f - U0_UART_RX/U0_data_sampling/Samples_reg_2_/D (SDFFARX1_RVT) - 0.00 2.17 f - data arrival time 2.17 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (ideal) 0.00 100.00 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) - 0.00 100.00 r - clock uncertainty -0.25 99.75 - library setup time -0.31 99.44 - data required time 99.44 - ------------------------------------------------------------------------ - data required time 99.44 - data arrival time -2.17 - ------------------------------------------------------------------------ - slack (MET) 97.27 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (ideal) 0.00 0.00 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/CLK (SDFFARX1_RVT) - 0.00 0.00 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_2_/Q (SDFFARX1_RVT) - 0.44 0.44 r - U0_UART_RX/U0_data_sampling/U50/Y (INVX0_RVT) 0.13 0.57 f - U0_UART_RX/U0_data_sampling/U49/Y (XOR2X1_RVT) 0.24 0.81 r - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.14 0.96 r - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) - 0.20 1.16 f - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.29 1.45 f - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.24 1.69 f - U0_UART_RX/U0_data_sampling/U37/Y (MUX21X1_RVT) - 0.22 1.92 f - U0_UART_RX/U0_data_sampling/Samples_reg_1_/D (SDFFARX1_RVT) - 0.00 1.92 f - data arrival time 1.92 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (ideal) 0.00 100.00 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) - 0.00 100.00 r - clock uncertainty -0.25 99.75 - library setup time -0.31 99.44 - data required time 99.44 - ------------------------------------------------------------------------ - data required time 99.44 - data arrival time -1.92 - ------------------------------------------------------------------------ - slack (MET) 97.52 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (ideal) 0.00 0.00 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) - 0.00 0.00 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) - 0.45 0.45 r - U0_UART_RX/U0_edge_bit_counter/U52/Y (XNOR2X1_RVT) - 0.31 0.76 r - U0_UART_RX/U0_edge_bit_counter/U53/Y (NAND3X0_RVT) - 0.12 0.88 f - U0_UART_RX/U0_edge_bit_counter/U59/Y (NOR4X0_RVT) - 0.35 1.23 r - U0_UART_RX/U0_edge_bit_counter/U36/Y (OR2X1_RVT) - 0.14 1.37 r - U0_UART_RX/U0_edge_bit_counter/U6/Y (INVX1_RVT) - 0.12 1.48 f - U0_UART_RX/U0_edge_bit_counter/U27/Y (AO21X1_RVT) - 0.15 1.63 f - U0_UART_RX/U0_edge_bit_counter/U24/Y (AO21X1_RVT) - 0.11 1.74 f - U0_UART_RX/U0_edge_bit_counter/U22/Y (AO22X1_RVT) - 0.17 1.91 f - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/D (SDFFARX1_RVT) - 0.00 1.91 f - data arrival time 1.91 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (ideal) 0.00 100.00 - U0_UART_RX/U0_edge_bit_counter/bit_count_reg_2_/CLK (SDFFARX1_RVT) - 0.00 100.00 r - clock uncertainty -0.25 99.75 - library setup time -0.30 99.45 - data required time 99.45 - ------------------------------------------------------------------------ - data required time 99.45 - data arrival time -1.91 - ------------------------------------------------------------------------ - slack (MET) 97.54 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (ideal) 0.00 0.00 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) - 0.00 0.00 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) - 0.45 0.45 r - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.31 0.76 r - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.12 0.88 f - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.34 1.22 r - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.25 1.47 f - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.26 1.72 r - U0_UART_RX/U0_deserializer/U16/Y (AO22X1_RVT) 0.20 1.92 r - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/D (SDFFARX1_RVT) - 0.00 1.92 r - data arrival time 1.92 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (ideal) 0.00 100.00 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) - 0.00 100.00 r - clock uncertainty -0.25 99.75 - library setup time -0.28 99.47 - data required time 99.47 - ------------------------------------------------------------------------ - data required time 99.47 - data arrival time -1.92 - ------------------------------------------------------------------------ - slack (MET) 97.55 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_0_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (ideal) 0.00 0.00 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) - 0.00 0.00 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) - 0.45 0.45 r - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.31 0.76 r - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.12 0.88 f - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.34 1.22 r - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.25 1.47 f - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.26 1.72 r - U0_UART_RX/U0_deserializer/U3/Y (AO22X1_RVT) 0.19 1.91 r - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/D (SDFFARX1_RVT) - 0.00 1.91 r - data arrival time 1.91 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (ideal) 0.00 100.00 - U0_UART_RX/U0_deserializer/P_DATA_reg_0_/CLK (SDFFARX1_RVT) - 0.00 100.00 r - clock uncertainty -0.25 99.75 - library setup time -0.28 99.47 - data required time 99.47 - ------------------------------------------------------------------------ - data required time 99.47 - data arrival time -1.91 - ------------------------------------------------------------------------ - slack (MET) 97.56 - - -1 diff --git a/pnr/reports/Routing/check_legality.rpt b/pnr/reports/Routing/check_legality.rpt deleted file mode 100644 index 65da976..0000000 --- a/pnr/reports/Routing/check_legality.rpt +++ /dev/null @@ -1,110 +0,0 @@ - -************************ - -running check_legality - -Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -PDC app_options settings ========= - place.legalize.enable_prerouted_net_check: 1 - place.legalize.num_tracks_for_access_check: 1 - place.legalize.use_eol_spacing_for_access_check: 0 - place.legalize.allow_touch_track_for_access_check: 1 - place.legalize.reduce_conservatism_in_eol_check: 0 - place.legalize.preroute_shape_merge_distance: 0.0 - place.legalize.enable_non_preferred_direction_span_check: 0 - -Layer M1: cached 0 shapes out of 402 total shapes. -Layer M2: cached 0 shapes out of 1765 total shapes. -Cached 0 vias out of 2782 total vias. - -check_legality for block design UART ... -Warning: Routing direction of metal layer PO is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Warning: Routing direction of metal layer MRDL is neither "horizontal" nor "vertical". PDC checks will not be performed on this layer. (PDC-003) -Design has no advanced rules -Checking legality -Checking cell legality: -0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% -Sorting rows. -Checking spacing rule legality. -0%....10%....20%....30%....40%....50%....60%....70%....80%....90%....100% -Checking packing rule legality. - - -**************************************** - Report : Legality -**************************************** - -VIOLATIONS BY CATEGORY: - MOVABLE APP-FIXED USER-FIXED DESCRIPTION - 0 0 0 Two objects overlap. - 0 0 0 A cell violates a pnet. - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell is not aligned with a site. - 0 0 0 A cell has an illegal orientation. - 0 0 0 A cell spacing rule is violated. - 0 0 0 A layer rule is violated. - 0 0 0 A cell is in the wrong region. - 0 0 0 Two cells violate cts margins. - 0 0 0 Two cells violate coloring. - - 0 0 0 TOTAL - -TOTAL 0 Violations. - -VIOLATIONS BY SUBCATEGORY: - MOVABLE APP-FIXED USER-FIXED DESCRIPTION - - 0 0 0 Two objects overlap. - 0 0 0 Two cells overlap. - 0 0 0 Two cells have overlapping keepout margins. - 0 0 0 A cell overlaps a blockage. - 0 0 0 A cell keepout margin overlaps a blockage. - - 0 0 0 A cell violates a pnet. - - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell violates pin-track alignment rules. - 0 0 0 A cell is illegal at a site. - 0 0 0 A cell violates legal index rule. - 0 0 0 A cell has the wrong variant for its location. - - 0 0 0 A cell is not aligned with a site. - 0 0 0 A cell is not aligned with the base site. - 0 0 0 A cell is not aligned with an overlaid site. - - 0 0 0 A cell has an illegal orientation. - - 0 0 0 A cell spacing rule is violated. - 0 0 0 A spacing rule is violated in a row. - 0 0 0 A spacing rule is violated between adjacent rows. - 0 0 0 A cell violates vertical abutment rule. - 0 0 0 A cell violates metal spacing rule. - - 0 0 0 A layer rule is violated. - 0 0 0 A layer VTH rule is violated. - 0 0 0 A layer OD rule is violated. - 0 0 0 A layer OD max-width rule is violated. - 0 0 0 A layer ALL_OD corner rule is violated. - 0 0 0 A layer max-vertical-length rule is violated. - 0 0 0 A layer TPO rule is violated. - 0 0 0 Filler cell insertion cannot satisfy layer rules. - - 0 0 0 A cell is in the wrong region. - 0 0 0 A cell is outside its hard bound. - 0 0 0 A cell is in the wrong voltage area. - 0 0 0 A cell violates an exclusive movebound. - - 0 0 0 Two cells violate cts margins. - - 0 0 0 Two cells violate coloring. - - -check_legality for block design UART succeeded! - - -check_legality succeeded. - -************************** - -1 diff --git a/pnr/reports/Routing/check_lvs.rpt b/pnr/reports/Routing/check_lvs.rpt deleted file mode 100644 index 226504e..0000000 --- a/pnr/reports/Routing/check_lvs.rpt +++ /dev/null @@ -1,39 +0,0 @@ -Information: Using 1 threads for LVS -[Check Short] Stage 1 Elapsed = 0:00:00, CPU = 0:00:00 -[Check Short] Stage 1-2 Elapsed = 0:00:00, CPU = 0:00:00 -[Check Short] Stage 2 Elapsed = 0:00:00, CPU = 0:00:00 -[Check Short] Stage 2-2 Elapsed = 0:00:00, CPU = 0:00:00 -[Check Short] Stage 3 Elapsed = 0:00:00, CPU = 0:00:00 -[Check Short] End Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] Init Elapsed = 0:00:00, CPU = 0:00:00 -Warning: Port VDD have no valid pin shapes. Skip this port. (RT-203) -Warning: Port VSS have no valid pin shapes. Skip this port. (RT-203) -[Check Net] 10% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 20% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 30% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 40% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 50% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 60% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 70% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 80% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] 90% Elapsed = 0:00:00, CPU = 0:00:00 -[Check Net] All nets are submitted. -[Check Net] 100% Elapsed = 0:00:00, CPU = 0:00:00 -Information: Detected floating route violation for Net VDD. BBox: (3.0000 3.0000)(45.7120 44.8000). (RT-587) -Information: Detected open violation for Net VSS. BBox: (3.0000 4.1050)(45.7120 44.8300). (RT-585) -Information: Detected floating route violation for Net VSS. BBox: (3.0000 3.0000)(45.7120 44.8000). (RT-587) -Information: Detected open violation for Net VDD. BBox: (3.0000 2.9700)(45.7120 43.9860). (RT-585) - -=============================================================== - Maximum number of violations is set to 20 - Abort checking when more than 20 violations are found - All violations might not be found. -=============================================================== -Total number of input nets is 441. -Total number of short violations is 0. -Total number of open nets is 2. -Open nets are VDD VSS -Total number of floating route violations is 2. - -Elapsed = 0:00:00, CPU = 0:00:00 -1 diff --git a/pnr/reports/Routing/check_routes.rpt b/pnr/reports/Routing/check_routes.rpt deleted file mode 100644 index 0cf51ea..0000000 --- a/pnr/reports/Routing/check_routes.rpt +++ /dev/null @@ -1,230 +0,0 @@ -Warning: Layer MRDL does not have a preferred direction, assigning to vertical. (ZRT-025) -Found antenna rule mode 4, diode mode 2: - layer M1: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M2: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M3: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M4: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M5: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M6: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M7: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M8: max ratio 1000, diode ratio {0.06 0 400 40000} - layer M9: max ratio 1000, diode ratio {0.06 0 8000 50000} - layer MRDL: max ratio 1000, diode ratio {0 0 1 0 0} - layer CO: , diode ratio {0 0 1 0 0} - layer VIA1: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA2: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA3: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA4: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA5: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA6: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA7: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIA8: max ratio 20, diode ratio {0.06 0 200 1000} - layer VIARDL: max ratio 20, diode ratio {0 0 1 0 0} -Cell Min-Routing-Layer = M1 -Cell Max-Routing-Layer = M8 -Warning: Cannot find a default contact code for layer CO. (ZRT-022) -Warning: Ignore 2 top cell ports with no pins. (ZRT-027) -Info: number of net_type_blockage: 0 - - -Start checking for open nets ... - -Total number of nets = 441, of which 0 are not extracted -Total number of open nets = 0, of which 0 are frozen - -Check 441 nets, 0 have Errors - -[CHECK OPEN NETS] Elapsed real time: 0:00:00 -[CHECK OPEN NETS] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 -[CHECK OPEN NETS] Stage (MB): Used 0 Alloctr 0 Proc 0 -[CHECK OPEN NETS] Total (MB): Used 78 Alloctr 80 Proc 1740 -Printing options for 'route.common.*' -common.verbose_level : 0 - -Printing options for 'route.detail.*' -detail.antenna : true -detail.antenna_fixing_preference : use_diodes -detail.diode_libcell_names : */ANTENNA_RVT -detail.force_end_on_preferred_grid : true -detail.optimize_wire_via_effort_level : high -detail.save_after_iterations : 2 -detail.timing_driven : true - -Printing options for 'route.auto_via_ladder.*' - -*****Start reporting antenna related parameters***** - Antenna/diode mode: - Antenna mode 4; diode mode 2 - Metal lay (M1)0; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA1)1; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M2)1; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA2)2; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M3)2; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA3)3; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M4)3; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA4)4; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M5)4; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA5)5; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M6)5; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA6)6; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M7)6; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA7)7; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M8)7; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 400.000 40000.000 0.000) - Cut lay (VIA8)8; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 200.000 1000.000 0.000) - Metal lay (M9)8; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.060 0.000 8000.000 50000.000 0.000) - Cut lay (VIARDL)9; maxRatio 20.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.000 0.000 1.000 0.000 0.000) - Metal lay (MRDL)9; maxRatio 1000.000 maxPRatio 2147483648.000 maxNRatio 2147483648.000; vector (0.000 0.000 1.000 0.000 0.000) - Accumulate from metal to cut == false - Accumulate from cut to metal == false - Top lay antenna ratio fix threshold == -1 - Antenna max pin count threshold == -1 - Check PG net == false - MergeGate == true - Break antenna to port mode == float - Break antenna to macro pin mode == normal -*****End reporting antenna related parameters***** -Warning: Skipping antenna analysis for net RST. The pin RST on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_CLK. The pin TX_CLK on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net RX_CLK. The pin RX_CLK on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net RX_IN_S. The pin RX_IN_S on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[7]. The pin TX_IN_P[7] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[6]. The pin TX_IN_P[6] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[5]. The pin TX_IN_P[5] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[4]. The pin TX_IN_P[4] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[3]. The pin TX_IN_P[3] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[2]. The pin TX_IN_P[2] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[1]. The pin TX_IN_P[1] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_P[0]. The pin TX_IN_P[0] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net TX_IN_V. The pin TX_IN_V on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net Prescale[5]. The pin Prescale[5] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net Prescale[4]. The pin Prescale[4] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net Prescale[3]. The pin Prescale[3] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net Prescale[2]. The pin Prescale[2] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net Prescale[1]. The pin Prescale[1] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net Prescale[0]. The pin Prescale[0] on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net parity_enable. The pin parity_enable on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net parity_type. The pin parity_type on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net SI. The pin SI on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net SE. The pin SE on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net scan_clk. The pin scan_clk on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net scan_rst. The pin scan_rst on cell UART does not have enough gate area information. (ZRT-311) -Warning: Skipping antenna analysis for net test_mode. The pin test_mode on cell UART does not have enough gate area information. (ZRT-311) -Skipping antenna analysis for 26 nets as they don't have enough gate area info. - -Begin full DRC check ... - -Information: Using 1 threads for routing. (ZRT-444) -Checked 1/1 Partitions, Violations = 0 -[DRC CHECK] Elapsed real time: 0:00:00 -[DRC CHECK] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 -[DRC CHECK] Stage (MB): Used 0 Alloctr 0 Proc 0 -[DRC CHECK] Total (MB): Used 93 Alloctr 95 Proc 1740 -Start net based rule analysis -Found 0 antenna instance ports -End net based rule analysis -[Antenna analysis] Elapsed real time: 0:00:00 -[Antenna analysis] Elapsed cpu time: sys=0:00:00 usr=0:00:00 total=0:00:00 -[Antenna analysis] Stage (MB): Used 0 Alloctr 0 Proc 0 -[Antenna analysis] Total (MB): Used 93 Alloctr 96 Proc 1740 - -DRC-SUMMARY: - @@@@@@@ TOTAL VIOLATIONS = 0 - - -Total Wire Length = 4218 micron -Total Number of Contacts = 2721 -Total Number of Wires = 2721 -Total Number of PtConns = 442 -Total Number of Routed Wires = 2721 -Total Routed Wire Length = 4164 micron -Total Number of Routed Contacts = 2721 - Layer M1 : 163 micron - Layer M2 : 1779 micron - Layer M3 : 1717 micron - Layer M4 : 466 micron - Layer M5 : 78 micron - Layer M6 : 14 micron - Layer M7 : 0 micron - Layer M8 : 0 micron - Layer M9 : 0 micron - Layer MRDL : 0 micron - Via VIA56SQ_C : 5 - Via VIA45SQ_C(rot) : 22 - Via VIA45LG_C : 2 - Via VIA34SQ_C : 170 - Via VIA34SQ_C(rot) : 1 - Via VIA34LG_C : 1 - Via VIA23SQ_C : 2 - Via VIA23SQ_C(rot) : 1130 - Via VIA23LG_C(rot) : 1 - Via VIA12SQ_C : 1255 - Via VIA12SQ_C(rot) : 74 - Via VIA12BAR_C : 22 - Via VIA12BAR(rot) : 2 - Via VIA12SQ_C_2x1 : 34 - - -Redundant via conversion report: --------------------------------- - - Total optimized via conversion rate = 1.25% (34 / 2721 vias) - - Layer VIA1 = 2.45% (34 / 1387 vias) - Weight 1 = 2.45% (34 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 97.55% (1353 vias) - Layer VIA2 = 0.00% (0 / 1133 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (1133 vias) - Layer VIA3 = 0.00% (0 / 172 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (172 vias) - Layer VIA4 = 0.00% (0 / 24 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (24 vias) - Layer VIA5 = 0.00% (0 / 5 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (5 vias) - - Total double via conversion rate = 1.25% (34 / 2721 vias) - - Layer VIA1 = 2.45% (34 / 1387 vias) - Layer VIA2 = 0.00% (0 / 1133 vias) - Layer VIA3 = 0.00% (0 / 172 vias) - Layer VIA4 = 0.00% (0 / 24 vias) - Layer VIA5 = 0.00% (0 / 5 vias) - - The optimized via conversion rate based on total routed via count = 1.25% (34 / 2721 vias) - - Layer VIA1 = 2.45% (34 / 1387 vias) - Weight 1 = 2.45% (34 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 97.55% (1353 vias) - Layer VIA2 = 0.00% (0 / 1133 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (1133 vias) - Layer VIA3 = 0.00% (0 / 172 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (172 vias) - Layer VIA4 = 0.00% (0 / 24 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (24 vias) - Layer VIA5 = 0.00% (0 / 5 vias) - Un-optimized = 0.00% (0 vias) - Un-mapped = 100.00% (5 vias) - - - -Verify Summary: - -Total number of nets = 441, of which 0 are not extracted -Total number of open nets = 0, of which 0 are frozen -Total number of excluded ports = 0 ports of 0 unplaced cells connected to 0 nets - 0 ports without pins of 0 cells connected to 0 nets - 0 ports of 0 cover cells connected to 0 non-pg nets -Total number of DRCs = 0 -Total number of antenna violations = 0 -Total number of tie to rail violations = not checked -Total number of tie to rail directly violations = not checked - - diff --git a/pnr/reports/Routing/report_constraints_max_capacitance.rpt b/pnr/reports/Routing/report_constraints_max_capacitance.rpt deleted file mode 100644 index bfa2fef..0000000 --- a/pnr/reports/Routing/report_constraints_max_capacitance.rpt +++ /dev/null @@ -1,30 +0,0 @@ -**************************************** -Report : constraint - -verbose - -all_violators - -max_capacitance -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 17:52:49 2024 -**************************************** - - - - - Total number of violation(s): 0 -1 -**************************************** -Report : constraint - -verbose - -all_violators - -max_capacitance -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:23:23 2024 -**************************************** - - - - - Total number of violation(s): 0 -1 diff --git a/pnr/reports/Routing/report_constraints_max_transition.rpt b/pnr/reports/Routing/report_constraints_max_transition.rpt deleted file mode 100644 index 0c3d4c7..0000000 --- a/pnr/reports/Routing/report_constraints_max_transition.rpt +++ /dev/null @@ -1,15 +0,0 @@ -**************************************** -Report : constraint - -verbose - -all_violators - -max_transition -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:23:23 2024 -**************************************** - - - - - Total number of violation(s): 0 -1 diff --git a/pnr/reports/Routing/report_qor.rpt b/pnr/reports/Routing/report_qor.rpt deleted file mode 100644 index 690a812..0000000 --- a/pnr/reports/Routing/report_qor.rpt +++ /dev/null @@ -1,24 +0,0 @@ -**************************************** -Report : qor - -summary -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:23:23 2024 -**************************************** -Information: Timer using 'SI, Timing Window Analysis, CRPR'. (TIM-050) - -Timing ---------------------------------------------------------------------------- -Context WNS TNS NVE ---------------------------------------------------------------------------- -Design (Setup) 97.29 0.00 0 - -Design (Hold) 0.29 0.00 0 ---------------------------------------------------------------------------- - -Miscellaneous ---------------------------------------------------------------------------- -Cell Area (netlist): 1279.87 -Cell Area (netlist and physical only): 1279.87 -Nets with DRC Violations: 0 -1 diff --git a/pnr/reports/Routing/report_timing.rpt b/pnr/reports/Routing/report_timing.rpt deleted file mode 100644 index bac0a0d..0000000 --- a/pnr/reports/Routing/report_timing.rpt +++ /dev/null @@ -1,234 +0,0 @@ -**************************************** -Report : timing - -path_type full - -delay_type max - -max_paths 5 - -report_by design -Design : UART -Version: O-2018.06-SP1 -Date : Wed Apr 24 18:23:23 2024 -**************************************** -Information: Timer using 'SI, Timing Window Analysis, CRPR'. (TIM-050) - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_2_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (propagated) 0.31 0.31 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) - 0.00 0.31 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/Q (SDFFARX1_RVT) - 0.55 0.86 r - U0_UART_RX/U0_data_sampling/U53/Y (INVX0_RVT) 0.12 0.98 f - U0_UART_RX/U0_data_sampling/U52/Y (XOR2X1_RVT) 0.25 1.23 r - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.13 1.35 r - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) - 0.20 1.55 f - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.29 1.84 f - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.25 2.09 f - U0_UART_RX/U0_data_sampling/U28/Y (NOR4X0_RVT) 0.29 2.37 r - U0_UART_RX/U0_data_sampling/U27/Y (MUX21X1_RVT) - 0.20 2.57 f - U0_UART_RX/U0_data_sampling/Samples_reg_2_/D (SDFFARX1_RVT) - 0.01 2.58 f - data arrival time 2.58 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (propagated) 0.28 100.28 - clock reconvergence pessimism 0.03 100.31 - U0_UART_RX/U0_data_sampling/Samples_reg_2_/CLK (SDFFARX1_RVT) - 0.00 100.31 r - clock uncertainty -0.20 100.11 - library setup time -0.24 99.87 - data required time 99.87 - ------------------------------------------------------------------------ - data required time 99.87 - data arrival time -2.58 - ------------------------------------------------------------------------ - slack (MET) 97.29 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_data_sampling/Samples_reg_1_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (propagated) 0.31 0.31 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/CLK (SDFFARX1_RVT) - 0.00 0.31 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_3_/Q (SDFFARX1_RVT) - 0.55 0.86 r - U0_UART_RX/U0_data_sampling/U53/Y (INVX0_RVT) 0.12 0.98 f - U0_UART_RX/U0_data_sampling/U52/Y (XOR2X1_RVT) 0.25 1.23 r - U0_UART_RX/U0_data_sampling/U48/Y (AND3X1_RVT) 0.13 1.35 r - U0_UART_RX/U0_data_sampling/U47/Y (NAND4X0_RVT) - 0.20 1.55 f - U0_UART_RX/U0_data_sampling/U39/Y (AND4X1_RVT) 0.29 1.84 f - U0_UART_RX/U0_data_sampling/U38/Y (AND4X1_RVT) 0.25 2.09 f - U0_UART_RX/U0_data_sampling/U37/Y (MUX21X1_RVT) - 0.24 2.33 f - U0_UART_RX/U0_data_sampling/Samples_reg_1_/D (SDFFARX1_RVT) - 0.00 2.33 f - data arrival time 2.33 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (propagated) 0.28 100.28 - clock reconvergence pessimism 0.03 100.31 - U0_UART_RX/U0_data_sampling/Samples_reg_1_/CLK (SDFFARX1_RVT) - 0.00 100.31 r - clock uncertainty -0.20 100.11 - library setup time -0.24 99.87 - data required time 99.87 - ------------------------------------------------------------------------ - data required time 99.87 - data arrival time -2.33 - ------------------------------------------------------------------------ - slack (MET) 97.54 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_7_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (propagated) 0.31 0.31 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) - 0.00 0.31 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) - 0.55 0.86 r - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.29 1.15 r - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.10 1.25 f - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.33 1.58 r - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.24 1.82 f - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.25 2.07 r - U0_UART_RX/U0_deserializer/U16/Y (AO22X1_RVT) 0.19 2.26 r - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/D (SDFFARX1_RVT) - 0.00 2.26 r - data arrival time 2.26 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (propagated) 0.28 100.28 - clock reconvergence pessimism 0.03 100.31 - U0_UART_RX/U0_deserializer/P_DATA_reg_7_/CLK (SDFFARX1_RVT) - 0.00 100.31 r - clock uncertainty -0.20 100.11 - library setup time -0.24 99.87 - data required time 99.87 - ------------------------------------------------------------------------ - data required time 99.87 - data arrival time -2.26 - ------------------------------------------------------------------------ - slack (MET) 97.61 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_3_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (propagated) 0.31 0.31 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) - 0.00 0.31 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) - 0.55 0.86 r - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.29 1.15 r - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.10 1.25 f - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.33 1.58 r - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.24 1.82 f - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.25 2.07 r - U0_UART_RX/U0_deserializer/U8/Y (AO22X1_RVT) 0.18 2.25 r - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/D (SDFFARX1_RVT) - 0.01 2.25 r - data arrival time 2.25 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (propagated) 0.28 100.28 - clock reconvergence pessimism 0.03 100.31 - U0_UART_RX/U0_deserializer/P_DATA_reg_3_/CLK (SDFFARX1_RVT) - 0.00 100.31 r - clock uncertainty -0.20 100.11 - library setup time -0.24 99.87 - data required time 99.87 - ------------------------------------------------------------------------ - data required time 99.87 - data arrival time -2.25 - ------------------------------------------------------------------------ - slack (MET) 97.62 - - - - Startpoint: U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Endpoint: U0_UART_RX/U0_deserializer/P_DATA_reg_6_ (rising edge-triggered flip-flop clocked by SCAN_CLK) - Mode: default - Corner: default - Scenario: default - Path Group: SCAN_CLK - Path Type: max - - Point Incr Path - ------------------------------------------------------------------------ - clock SCAN_CLK (rise edge) 0.00 0.00 - clock network delay (propagated) 0.31 0.31 - - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/CLK (SDFFARX1_RVT) - 0.00 0.31 r - U0_UART_RX/U0_edge_bit_counter/edge_count_reg_4_/Q (SDFFARX1_RVT) - 0.55 0.86 r - U0_UART_RX/U0_deserializer/U37/Y (XNOR2X1_RVT) 0.29 1.15 r - U0_UART_RX/U0_deserializer/U38/Y (NAND3X0_RVT) 0.10 1.25 f - U0_UART_RX/U0_deserializer/U44/Y (NOR4X0_RVT) 0.33 1.58 r - U0_UART_RX/U0_deserializer/U9/Y (NAND2X0_RVT) 0.24 1.82 f - U0_UART_RX/U0_deserializer/U5/Y (INVX1_RVT) 0.25 2.07 r - U0_UART_RX/U0_deserializer/U14/Y (AO22X1_RVT) 0.17 2.24 r - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/D (SDFFARX1_RVT) - 0.01 2.25 r - data arrival time 2.25 - - clock SCAN_CLK (rise edge) 100.00 100.00 - clock network delay (propagated) 0.28 100.28 - clock reconvergence pessimism 0.03 100.31 - U0_UART_RX/U0_deserializer/P_DATA_reg_6_/CLK (SDFFARX1_RVT) - 0.00 100.31 r - clock uncertainty -0.20 100.11 - library setup time -0.24 99.87 - data required time 99.87 - ------------------------------------------------------------------------ - data required time 99.87 - data arrival time -2.25 - ------------------------------------------------------------------------ - slack (MET) 97.62 - - -1 diff --git a/pnr/scripts/ndr.tcl b/pnr/scripts/ndr.tcl deleted file mode 100644 index 9d18571..0000000 --- a/pnr/scripts/ndr.tcl +++ /dev/null @@ -1,38 +0,0 @@ -set CTS_NDR_MIN_ROUTING_LAYER "M4" -set CTS_NDR_MAX_ROUTING_LAYER "M5" -set CTS_LEAF_NDR_MIN_ROUTING_LAYER "M1" -set CTS_LEAF_NDR_MAX_ROUTING_LAYER "M5" -set CTS_NDR_RULE_NAME "cts_w2_s2_vlg" -set CTS_LEAF_NDR_RULE_NAME "cts_w1_s2" - - - create_routing_rule $CTS_NDR_RULE_NAME \ - -default_reference_rule \ - -widths { M1 0.1 M2 0.11 M3 0.11 M4 0.11 M5 0.11 } \ - -spacings { M2 0.16 M3 0.45 M4 0.45 M5 1.1 } \ - -spacing_length_thresholds {M2 3.0 M3 3.0 M4 4.0 M5 4.0} \ - -taper_distance 0.4 \ - -driver_taper_distance 0.4 \ - -cuts { \ - { VIA1 {V1LG 1} } \ - { VIA2 {V2LG 1} } \ - { VIA3 {V3LG 1} } \ - { VIA4 {V4LG 1} } \ - { VIA5 {V5LG 1} } \ - } - - set_clock_routing_rules -rules $CTS_NDR_RULE_NAME \ - -min_routing_layer $CTS_NDR_MIN_ROUTING_LAYER \ - -max_routing_layer $CTS_NDR_MAX_ROUTING_LAYER - - - - - create_routing_rule $CTS_LEAF_NDR_RULE_NAME \ - -default_reference_rule \ - -spacings { M2 0.16 M3 0.45 M4 0.45 M5 1.1 } - - set_clock_routing_rules -net_type sink -rules $CTS_LEAF_NDR_RULE_NAME \ - -min_routing_layer $CTS_LEAF_NDR_MIN_ROUTING_LAYER \ - -max_routing_layer $CTS_LEAF_NDR_MAX_ROUTING_LAYER - diff --git a/pnr/scripts/power_network.tcl b/pnr/scripts/power_network.tcl deleted file mode 100644 index a64dea4..0000000 --- a/pnr/scripts/power_network.tcl +++ /dev/null @@ -1,49 +0,0 @@ -### connect pg -connect_pg_net -automatic - -### remove before create -remove_pg_strategies -all -remove_pg_patterns -all -remove_pg_regions -all -remove_pg_via_master_rules -all -remove_pg_strategy_via_rules -all -remove_routes -net_types {power ground} -ring -stripe -lib_cell_pin_connect > /dev/null - -set_pg_via_master_rule pgvia_2x3 -via_array_dimension {2 3} - -################################################################################ -# Build the main power mesh and ring. -################################################################################ - -#define region for pg -create_pg_region r -core - -create_pg_mesh_pattern mesh \ - -layers { \ - { {horizontal_layer: M7} {width: 0.5} {spacing: interleaving} {pitch: 8} {offset: 1} } \ - { {vertical_layer: M8} {width: 0.5} {spacing: interleaving} {pitch: 8} {offset: 1} } \ - } \ - -via_rule { {intersection: adjacent} {via_master : pgvia_2x3} } - -set_pg_strategy s_mesh \ - -pg_regions {r} \ - -pattern { {name: mesh} {nets:{VSS VDD}}} - - - compile_pg -strategies {s_mesh} - -################################################################################ -# Build the standard cell rails -################################################################################ - -# rail pattern -create_pg_std_cell_conn_pattern -layers M1 P_std_cell_rail - -set_pg_strategy S_std_cell_rail \ - -core \ - -pattern {{pattern: P_std_cell_rail}{nets: {VSS VDD}}} - -set_pg_strategy_via_rule S_via_stdcellrail \ - -via_rule {{intersection: adjacent}{via_master: default}} - -compile_pg -strategies {S_std_cell_rail} -via_rule {S_via_stdcellrail}