From 9ac8b3107f548bec0ef2d8bd56d4c440a7446c07 Mon Sep 17 00:00:00 2001
From: AMR_KHALID_SALAH <84184457+amrkhalid-star902@users.noreply.github.com>
Date: Thu, 24 Aug 2023 10:14:00 +0300
Subject: [PATCH] Update AXI_Master.v

---
 AXI/AXI_Master.v | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/AXI/AXI_Master.v b/AXI/AXI_Master.v
index e2a2042..5a589d9 100644
--- a/AXI/AXI_Master.v
+++ b/AXI/AXI_Master.v
@@ -1,6 +1,7 @@
-
 `timescale 1ns / 1ps
 
+
+
 module AXI_Master#(
 
 parameter DATAW   = 32, 
@@ -33,8 +34,8 @@ parameter MEMSIZE = 4096
     output reg               WVALID,
     
     //Signals of the Write Response channel
-    input                    BID,
-    input                    BRESP,
+    input [(DATAW/8)-1 : 0]  BID,
+    input [SIZE-2 : 0]       BRESP,
     input                    BVALID,
     output reg               BREADY,
     
@@ -51,7 +52,7 @@ parameter MEMSIZE = 4096
     //Signals of the Read Data channels
     output reg [(DATAW/8)-1 : 0] RID,
     input [DATAW-1 : 0]      RDATA,
-    input                    RRESP,
+    input [SIZE-2 : 0]       RRESP,
     input                    RLAST,
     input                    RVALID,
     output reg               RREADY,
@@ -1030,7 +1031,8 @@ parameter MEMSIZE = 4096
         endcase
      
      end
-  
+
+    
 endmodule