Hey there! I geek into microarchitectural concepts and floss over performance enhancements in the architectural scheme! FOSS & RISCV! Join the Revolution.
- Bangalore, Karnataka
- in/aakarsh-vinay-039154210
- @aakarsh_vinay
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pes_karatsuba_multiplier Public
This repo includes all the files related to the design of a 32-bit multiplier invigorated with the Karatsuba Algorithm on Hardware Description Language SystemVerilog.
Verilog UpdatedNov 27, 2023 -
TapeoutSzn Public
The road to tapeout is real. Welcome to my assignment hub! Physical Design w/ASICs Aug-Dec'23
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100DaysOfTLV Public
Hey There! Welcome to my journey of dissecting and exploring the corners of Transaction Level Verilog HDL! 100 days of building and experimenting!
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MPI-Memento Public
Involves a brief list of Message Passing Interface (MPI) programs I had worked on in my Summer School at IIT Palakkad, June 2023.
C GNU General Public License v3.0 UpdatedAug 14, 2023 -
ai-aes Public
Forked from skudlur/ai-aesThis is a submission for Efabless AI Generated Design Contest.
MIT License UpdatedMay 29, 2023 -
diablo Public
Forked from skudlur/diablodiablo is an Out-Of-Order 64-bit RISC-V processor
SystemVerilog MIT License UpdatedMay 29, 2023 -
Ripes Public
Forked from mortbopet/RipesA graphical processor simulator and assembly editor for the RISC-V ISA
C++ MIT License UpdatedApr 25, 2023