Need some explaination for this patch of code

[mr-yamraj]

Can you please explain how exactly this part of the code works
This is a screenshot from [link]

I am not able to get how exactly out_buffer is calculated.
There must be some calculations done to calculate the out buffer. So how those are done here. Here in this code, in the in_buffer we store the X_data and we change the bits of some registers and get output in out_buffer.
From what I have read till now in the documentation. I think it is something done while making the overlay.
So if that is the case then I am not able to find tutorials for making a custom overlay for my Machine Learning Model.

[rpokana]

Hi Yamraj,

As you have figured out, the data processing is happening in the overlay and written back to out_buffer at the allocated location in DDR via DMAs.

You can check the functionality of the overlay by using Xilinx Vivado tool and sourcing the overlay.tcl provided in "spooNN/mnist-cnn/deploy/" location.

Now if you want to change this overlay, the bd can be tweaked by adding another IP or RTL design sources to achieve the processing you need. Once the bd is validated, you can generate a new overlay bitstream. Here are some of the videos which could be of help to generate custom overlays:

https://www.youtube.com/watch?v=UBsCNPWudww&t=398s
https://www.youtube.com/watch?v=LomArt-hi4M

If you do not have access to Xilinx tools, you can think of using existing overlays and building the python software to solve a different problem.

Hope this helps. Let us know if you have further queries.

Cheers!
Radhika

[rpokana]

@mr-yamraj , If you are just looking for understanding out_buffer computation implemented in the overlay, do look at the source code at:
https://github.com/fpgasystems/spooNN/blob/master/mnist-cnn/hls/mnist-cnn-1W5A.cpp

[mr-yamraj]

If I just do this by multiplying numpy matrix and applying activation function. Then that will be ineffective right.
What all existing overlays that you can suggest to do the matrix multiplication and other computation.

[rpokana]

Yes that is the reason this matrix multiply cpp kernel is targeted to Xilinx FPGA to achieve compute efficiency.

You can check for different neural network implementations from pynq community: https://www.pynq.io/community.html

For ex:
QNN overlay from Xilinx labs is here:
https://github.com/Xilinx/QNN-MO-PYNQ/tree/master/qnn/bitstreams/pynqZ1-Z2