PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

Must-have verilog systemverilog modules

Various HDL (Verilog) IP Cores

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Verilog SDRAM memory controller

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

xk265：HEVC/H.265 Video Encoder IP Core (RTL)

Opensource DDR3 Controller

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

Basic Peripheral SoC (SPI, GPIO, Timer, UART)

FPGA implementation of deflate (de)compress RFC 1950/1951

A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very …

USB Full Speed PHY

An open source FPGA PCI core & 8250-Compatible PCI UART core

This repository is used to release the Labs of Computer Architecture Course from USTC

Code for "Computer Architecture" in 2020 Spring.

【例程】国产高云FPGA 开发板及其工程

Groundhog - Serial ATA Host Bus Adapter

【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板

How to use the Intel JTAG primitive without using virtual JTAG

Improved version of https://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v

An AES cipher chip supporting 128/256 ECB mode with 8-bit half-duplex data bus, being taped out using SMIC 130nm process.

Altera MAX II EPM1270 development board and more