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fix broken msg passing in wishbone master for (fix #692) #693

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merged 2 commits into from
Nov 23, 2020

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slaweksiluk
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Sławomir Siluk added 2 commits November 12, 2020 18:52
Fails on modelsim, but working properly on ghdl.
@@ -22,7 +22,7 @@ def encode(tb_cfg):


def gen_wb_tests(obj, *args):
for dat_width, num_cycles, strobe_prob, ack_prob, stall_prob in product(*args):
for dat_width, num_cycles, strobe_prob, ack_prob, stall_prob, slave_inst in product(*args):
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I would use slave_comb instead of slave_inst, since my understanding is that the difference between the two cases is whether the slave is combinatorial or registered.

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The idea is to have possibility to skip wb slave VC instantiation and drive wishbone slave signals directly. It makes possible to test various corner cases - like here when specific set of acknowledge logic lead to crash on modelsim, but not ghdl. I thinks it's not feasible to add this corner cases reproducers to wishbone slave as it will obfuscate code. This is all about wb master VC bug.



TB_WISHBONE_MASTER = LIB.test_bench("tb_wishbone_master")

for test in TB_WISHBONE_MASTER.get_tests():
gen_wb_tests(test, [8, 32], [1, 64], [0.3, 1.0], [0.3, 1.0], [0.4, 0.0])
if test.name == "slave comb ack":
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I'm not sure to understand this. Why is the combinatorial version tested with one set of params but the other one is tested with two?

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slave comb ack test case doesn't need/cannot have random stimulus

stall => stall,
ack => ack
);
slave_gen : if tb_cfg.slave_inst generate
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Would it make sense for comb to be an option (generic) of the wishbone slave, instead of using a generate in the testbench?

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as described in first comment IMHO: no, it would not

@eine eine changed the title Fix broken msg passing in wishbone master for #692 fix broken msg passing in wishbone master for (fix #692) Nov 23, 2020
@eine eine merged commit f87a6ec into VUnit:master Nov 23, 2020
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2 participants