diff --git a/.github/workflows/action_tools.yml b/.github/workflows/action_tools.yml
index 92fe4c45227..72ea1db6bd0 100644
--- a/.github/workflows/action_tools.yml
+++ b/.github/workflows/action_tools.yml
@@ -8,7 +8,7 @@ on:
- cron: '0 16 1 * *'
push:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
@@ -18,7 +18,7 @@ on:
- '**/*.cpp'
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
diff --git a/.github/workflows/action_utest.yml b/.github/workflows/action_utest.yml
index 99690a6e488..8a5245955bd 100644
--- a/.github/workflows/action_utest.yml
+++ b/.github/workflows/action_utest.yml
@@ -8,14 +8,14 @@ on:
- cron: '0 16 1 * *'
push:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml
index 3bdc0c76506..7268ccf603d 100644
--- a/.github/workflows/bsp_buildings.yml
+++ b/.github/workflows/bsp_buildings.yml
@@ -8,14 +8,14 @@ on:
- cron: '0 16 * * *'
push:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
@@ -37,14 +37,17 @@ jobs:
fail-fast: false
matrix:
legs:
- - RTT_BSP: "RT-Thread Online Packages"
+ - RTT_BSP: "RT-Thread Online Packages (STM32F407 RT-Spark)"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
- "stm32/stm32f407-rt-spark"
- - RTT_BSP: "RTduino/Arduino Libraries"
+ - RTT_BSP: "RTduino/Arduino Libraries (STM32F412 Nucleo)"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
- "stm32/stm32f412-st-nucleo"
+ - RTT_BSP: "RTduino/Arduino Libraries (Raspberry Pico)"
+ RTT_TOOL_CHAIN: "sourcery-arm"
+ SUB_RTT_BSP:
- "raspberry-pico"
- RTT_BSP: "others_at32_hc32"
RTT_TOOL_CHAIN: "sourcery-arm"
@@ -136,6 +139,7 @@ jobs:
- "stm32/stm32f401-weact-blackpill"
- "stm32/stm32f405-smdz-breadfruit"
- "stm32/stm32f407-armfly-v5"
+ - "stm32/stm32f407-lckfb-skystar"
- "stm32/stm32f407-atk-explorer"
- "stm32/stm32f407-robomaster-c"
- "stm32/stm32f407-st-discovery"
@@ -176,6 +180,7 @@ jobs:
- "stm32/stm32h750-artpi"
- "stm32/stm32h750-weact-ministm32h7xx"
- "stm32/stm32h750-fk750m1-vbt6"
+ - "stm32/stm32h7s7-st-disco"
- "stm32/stm32mp157a-st-discovery"
- "stm32/stm32mp157a-st-ev1"
- "stm32/stm32u575-st-nucleo"
@@ -218,6 +223,7 @@ jobs:
- "renesas/ra8m1-ek"
- "renesas/ra8d1-ek"
- "renesas/ra8d1-vision-board"
+ - "renesas/rzt2m_rsk"
- "frdm-k64f"
- "xplorer4330/M4"
- RTT_BSP: "gd32_n32_apm32"
diff --git a/.github/workflows/compile_bsp_with_drivers.yml b/.github/workflows/compile_bsp_with_drivers.yml
index 634eab49bb0..0062a4ac86f 100644
--- a/.github/workflows/compile_bsp_with_drivers.yml
+++ b/.github/workflows/compile_bsp_with_drivers.yml
@@ -15,14 +15,14 @@ name: BSP compilation with more drivers
on:
push:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
diff --git a/.github/workflows/doxygen.yml b/.github/workflows/doxygen.yml
index 934a07eab7a..56fbd31bf73 100644
--- a/.github/workflows/doxygen.yml
+++ b/.github/workflows/doxygen.yml
@@ -5,14 +5,14 @@ on:
- cron: '0 16 30 * *'
push:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- bsp/**
diff --git a/.github/workflows/file_check.yml b/.github/workflows/file_check.yml
index 2959db7e585..b4d7de3f124 100644
--- a/.github/workflows/file_check.yml
+++ b/.github/workflows/file_check.yml
@@ -3,7 +3,7 @@ name: Check File Format and License
on:
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml
index 7658f948c0a..f3b4186b640 100644
--- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml
+++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml
@@ -126,6 +126,8 @@ jobs:
#- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题
- {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evk"}
- {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evkmini"}
+ - {RTT_BSP_NAME: "ht32f12366", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f12366"}
+ - {RTT_BSP_NAME: "ht32f52352", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f52352"}
#- {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchain还没支持
- {RTT_BSP_NAME: "imx6sx_cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6sx/cortex-a9"}
- {RTT_BSP_NAME: "imx6ul", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6ul"}
diff --git a/.github/workflows/pkgs_test.yml b/.github/workflows/pkgs_test.yml
index 87e70fb35ca..63921920139 100644
--- a/.github/workflows/pkgs_test.yml
+++ b/.github/workflows/pkgs_test.yml
@@ -3,14 +3,14 @@ name: pkgs_test
on:
push:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
diff --git a/.github/workflows/spell_check.yml b/.github/workflows/spell_check.yml
index af0942c2783..c77b5f946bb 100644
--- a/.github/workflows/spell_check.yml
+++ b/.github/workflows/spell_check.yml
@@ -3,12 +3,12 @@ name: Check Spelling
on:
push:
branches:
- - master
+ - v5.1.x
paths:
- 'documentation/**'
pull_request:
branches:
- - master
+ - v5.1.x
paths:
- 'documentation/**'
jobs:
diff --git a/.github/workflows/static_code_analysis.yml b/.github/workflows/static_code_analysis.yml
index 025e458517d..8143dbd90e5 100644
--- a/.github/workflows/static_code_analysis.yml
+++ b/.github/workflows/static_code_analysis.yml
@@ -3,7 +3,7 @@ name: Static code analysis
on:
pull_request:
branches:
- - master
+ - v5.1.x
paths-ignore:
- documentation/**
- '**/README.md'
diff --git a/README.md b/README.md
index 2ed689db2bb..ba3f1ab16f3 100644
--- a/README.md
+++ b/README.md
@@ -144,7 +144,7 @@ RT-Thread is very grateful for the support from all community developers, and if
# Contribution
-If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](documentation/contribution_guide/contribution_guide.md).
+If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](.github/CONTRIBUTING.md).
## Thanks for the following contributors!
diff --git a/README_de.md b/README_de.md
index 5ce4b2f0105..f57408dc31e 100644
--- a/README_de.md
+++ b/README_de.md
@@ -144,4 +144,4 @@ RT-Thread ist sehr dankbar für die Unterstützung durch alle Entwickler der Com
# Beitrag
-Wenn Sie an RT-Thread interessiert sind und sich an der Entwicklung von RT-Thread beteiligen und einen Beitrag zum Code leisten wollen, lesen Sie bitte den [Code Contribution Guide](documentation/contribution_guide/contribution_guide.md).
+Wenn Sie an RT-Thread interessiert sind und sich an der Entwicklung von RT-Thread beteiligen und einen Beitrag zum Code leisten wollen, lesen Sie bitte den [Code Contribution Guide](.github/CONTRIBUTING.md).
diff --git a/README_es.md b/README_es.md
index 82794aa034e..455dd0c30f1 100644
--- a/README_es.md
+++ b/README_es.md
@@ -143,4 +143,4 @@ RT-Thread está muy agradecido por el apoyo de todos los desarrolladores de la c
# Contribución
-Si estás interesado en RT-Thread y quieres unirte al desarrollo de RT-Thread y convertirte en un contribuidor de código, por favor consulta la [Guía de Contribución de Código.](documentation/contribution_guide/contribution_guide.md).
+Si estás interesado en RT-Thread y quieres unirte al desarrollo de RT-Thread y convertirte en un contribuidor de código, por favor consulta la [Guía de Contribución de Código.](.github/CONTRIBUTING.md).
diff --git a/bsp/CME_M7/project.uvproj b/bsp/CME_M7/project.uvproj
index ad342552a15..af9d6f73376 100644
--- a/bsp/CME_M7/project.uvproj
+++ b/bsp/CME_M7/project.uvproj
@@ -543,6 +543,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1147,93 +1166,93 @@
Libraries
- cmem7_efuse.c
+ cmem7_i2c.c
1
- StdPeriph_Driver\src\cmem7_efuse.c
+ StdPeriph_Driver\src\cmem7_i2c.c
- cmem7_eth.c
+ cmem7_tim.c
1
- StdPeriph_Driver\src\cmem7_eth.c
+ StdPeriph_Driver\src\cmem7_tim.c
- cmem7_flash.c
+ cmem7_wdg.c
1
- StdPeriph_Driver\src\cmem7_flash.c
+ StdPeriph_Driver\src\cmem7_wdg.c
- cmem7_adc.c
+ cmem7_aes.c
1
- StdPeriph_Driver\src\cmem7_adc.c
+ StdPeriph_Driver\src\cmem7_aes.c
- cmem7_i2c.c
+ cmem7_eth.c
1
- StdPeriph_Driver\src\cmem7_i2c.c
+ StdPeriph_Driver\src\cmem7_eth.c
- cmem7_dma.c
+ cmem7_gpio.c
1
- StdPeriph_Driver\src\cmem7_dma.c
+ StdPeriph_Driver\src\cmem7_gpio.c
- cmem7_gpio.c
+ cmem7_spi.c
1
- StdPeriph_Driver\src\cmem7_gpio.c
+ StdPeriph_Driver\src\cmem7_spi.c
- cmem7_misc.c
+ cmem7_dma.c
1
- StdPeriph_Driver\src\cmem7_misc.c
+ StdPeriph_Driver\src\cmem7_dma.c
- cmem7_wdg.c
+ cmem7_rtc.c
1
- StdPeriph_Driver\src\cmem7_wdg.c
+ StdPeriph_Driver\src\cmem7_rtc.c
- cmem7_rtc.c
+ cmem7_uart.c
1
- StdPeriph_Driver\src\cmem7_rtc.c
+ StdPeriph_Driver\src\cmem7_uart.c
- cmem7_can.c
+ cmem7_flash.c
1
- StdPeriph_Driver\src\cmem7_can.c
+ StdPeriph_Driver\src\cmem7_flash.c
- cmem7_tim.c
+ cmem7_can.c
1
- StdPeriph_Driver\src\cmem7_tim.c
+ StdPeriph_Driver\src\cmem7_can.c
- cmem7_spi.c
+ cmem7_usb.c
1
- StdPeriph_Driver\src\cmem7_spi.c
+ StdPeriph_Driver\src\cmem7_usb.c
@@ -1245,23 +1264,23 @@
- cmem7_aes.c
+ cmem7_adc.c
1
- StdPeriph_Driver\src\cmem7_aes.c
+ StdPeriph_Driver\src\cmem7_adc.c
- cmem7_usb.c
+ cmem7_efuse.c
1
- StdPeriph_Driver\src\cmem7_usb.c
+ StdPeriph_Driver\src\cmem7_efuse.c
- cmem7_uart.c
+ cmem7_misc.c
1
- StdPeriph_Driver\src\cmem7_uart.c
+ StdPeriph_Driver\src\cmem7_misc.c
diff --git a/bsp/ESP32_C3/drivers/drv_gpio.c b/bsp/ESP32_C3/drivers/drv_gpio.c
index f09f45dc930..4a4aa978ff6 100644
--- a/bsp/ESP32_C3/drivers/drv_gpio.c
+++ b/bsp/ESP32_C3/drivers/drv_gpio.c
@@ -21,9 +21,9 @@ static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
/*TODO:set gpio out put mode */
}
-static rt_int8_t mcu_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t mcu_pin_read(rt_device_t dev, rt_base_t pin)
{
- rt_int8_t value;
+ rt_ssize_t value;
value = gpio_get_level(pin);
return value;
}
diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c b/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c
index 1fd09c1cd43..e1a8f0ee81e 100644
--- a/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c
@@ -150,7 +150,7 @@ static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
cyhal_gpio_write(gpio_pin, value);
}
-static rt_int8_t ifx_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t ifx_pin_read(struct rt_device *device, rt_base_t pin)
{
rt_uint16_t gpio_pin;
@@ -160,7 +160,7 @@ static rt_int8_t ifx_pin_read(struct rt_device *device, rt_base_t pin)
}
else
{
- return -RT_ERROR;
+ return -RT_EINVAL;
}
return cyhal_gpio_read(gpio_pin);
diff --git a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj
index 51f96880420..177734ce465 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj
+++ b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1093,13 +1112,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cy_scb_uart.c
@@ -1149,6 +1161,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
cyhal_utils.c
@@ -1191,13 +1210,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c
-
-
- psoc6_01_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
-
-
cy_prot.c
@@ -1226,13 +1238,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
-
-
- psoc6_04_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
-
-
cyhal_triggers_psoc6_01.c
@@ -1242,16 +1247,16 @@
- cyhal_syspm.c
+ psoc6_01_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
- psoc6_02_cm0p_sleep.c
+ cyhal_syspm.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
@@ -1282,6 +1287,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cy_flash.c
@@ -1289,6 +1301,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
cy_ble_clk.c
@@ -1315,58 +1334,58 @@
libs
- cycfg_routing.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c
- cycfg_clocks.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c
- cycfg_qspi_memslot.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c
- cybsp.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062-BLE\cybsp.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c
- cycfg.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c
- cycfg_capsense.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c
- startup_psoc6_01_cm4.S
- 2
- libs\TARGET_CY8CKIT-062-BLE\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.S
+ cycfg_system.c
+ 1
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_system.c
- cycfg_system.c
- 1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_system.c
+ startup_psoc6_01_cm4.S
+ 2
+ libs\TARGET_CY8CKIT-062-BLE\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.S
@@ -1385,9 +1404,9 @@
- cycfg_peripherals.c
+ cybsp.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062-BLE\cybsp.c
diff --git a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx
index ab1c6366996..c1ec39d859f 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx
+++ b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx
@@ -487,6 +487,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1130,16 +1149,16 @@
- cy_ipc_drv.c
+ psoc6_02_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
- psoc6_01_cm0p_sleep.c
+ cy_ipc_drv.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c
@@ -1156,6 +1175,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cy_ipc_pipe.c
@@ -1193,9 +1219,9 @@
- psoc6_03_cm0p_sleep.c
+ psoc6_01_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
@@ -1219,13 +1245,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
-
-
- psoc6_02_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
-
-
cy_systick.c
@@ -1263,9 +1282,9 @@
- psoc6_04_cm0p_sleep.c
+ psoc6_03_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
@@ -1292,20 +1311,6 @@
libs
-
-
- cycfg_capsense.c
- 1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c
-
-
-
-
- cycfg_qspi_memslot.c
- 1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c
-
-
system_psoc6_cm4.c
@@ -1322,30 +1327,30 @@
- cycfg_peripherals.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c
- cycfg.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c
- cycfg_routing.c
+ cybsp.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062-BLE\cybsp.c
- cycfg_clocks.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c
@@ -1357,9 +1362,9 @@
- cybsp.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CKIT-062-BLE\cybsp.c
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c
@@ -1369,6 +1374,20 @@
libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_pins.c
+
+
+ cycfg_routing.c
+ 1
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c
+
+
+
+
+ cycfg_qspi_memslot.c
+ 1
+ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c
+
+
diff --git a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj
index db26d3f9d77..b66c62fe666 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj
+++ b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1086,6 +1105,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
cyhal_clock.c
@@ -1093,6 +1119,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c
+
+
+ psoc6_01_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
+
+
cy_scb_uart.c
@@ -1114,13 +1147,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_impl.c
-
-
- psoc6_02_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
-
-
cyhal_gpio.c
@@ -1142,6 +1168,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cyhal_utils.c
@@ -1184,13 +1217,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cy_prot.c
@@ -1247,13 +1273,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_01_124_bga.c
-
-
- psoc6_01_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
-
-
cyhal_interconnect.c
@@ -1284,16 +1303,16 @@
- cy_syspm.c
+ psoc6_03_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
- psoc6_04_cm0p_sleep.c
+ cy_syspm.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c
@@ -1308,86 +1327,86 @@
libs
- cycfg_routing.c
+ cycfg_system.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c
- cycfg_connectivity_bt.c
+ cybsp.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c
- cycfg_pins.c
+ system_psoc6_cm4.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_pins.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c
- cycfg_qspi_memslot.c
+ cycfg_pins.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_pins.c
- cycfg.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c
- startup_psoc6_01_cm4.s
- 2
- libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s
+ cycfg_qspi_memslot.c
+ 1
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_qspi_memslot.c
- system_psoc6_cm4.c
+ cycfg_connectivity_bt.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c
- cybsp.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c
- cycfg_system.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c
- cycfg_clocks.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c
- cycfg_capsense.c
- 1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c
+ startup_psoc6_01_cm4.s
+ 2
+ libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s
- cycfg_peripherals.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c
diff --git a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx
index 802886c109a..93441081eeb 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx
+++ b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1050,13 +1069,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_gpio.c
-
-
- psoc6_01_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
-
-
cyhal_irq_impl.c
@@ -1078,6 +1090,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
cy_scb_uart.c
@@ -1099,13 +1118,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_impl.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cyhal_gpio.c
@@ -1129,30 +1141,30 @@
- psoc6_04_cm0p_sleep.c
+ psoc6_03_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
- psoc6_02_cm0p_sleep.c
+ cyhal_utils.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c
- cyhal_utils.c
+ cy_ipc_drv.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c
- cy_ipc_drv.c
+ psoc6_04_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
@@ -1267,6 +1279,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c
+
+
+ psoc6_01_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
+
+
cy_syspm.c
@@ -1286,23 +1305,23 @@
libs
- cybsp.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c
- cycfg_peripherals.c
+ cycfg_system.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c
- cycfg_system.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c
@@ -1314,9 +1333,9 @@
- cycfg_routing.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c
@@ -1328,44 +1347,44 @@
- cycfg_connectivity_bt.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c
- cycfg.c
+ system_psoc6_cm4.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c
- cycfg_capsense.c
+ cybsp.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c
- startup_psoc6_01_cm4.s
- 2
- libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s
+ cycfg_clocks.c
+ 1
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c
- system_psoc6_cm4.c
- 1
- libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c
+ startup_psoc6_01_cm4.s
+ 2
+ libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s
- cycfg_clocks.c
+ cycfg_connectivity_bt.c
1
- libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c
diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj
index 2e8318d7fe7..b3024717b8a 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj
+++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1109,9 +1128,9 @@
- psoc6_02_cm0p_sleep.c
+ cy_scb_uart.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c
@@ -1123,9 +1142,9 @@
- cy_scb_uart.c
+ psoc6_03_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
@@ -1142,13 +1161,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_impl.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cyhal_gpio.c
@@ -1198,13 +1210,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c
-
-
- psoc6_04_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
-
-
cy_ipc_pipe.c
@@ -1261,6 +1266,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cyhal_interconnect.c
@@ -1282,6 +1294,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
psoc6_01_cm0p_sleep.c
@@ -1308,16 +1327,16 @@
libs
- cycfg_pins.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_pins.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c
- cycfg_system.c
- 1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c
+ startup_psoc6_02_cm4.S
+ 2
+ libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S
@@ -1329,65 +1348,65 @@
- startup_psoc6_02_cm4.S
- 2
- libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S
+ cycfg_connectivity_bt.c
+ 1
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c
- system_psoc6_cm4.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c
- cycfg_capsense.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c
- cycfg_routing.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c
- cycfg_clocks.c
+ cycfg_pins.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_pins.c
- cycfg.c
+ cycfg_system.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c
- cycfg_connectivity_bt.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c
- cycfg_qspi_memslot.c
+ system_psoc6_cm4.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c
- cycfg_peripherals.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c
diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx
index a2bdc271d7f..f6c8fe33b9d 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx
+++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1078,6 +1097,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
cyhal_clock.c
@@ -1169,6 +1195,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
cy_ipc_pipe.c
@@ -1213,23 +1246,23 @@
- cyhal_syspm.c
+ psoc6_04_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
- cy_systick.c
+ cyhal_syspm.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
- psoc6_04_cm0p_sleep.c
+ cy_systick.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c
@@ -1253,20 +1286,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
-
-
- psoc6_02_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
-
-
cy_syspm.c
@@ -1286,23 +1305,23 @@
libs
- cycfg_connectivity_bt.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c
- cycfg_routing.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c
- cycfg_qspi_memslot.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c
@@ -1314,23 +1333,23 @@
- cycfg_peripherals.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c
- cycfg_system.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c
- cybsp.c
+ cycfg_system.c
1
- libs\TARGET_CY8CKIT-062S2-43012\cybsp.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c
@@ -1342,9 +1361,9 @@
- cycfg.c
+ cycfg_connectivity_bt.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c
@@ -1356,16 +1375,16 @@
- cycfg_clocks.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c
- cycfg_capsense.c
+ cybsp.c
1
- libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CKIT-062S2-43012\cybsp.c
diff --git a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj
index d83ee73212c..6f0062e7643 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj
+++ b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1058,6 +1077,20 @@
Libraries
+
+
+ psoc6_01_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
+
+
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
cy_retarget_io.c
@@ -1163,13 +1196,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c
-
-
- psoc6_04_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
-
-
cy_ipc_drv.c
@@ -1191,6 +1217,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
cy_ipc_pipe.c
@@ -1233,13 +1266,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
-
-
- psoc6_01_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
-
-
cyhal_syspm.c
@@ -1254,13 +1280,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cyhal_interconnect.c
@@ -1284,16 +1303,16 @@
- cy_flash.c
+ psoc6_04_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
- psoc6_02_cm0p_sleep.c
+ cy_flash.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c
@@ -1322,23 +1341,16 @@
libs
- cycfg_pins.c
- 1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c
-
-
-
-
- cycfg_qspi_memslot.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c
- cycfg_system.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_routing.c
@@ -1350,16 +1362,16 @@
- system_psoc6_cm4.c
+ cycfg_pins.c
1
- libs\TARGET_CY8CKIT-062S4\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c
- cycfg_peripherals.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c
@@ -1371,16 +1383,23 @@
- cycfg_capsense.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_qspi_memslot.c
- cycfg_routing.c
+ system_psoc6_cm4.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CKIT-062S4\COMPONENT_CM4\system_psoc6_cm4.c
+
+
+
+
+ cycfg_peripherals.c
+ 1
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_peripherals.c
@@ -1392,9 +1411,9 @@
- cycfg.c
+ cycfg_system.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c
diff --git a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx
index 51e6d217c7b..204ec0a4307 100644
--- a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx
+++ b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1043,6 +1062,13 @@
..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cy_scb_i2c.c
@@ -1087,23 +1113,16 @@
- psoc6_01_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
-
-
-
-
- psoc6_03_cm0p_sleep.c
+ cy_scb_uart.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c
- cy_scb_uart.c
+ psoc6_01_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
@@ -1127,6 +1146,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
cyhal_system.c
@@ -1162,13 +1188,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c
-
-
- psoc6_04_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
-
-
cyhal_hwmgr.c
@@ -1262,23 +1281,23 @@
- cy_flash.c
+ psoc6_02_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
- cy_ble_clk.c
+ cy_flash.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ble_clk.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c
- psoc6_02_cm0p_sleep.c
+ cy_ble_clk.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ble_clk.c
@@ -1298,13 +1317,6 @@
libs
-
-
- cycfg_clocks.c
- 1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_clocks.c
-
-
cycfg_routing.c
@@ -1314,23 +1326,23 @@
- cycfg_system.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c
- cybsp.c
+ cycfg.c
1
- libs\TARGET_CY8CKIT-062S4\cybsp.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c
- cycfg_capsense.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_clocks.c
@@ -1340,6 +1352,20 @@
libs\TARGET_CY8CKIT-062S4\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_04_cm4.S
+
+
+ cybsp.c
+ 1
+ libs\TARGET_CY8CKIT-062S4\cybsp.c
+
+
+
+
+ cycfg_pins.c
+ 1
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c
+
+
cycfg_peripherals.c
@@ -1363,16 +1389,9 @@
- cycfg_pins.c
- 1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c
-
-
-
-
- cycfg.c
+ cycfg_system.c
1
- libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c
diff --git a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj
index 1745503c534..8e98bdeb5c9 100644
--- a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj
+++ b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1100,6 +1119,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
cyhal_clock.c
@@ -1151,23 +1177,16 @@
- psoc6_04_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
-
-
-
-
- psoc6_01_cm0p_sleep.c
+ cyhal_utils.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c
- cyhal_utils.c
+ psoc6_03_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
@@ -1191,6 +1210,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cy_ipc_pipe.c
@@ -1240,13 +1266,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cy_systick.c
@@ -1284,9 +1303,9 @@
- psoc6_02_cm0p_sleep.c
+ psoc6_01_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
@@ -1308,16 +1327,23 @@
libs
- cycfg_qspi_memslot.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c
- cycfg_clocks.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c
+
+
+
+
+ cycfg_qspi_memslot.c
+ 1
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c
@@ -1341,13 +1367,6 @@
libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_system.c
-
-
- cycfg_connectivity_bt.c
- 1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_connectivity_bt.c
-
-
cycfg_peripherals.c
@@ -1357,37 +1376,37 @@
- cycfg_routing.c
+ cybsp.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c
- system_psoc6_cm4.c
+ cycfg_connectivity_bt.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_connectivity_bt.c
- cybsp.c
+ cycfg_capsense.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_capsense.c
- cycfg_pins.c
+ system_psoc6_cm4.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c
- cycfg_capsense.c
+ cycfg_pins.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c
diff --git a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx
index 61f319b3ba8..acdff3e7e51 100644
--- a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx
+++ b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1036,6 +1055,13 @@
Libraries
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
cyhal_triggers_psoc6_03.c
@@ -1045,9 +1071,16 @@
- psoc6_04_cm0p_sleep.c
+ psoc6_02_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
+
+
+ cy_retarget_io.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c
@@ -1092,13 +1125,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c
-
-
- psoc6_02_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
-
-
cy_scb_common.c
@@ -1134,13 +1160,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c
-
-
- cy_retarget_io.c
- 1
- ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c
-
-
cyhal_utils.c
@@ -1183,6 +1202,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cy_prot.c
@@ -1206,16 +1232,16 @@
- psoc6_03_cm0p_sleep.c
+ cy_sysint.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
- cy_sysint.c
+ psoc6_01_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
@@ -1260,13 +1286,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c
-
-
- psoc6_01_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
-
-
cy_syspm.c
@@ -1286,44 +1305,44 @@
libs
- cybsp.c
+ cycfg_pins.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c
- cycfg_system.c
- 1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_system.c
+ startup_psoc6_03_cm4.S
+ 2
+ libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_03_cm4.S
- cycfg.c
+ cybsp.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c
- cycfg_clocks.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c
- cycfg_qspi_memslot.c
+ system_psoc6_cm4.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c
- cycfg_peripherals.c
+ cycfg_routing.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c
@@ -1335,16 +1354,16 @@
- startup_psoc6_03_cm4.S
- 2
- libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_03_cm4.S
+ cycfg_system.c
+ 1
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_system.c
- cycfg_pins.c
+ cycfg_clocks.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c
@@ -1356,16 +1375,16 @@
- cycfg_routing.c
+ cycfg.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg.c
- system_psoc6_cm4.c
+ cycfg_peripherals.c
1
- libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_peripherals.c
diff --git a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj
index 1ef03d4cb05..306b0209373 100644
--- a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj
+++ b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1086,13 +1105,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_gpio.c
-
-
- psoc6_03_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
-
-
cyhal_irq_impl.c
@@ -1156,6 +1168,20 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
+
+
+ psoc6_02_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+
+
psoc6_01_cm0p_sleep.c
@@ -1205,6 +1231,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c
+
+
+ psoc6_04_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+
+
cy_prot.c
@@ -1233,13 +1266,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
-
-
- psoc6_04_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
-
-
cyhal_syspm.c
@@ -1282,13 +1308,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c
-
-
- psoc6_02_cm0p_sleep.c
- 1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
-
-
cy_syspm.c
@@ -1306,13 +1325,6 @@
libs
-
-
- cycfg_connectivity_bt.c
- 1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c
-
-
cybsp.c
@@ -1322,44 +1334,44 @@
- cycfg_qspi_memslot.c
+ cycfg_capsense.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c
- cycfg_system.c
+ system_psoc6_cm4.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c
- cycfg_peripherals.c
- 1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c
+ startup_psoc6_02_cm4.S
+ 2
+ libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S
- system_psoc6_cm4.c
+ cycfg_connectivity_bt.c
1
- libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c
- startup_psoc6_02_cm4.S
- 2
- libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S
+ cycfg_pins.c
+ 1
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c
- cycfg_capsense.c
+ cycfg_peripherals.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c
@@ -1371,16 +1383,16 @@
- cycfg_pins.c
+ cycfg_routing.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c
- cycfg_routing.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c
@@ -1390,6 +1402,13 @@
libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg.c
+
+
+ cycfg_system.c
+ 1
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c
+
+
diff --git a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx
index 7678f8d16b1..a3778c2b8bc 100644
--- a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx
+++ b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1045,9 +1064,9 @@
- psoc6_03_cm0p_sleep.c
+ cy_retarget_io.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c
@@ -1108,16 +1127,16 @@
- psoc6_04_cm0p_sleep.c
+ cyhal_gpio.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c
- cyhal_gpio.c
+ psoc6_02_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
@@ -1134,13 +1153,6 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c
-
-
- cy_retarget_io.c
- 1
- ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c
-
-
cyhal_utils.c
@@ -1206,44 +1218,44 @@
- cy_sysint.c
+ psoc6_04_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c
- cyhal_syspm.c
+ cy_sysint.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c
- cyhal_psoc6_02_68_qfn.c
+ psoc6_01_cm0p_sleep.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_02_68_qfn.c
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
- psoc6_01_cm0p_sleep.c
+ cyhal_syspm.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c
- cy_systick.c
+ cyhal_psoc6_02_68_qfn.c
1
- ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_02_68_qfn.c
- psoc6_02_cm0p_sleep.c
+ cy_systick.c
1
- ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c
+ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c
@@ -1267,6 +1279,13 @@
..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c
+
+
+ psoc6_03_cm0p_sleep.c
+ 1
+ ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c
+
+
cy_syspm.c
@@ -1293,37 +1312,37 @@
- cycfg_clocks.c
+ cycfg_routing.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_clocks.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c
- cycfg_capsense.c
+ system_psoc6_cm4.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c
+ libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c
- system_psoc6_cm4.c
+ cycfg_capsense.c
1
- libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c
- cycfg_system.c
+ cycfg_pins.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c
- cycfg_qspi_memslot.c
+ cycfg_system.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c
@@ -1335,37 +1354,37 @@
- cycfg_peripherals.c
+ cycfg_qspi_memslot.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c
- cycfg_routing.c
+ cycfg_peripherals.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c
- cycfg_pins.c
+ cycfg.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg.c
- cycfg_connectivity_bt.c
+ cycfg_clocks.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_clocks.c
- cycfg.c
+ cycfg_connectivity_bt.c
1
- libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg.c
+ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c
diff --git a/bsp/Vango/v85xx/drivers/drv_gpio.c b/bsp/Vango/v85xx/drivers/drv_gpio.c
index 4caf5b9bccc..11d7454841a 100644
--- a/bsp/Vango/v85xx/drivers/drv_gpio.c
+++ b/bsp/Vango/v85xx/drivers/drv_gpio.c
@@ -140,11 +140,11 @@ static void v85xx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t v85xx_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t v85xx_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
- int value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
if (PIN_PORT(pin) == PIN_V85XXPORT_A)
{
@@ -157,6 +157,10 @@ static rt_int8_t v85xx_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_V85XXPIN(pin);
value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin);
}
+ else
+ {
+ return -RT_EINVAL;
+ }
return value;
}
diff --git a/bsp/Vango/v85xx/project.uvprojx b/bsp/Vango/v85xx/project.uvprojx
index 871cd8c3546..5044c86edbe 100644
--- a/bsp/Vango/v85xx/project.uvprojx
+++ b/bsp/Vango/v85xx/project.uvprojx
@@ -483,6 +483,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1059,9 +1078,16 @@
Vango_Lib
- lib_wdt.c
+ lib_misc.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_wdt.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_misc.c
+
+
+
+
+ lib_tmr.c
+ 1
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c
@@ -1073,79 +1099,79 @@
- lib_i2c.c
+ lib_LoadNVR.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_i2c.c
+ Libraries\CMSIS\Vango\V85xx\Source\lib_LoadNVR.c
- lib_cortex.c
+ lib_flash.c
1
- Libraries\CMSIS\Vango\V85xx\Source\lib_cortex.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_flash.c
- lib_ana.c
+ lib_rtc.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_ana.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_rtc.c
- lib_LoadNVR.c
+ lib_u32k.c
1
- Libraries\CMSIS\Vango\V85xx\Source\lib_LoadNVR.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_u32k.c
- lib_comp.c
+ lib_dma.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_comp.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c
- lib_misc.c
+ lib_clk.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_misc.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_clk.c
- lib_tmr.c
+ lib_gpio.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_gpio.c
- lib_iso7816.c
+ lib_CodeRAM.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_iso7816.c
+ Libraries\CMSIS\Vango\V85xx\Source\lib_CodeRAM.c
- lib_adc_tiny.c
+ lib_crypt.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_crypt.c
- lib_CodeRAM.c
+ lib_lcd.c
1
- Libraries\CMSIS\Vango\V85xx\Source\lib_CodeRAM.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_lcd.c
- lib_u32k.c
+ lib_uart.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_u32k.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c
@@ -1157,37 +1183,30 @@
- lib_rtc.c
- 1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_rtc.c
-
-
-
-
- lib_flash.c
+ lib_adc_tiny.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_flash.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c
- lib_lcd.c
+ lib_version.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_lcd.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_version.c
- lib_uart.c
+ lib_iso7816.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_iso7816.c
- lib_crypt.c
+ lib_cortex.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_crypt.c
+ Libraries\CMSIS\Vango\V85xx\Source\lib_cortex.c
@@ -1199,51 +1218,51 @@
- lib_spi.c
+ lib_adc.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_spi.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_adc.c
- lib_pmu.c
+ lib_comp.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_pmu.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_comp.c
- lib_clk.c
+ lib_spi.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_clk.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_spi.c
- lib_dma.c
+ lib_wdt.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_wdt.c
- lib_version.c
+ lib_pmu.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_version.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_pmu.c
- lib_adc.c
+ lib_i2c.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_adc.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_i2c.c
- lib_gpio.c
+ lib_ana.c
1
- Libraries\VangoV85xx_standard_peripheral\Source\lib_gpio.c
+ Libraries\VangoV85xx_standard_peripheral\Source\lib_ana.c
diff --git a/bsp/Vango/v85xxp/drivers/drv_gpio.c b/bsp/Vango/v85xxp/drivers/drv_gpio.c
index dcb57e0dd5b..4b7f2fdfcf4 100644
--- a/bsp/Vango/v85xxp/drivers/drv_gpio.c
+++ b/bsp/Vango/v85xxp/drivers/drv_gpio.c
@@ -141,11 +141,11 @@ static void V85XXP_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t V85XXP_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t V85XXP_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_Type *gpio_port;
uint16_t gpio_pin;
- int value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
if (PIN_PORT(pin) == PIN_V85XXPPORT_A)
{
diff --git a/bsp/Vango/v85xxp/project.uvprojx b/bsp/Vango/v85xxp/project.uvprojx
index 1af4617310e..bd682a6c7e6 100644
--- a/bsp/Vango/v85xxp/project.uvprojx
+++ b/bsp/Vango/v85xxp/project.uvprojx
@@ -483,6 +483,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1052,142 +1071,142 @@
Vango_Lib
- lib_adc_tiny.c
+ lib_version.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc_tiny.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_version.c
- lib_uart.c
+ lib_cmp.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_uart.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_cmp.c
- lib_wdt.c
+ lib_iso7816.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_wdt.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_iso7816.c
- lib_lcd.c
+ lib_misc.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_lcd.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_misc.c
- lib_adc.c
+ lib_uart.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_uart.c
- lib_flash.c
+ lib_tmr.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_flash.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_tmr.c
- lib_misc.c
+ lib_adc.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_misc.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc.c
- lib_spi.c
+ lib_flash.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_spi.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_flash.c
- lib_ana.c
+ lib_gpio.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_ana.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_gpio.c
- lib_tmr.c
+ lib_cortex.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_tmr.c
+ Libraries\CMSIS\Vango\V85xxP\Source\lib_cortex.c
- lib_cortex.c
+ lib_crypt.c
1
- Libraries\CMSIS\Vango\V85xxP\Source\lib_cortex.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_crypt.c
- lib_cmp.c
+ lib_clk.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_cmp.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_clk.c
- lib_crypt.c
+ lib_pwm.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_crypt.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_pwm.c
- lib_dma.c
+ lib_adc_tiny.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_dma.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc_tiny.c
- lib_pwm.c
+ lib_pmu.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_pwm.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_pmu.c
- lib_clk.c
+ lib_lcd.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_clk.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_lcd.c
- lib_gpio.c
+ lib_wdt.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_gpio.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_wdt.c
- lib_pmu.c
+ system_target.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_pmu.c
+ Libraries\CMSIS\Vango\V85xxP\Source\system_target.c
- lib_u32k.c
+ lib_i2c.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_u32k.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_i2c.c
- lib_i2c.c
+ lib_rtc.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_i2c.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_rtc.c
@@ -1199,16 +1218,23 @@
- lib_rtc.c
+ lib_spi.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_rtc.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_spi.c
- lib_iso7816.c
+ lib_dma.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_iso7816.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_dma.c
+
+
+
+
+ lib_u32k.c
+ 1
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_u32k.c
@@ -1227,16 +1253,9 @@
- system_target.c
- 1
- Libraries\CMSIS\Vango\V85xxP\Source\system_target.c
-
-
-
-
- lib_version.c
+ lib_ana.c
1
- Libraries\VangoV85xxP_standard_peripheral\Source\lib_version.c
+ Libraries\VangoV85xxP_standard_peripheral\Source\lib_ana.c
diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c
index 000f60397a4..8bddf41ed02 100644
--- a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c
+++ b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c
@@ -188,7 +188,7 @@ static void acm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
}
-static rt_int8_t acm32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t acm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
@@ -198,7 +198,7 @@ static rt_int8_t acm32_pin_read(rt_device_t dev, rt_base_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c
index 63150e4063f..e431e467e1e 100644
--- a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c
+++ b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c
@@ -135,7 +135,7 @@ static rt_tick_t _pm_timer_get_tick(struct rt_pm *pm)
{
rt_tick_t tick;
RT_ASSERT(pm != RT_NULL);
-
+
tick = 1;
return get_os_tick_from_pm_tick(tick);
diff --git a/bsp/acm32/acm32f0x0-nucleo/project.ewp b/bsp/acm32/acm32f0x0-nucleo/project.ewp
index b14d36e28a8..92bb6c55af5 100644
--- a/bsp/acm32/acm32f0x0-nucleo/project.ewp
+++ b/bsp/acm32/acm32f0x0-nucleo/project.ewp
@@ -2230,6 +2230,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
@@ -2267,34 +2270,34 @@
$PROJ_DIR$\drivers\drv_i2c.c
- $PROJ_DIR$\drivers\drv_wdt.c
+ $PROJ_DIR$\drivers\drv_uart.c
- $PROJ_DIR$\drivers\drv_rtc.c
+ $PROJ_DIR$\drivers\drv_wdt.c
- $PROJ_DIR$\drivers\drv_spi.c
+ $PROJ_DIR$\drivers\drv_adc.c
- $PROJ_DIR$\drivers\drv_adc.c
+ $PROJ_DIR$\drivers\drv_spi.c
$PROJ_DIR$\drivers\drv_gpio.c
- $PROJ_DIR$\drivers\drv_hwtimer.c
+ $PROJ_DIR$\drivers\drv_pm.c
- $PROJ_DIR$\drivers\drv_pm.c
+ $PROJ_DIR$\drivers\drv_hwtimer.c
$PROJ_DIR$\drivers\drv_soft_i2c.c
- $PROJ_DIR$\drivers\board.c
+ $PROJ_DIR$\drivers\drv_rtc.c
- $PROJ_DIR$\drivers\drv_uart.c
+ $PROJ_DIR$\drivers\board.c
diff --git a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx
index e0f6df6bd25..da7df308e26 100644
--- a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx
+++ b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx
@@ -606,6 +606,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -801,9 +820,9 @@
Drivers
- drv_soft_i2c.c
+ drv_pm.c
1
- drivers\drv_soft_i2c.c
+ drivers\drv_pm.c
@@ -813,6 +832,13 @@
drivers\drv_rtc.c
+
+
+ drv_adc.c
+ 1
+ drivers\drv_adc.c
+
+
drv_uart.c
@@ -829,16 +855,16 @@
- drv_wdt.c
+ drv_soft_i2c.c
1
- drivers\drv_wdt.c
+ drivers\drv_soft_i2c.c
- drv_pm.c
+ drv_gpio.c
1
- drivers\drv_pm.c
+ drivers\drv_gpio.c
@@ -850,9 +876,9 @@
- board.c
+ drv_wdt.c
1
- drivers\board.c
+ drivers\drv_wdt.c
@@ -864,16 +890,9 @@
- drv_adc.c
- 1
- drivers\drv_adc.c
-
-
-
-
- drv_gpio.c
+ board.c
1
- drivers\drv_gpio.c
+ drivers\board.c
diff --git a/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c b/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c
index 3b5d7a32258..bb653fca6e9 100644
--- a/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c
+++ b/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c
@@ -206,7 +206,7 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
}
-static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
@@ -216,7 +216,7 @@ static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
diff --git a/bsp/acm32/acm32f4xx-nucleo/project.ewp b/bsp/acm32/acm32f4xx-nucleo/project.ewp
index 3fb0b2981e5..48c5da0cf5f 100644
--- a/bsp/acm32/acm32f4xx-nucleo/project.ewp
+++ b/bsp/acm32/acm32f4xx-nucleo/project.ewp
@@ -2210,6 +2210,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
@@ -2238,10 +2241,10 @@
Drivers
- $PROJ_DIR$\drivers\drv_gpio.c
+ $PROJ_DIR$\drivers\drv_uart.c
- $PROJ_DIR$\drivers\drv_uart.c
+ $PROJ_DIR$\drivers\drv_gpio.c
$PROJ_DIR$\drivers\board.c
diff --git a/bsp/acm32/acm32f4xx-nucleo/project.uvprojx b/bsp/acm32/acm32f4xx-nucleo/project.uvprojx
index f3290dcac06..02b15ed3720 100644
--- a/bsp/acm32/acm32f4xx-nucleo/project.uvprojx
+++ b/bsp/acm32/acm32f4xx-nucleo/project.uvprojx
@@ -538,6 +538,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -702,16 +721,16 @@
- board.c
+ drv_uart.c
1
- drivers\board.c
+ drivers\drv_uart.c
- drv_uart.c
+ board.c
1
- drivers\drv_uart.c
+ drivers\board.c
diff --git a/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c b/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c
index 6c17599e89f..b726ec4e6bf 100644
--- a/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c
+++ b/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c
@@ -60,7 +60,7 @@ static void air105_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t air105_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t air105_pin_read(rt_device_t dev, rt_base_t pin)
{
if (pin < GPIO_MAX)
{
@@ -68,7 +68,7 @@ static rt_int8_t air105_pin_read(rt_device_t dev, rt_base_t pin)
}
else
{
- return -1;
+ return -RT_EINVAL;
}
}
diff --git a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c
index a81c1790bb4..53dac60dfbd 100644
--- a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c
+++ b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c
@@ -157,7 +157,7 @@ static void air32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t air32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t air32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
@@ -169,6 +169,10 @@ static rt_int8_t air32_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_AIRPIN(pin);
value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
}
+ else
+ {
+ return -RT_EINVAL;
+ }
return value;
}
diff --git a/bsp/airm2m/air32f103/project.ewp b/bsp/airm2m/air32f103/project.ewp
index 7bcc40bef25..8d9fbcdfc82 100644
--- a/bsp/airm2m/air32f103/project.ewp
+++ b/bsp/airm2m/air32f103/project.ewp
@@ -2218,6 +2218,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/airm2m/air32f103/project.uvprojx b/bsp/airm2m/air32f103/project.uvprojx
index e1a8bd60158..e4656d9989a 100644
--- a/bsp/airm2m/air32f103/project.uvprojx
+++ b/bsp/airm2m/air32f103/project.uvprojx
@@ -487,6 +487,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/allwinner/d1/.config b/bsp/allwinner/d1/.config
index 8e0b8ccb122..f38cb96783f 100644
--- a/bsp/allwinner/d1/.config
+++ b/bsp/allwinner/d1/.config
@@ -72,7 +72,7 @@ CONFIG_RT_USING_MEMTRACE=y
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
+CONFIG_RT_USING_DEVICE_OPS=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
@@ -153,6 +153,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set
+CONFIG_RT_USING_DFS_PTYFS=y
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
@@ -187,8 +188,6 @@ CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
-CONFIG_RT_USING_TTY=y
-# CONFIG_RT_TTY_DEBUG is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
@@ -397,10 +396,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024
CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
CONFIG_LWP_TID_MAX_NR=64
CONFIG_RT_LWP_SHM_MAX_NR=64
-# CONFIG_LWP_UNIX98_PTY is not set
CONFIG_RT_USING_LDSO=y
# CONFIG_ELF_DEBUG_ENABLE is not set
# CONFIG_ELF_LOAD_RANDOMIZE is not set
+CONFIG_LWP_USING_TERMINAL=y
+CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
#
# Memory management
diff --git a/bsp/allwinner/d1/rtconfig.h b/bsp/allwinner/d1/rtconfig.h
index 8aca7375f97..fa1d2d602a9 100644
--- a/bsp/allwinner/d1/rtconfig.h
+++ b/bsp/allwinner/d1/rtconfig.h
@@ -47,6 +47,7 @@
#define RT_USING_MEMTRACE
#define RT_USING_HEAP
#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart"
@@ -105,6 +106,7 @@
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_ROMFS
+#define RT_USING_DFS_PTYFS
#define RT_USING_PAGECACHE
/* page cache config */
@@ -131,7 +133,6 @@
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_TTY
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
@@ -256,6 +257,8 @@
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
+#define LWP_USING_TERMINAL
+#define LWP_PTY_MAX_PARIS_LIMIT 64
/* Memory management */
diff --git a/bsp/allwinner/d1s/.config b/bsp/allwinner/d1s/.config
index 8beb51059e8..38a1e7d9006 100644
--- a/bsp/allwinner/d1s/.config
+++ b/bsp/allwinner/d1s/.config
@@ -72,7 +72,7 @@ CONFIG_RT_USING_MEMTRACE=y
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
+CONFIG_RT_USING_DEVICE_OPS=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
@@ -152,6 +152,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
# CONFIG_RT_DFS_ELM_USE_EXFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_PTYFS=y
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
@@ -185,8 +186,6 @@ CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_SERIAL_V1 is not set
CONFIG_RT_USING_SERIAL_V2=y
# CONFIG_RT_SERIAL_USING_DMA is not set
-CONFIG_RT_USING_TTY=y
-# CONFIG_RT_TTY_DEBUG is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
@@ -316,10 +315,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024
CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
CONFIG_LWP_TID_MAX_NR=64
CONFIG_RT_LWP_SHM_MAX_NR=64
-# CONFIG_LWP_UNIX98_PTY is not set
CONFIG_RT_USING_LDSO=y
# CONFIG_ELF_DEBUG_ENABLE is not set
# CONFIG_ELF_LOAD_RANDOMIZE is not set
+CONFIG_LWP_USING_TERMINAL=y
+CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
#
# Memory management
diff --git a/bsp/allwinner/d1s/rtconfig.h b/bsp/allwinner/d1s/rtconfig.h
index 032644d48f6..b52049619c4 100644
--- a/bsp/allwinner/d1s/rtconfig.h
+++ b/bsp/allwinner/d1s/rtconfig.h
@@ -47,6 +47,7 @@
#define RT_USING_MEMTRACE
#define RT_USING_HEAP
#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart0"
@@ -104,6 +105,7 @@
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_PTYFS
#define RT_USING_PAGECACHE
/* page cache config */
@@ -128,7 +130,6 @@
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V2
-#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
@@ -194,6 +195,8 @@
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
+#define LWP_USING_TERMINAL
+#define LWP_PTY_MAX_PARIS_LIMIT 64
/* Memory management */
diff --git a/bsp/allwinner/libraries/drivers/drv_pin.c b/bsp/allwinner/libraries/drivers/drv_pin.c
index ce0a5359a9e..5d0d4e94391 100644
--- a/bsp/allwinner/libraries/drivers/drv_pin.c
+++ b/bsp/allwinner/libraries/drivers/drv_pin.c
@@ -32,11 +32,11 @@ static void hal_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va
hal_gpio_set_data(pin,value);
}
-static rt_int8_t hal_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t hal_pin_read(struct rt_device *device, rt_base_t pin)
{
gpio_data_t value;
hal_gpio_get_data(pin,&value);
- return (rt_int8_t)value;
+ return (rt_ssize_t)value;
}
static rt_err_t hal_pin_attach_irq(struct rt_device *device, rt_base_t pin,
diff --git a/bsp/allwinner/libraries/drivers/touch/drv_touch.c b/bsp/allwinner/libraries/drivers/touch/drv_touch.c
index 8361fb17428..d21013551cc 100644
--- a/bsp/allwinner/libraries/drivers/touch/drv_touch.c
+++ b/bsp/allwinner/libraries/drivers/touch/drv_touch.c
@@ -1,5 +1,5 @@
/*
- * COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
+ * COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd
* All rights reserved.
* Change Logs:
* Date Author Notes
diff --git a/bsp/allwinner/libraries/drivers/touch/drv_touch.h b/bsp/allwinner/libraries/drivers/touch/drv_touch.h
index e7c6e7e0fbd..ad96e7c2458 100644
--- a/bsp/allwinner/libraries/drivers/touch/drv_touch.h
+++ b/bsp/allwinner/libraries/drivers/touch/drv_touch.h
@@ -1,5 +1,5 @@
/*
- * COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
+ * COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd
* All rights reserved.
* Change Logs:
* Date Author Notes
diff --git a/bsp/allwinner_tina/drivers/drv_gpio.c b/bsp/allwinner_tina/drivers/drv_gpio.c
index d2457cd652c..25d956d35eb 100644
--- a/bsp/allwinner_tina/drivers/drv_gpio.c
+++ b/bsp/allwinner_tina/drivers/drv_gpio.c
@@ -453,12 +453,12 @@ static void pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
gpio_set_value(pin_index[pin].pin_port, pin_index[pin].pin, value);
}
-static rt_int8_t pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t pin_read(struct rt_device *device, rt_base_t pin)
{
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
{
LOG_E("pin:%d value wrongful", pin);
- return 0;
+ return -RT_EINVAL;
}
return gpio_get_value(pin_index[pin].pin_port, pin_index[pin].pin);
diff --git a/bsp/amebaz/.config b/bsp/amebaz/.config
index bed1c53c04e..f4b177dd90d 100644
--- a/bsp/amebaz/.config
+++ b/bsp/amebaz/.config
@@ -163,6 +163,7 @@ CONFIG_RT_WLAN_SCAN_WAIT_MS=10000
CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000
CONFIG_RT_WLAN_SCAN_SORT=y
CONFIG_RT_WLAN_MSH_CMD_ENABLE=y
+CONFIG_RT_WLAN_JOIN_SCAN_BY_MGNT=y
CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y
CONFIG_AUTO_CONNECTION_PERIOD_MS=2000
CONFIG_RT_WLAN_CFG_ENABLE=y
diff --git a/bsp/amebaz/project.ewp b/bsp/amebaz/project.ewp
index 28a4c609070..f4726be0fa5 100644
--- a/bsp/amebaz/project.ewp
+++ b/bsp/amebaz/project.ewp
@@ -2144,10 +2144,10 @@
Applications
- $PROJ_DIR$\applications\smartconfig_app.c
+ $PROJ_DIR$\applications\main.c
- $PROJ_DIR$\applications\main.c
+ $PROJ_DIR$\applications\smartconfig_app.c
@@ -2206,6 +2206,9 @@
$PROJ_DIR$\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/amebaz/rtconfig.h b/bsp/amebaz/rtconfig.h
index c52448d9c3c..387265ad719 100644
--- a/bsp/amebaz/rtconfig.h
+++ b/bsp/amebaz/rtconfig.h
@@ -92,6 +92,7 @@
#define RT_WLAN_CONNECT_WAIT_MS 10000
#define RT_WLAN_SCAN_SORT
#define RT_WLAN_MSH_CMD_ENABLE
+#define RT_WLAN_JOIN_SCAN_BY_MGNT
#define RT_WLAN_AUTO_CONNECT_ENABLE
#define AUTO_CONNECTION_PERIOD_MS 2000
#define RT_WLAN_CFG_ENABLE
diff --git a/bsp/apm32/apm32e103ze-evalboard/project.ewp b/bsp/apm32/apm32e103ze-evalboard/project.ewp
index a6157909c1b..f208d0a2b64 100644
--- a/bsp/apm32/apm32e103ze-evalboard/project.ewp
+++ b/bsp/apm32/apm32e103ze-evalboard/project.ewp
@@ -2262,6 +2262,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32e103ze-evalboard/project.uvprojx b/bsp/apm32/apm32e103ze-evalboard/project.uvprojx
index 7d7d60d64ff..2866f8214e2 100644
--- a/bsp/apm32/apm32e103ze-evalboard/project.uvprojx
+++ b/bsp/apm32/apm32e103ze-evalboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32e103ze-tinyboard/project.ewp b/bsp/apm32/apm32e103ze-tinyboard/project.ewp
index a6157909c1b..f208d0a2b64 100644
--- a/bsp/apm32/apm32e103ze-tinyboard/project.ewp
+++ b/bsp/apm32/apm32e103ze-tinyboard/project.ewp
@@ -2262,6 +2262,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx b/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx
index 9ede6405645..f42adf6f62c 100644
--- a/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx
+++ b/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f030r8-miniboard/project.ewp b/bsp/apm32/apm32f030r8-miniboard/project.ewp
index e0d213ce2ef..9a285d4d417 100644
--- a/bsp/apm32/apm32f030r8-miniboard/project.ewp
+++ b/bsp/apm32/apm32f030r8-miniboard/project.ewp
@@ -2260,6 +2260,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f030r8-miniboard/project.uvprojx b/bsp/apm32/apm32f030r8-miniboard/project.uvprojx
index c4dd4234e52..158420bae08 100644
--- a/bsp/apm32/apm32f030r8-miniboard/project.uvprojx
+++ b/bsp/apm32/apm32f030r8-miniboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f051r8-evalboard/project.ewp b/bsp/apm32/apm32f051r8-evalboard/project.ewp
index a84fcdf51e9..34e0559bdf0 100644
--- a/bsp/apm32/apm32f051r8-evalboard/project.ewp
+++ b/bsp/apm32/apm32f051r8-evalboard/project.ewp
@@ -2262,6 +2262,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f051r8-evalboard/project.uvprojx b/bsp/apm32/apm32f051r8-evalboard/project.uvprojx
index 122ed969181..f910946d8ce 100644
--- a/bsp/apm32/apm32f051r8-evalboard/project.uvprojx
+++ b/bsp/apm32/apm32f051r8-evalboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f072vb-miniboard/project.ewp b/bsp/apm32/apm32f072vb-miniboard/project.ewp
index d45cf9a48ec..4739701e977 100644
--- a/bsp/apm32/apm32f072vb-miniboard/project.ewp
+++ b/bsp/apm32/apm32f072vb-miniboard/project.ewp
@@ -2262,6 +2262,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f072vb-miniboard/project.uvprojx b/bsp/apm32/apm32f072vb-miniboard/project.uvprojx
index b244010ae1a..3a1b6f28e50 100644
--- a/bsp/apm32/apm32f072vb-miniboard/project.uvprojx
+++ b/bsp/apm32/apm32f072vb-miniboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f091vc-miniboard/project.ewp b/bsp/apm32/apm32f091vc-miniboard/project.ewp
index 8b0f72946e0..a13f8c829c5 100644
--- a/bsp/apm32/apm32f091vc-miniboard/project.ewp
+++ b/bsp/apm32/apm32f091vc-miniboard/project.ewp
@@ -2262,6 +2262,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f091vc-miniboard/project.uvprojx b/bsp/apm32/apm32f091vc-miniboard/project.uvprojx
index 8a995d61605..839ee78bb64 100644
--- a/bsp/apm32/apm32f091vc-miniboard/project.uvprojx
+++ b/bsp/apm32/apm32f091vc-miniboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f103vb-miniboard/project.ewp b/bsp/apm32/apm32f103vb-miniboard/project.ewp
index 5cec65a487c..4c067c58a63 100644
--- a/bsp/apm32/apm32f103vb-miniboard/project.ewp
+++ b/bsp/apm32/apm32f103vb-miniboard/project.ewp
@@ -2264,6 +2264,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f103vb-miniboard/project.uvprojx b/bsp/apm32/apm32f103vb-miniboard/project.uvprojx
index d8a76eaa29a..a82c61ae79b 100644
--- a/bsp/apm32/apm32f103vb-miniboard/project.uvprojx
+++ b/bsp/apm32/apm32f103vb-miniboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f103xe-minibroard/project.ewp b/bsp/apm32/apm32f103xe-minibroard/project.ewp
index 80f623ea5ef..a7f72c5b6b3 100644
--- a/bsp/apm32/apm32f103xe-minibroard/project.ewp
+++ b/bsp/apm32/apm32f103xe-minibroard/project.ewp
@@ -2234,6 +2234,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx
index 2c27db85799..9091c43e62b 100644
--- a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx
+++ b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f107vc-evalboard/project.ewp b/bsp/apm32/apm32f107vc-evalboard/project.ewp
index b6df615df8d..61791b7dafb 100644
--- a/bsp/apm32/apm32f107vc-evalboard/project.ewp
+++ b/bsp/apm32/apm32f107vc-evalboard/project.ewp
@@ -2264,6 +2264,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f107vc-evalboard/project.uvprojx b/bsp/apm32/apm32f107vc-evalboard/project.uvprojx
index a523336e8da..b17679dc89b 100644
--- a/bsp/apm32/apm32f107vc-evalboard/project.uvprojx
+++ b/bsp/apm32/apm32f107vc-evalboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f407ig-minibroard/project.ewp b/bsp/apm32/apm32f407ig-minibroard/project.ewp
index b01f024fbbb..1452a27546c 100644
--- a/bsp/apm32/apm32f407ig-minibroard/project.ewp
+++ b/bsp/apm32/apm32f407ig-minibroard/project.ewp
@@ -2232,6 +2232,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f407ig-minibroard/project.uvprojx b/bsp/apm32/apm32f407ig-minibroard/project.uvprojx
index 5cee83c6ecf..2b0b55fc395 100644
--- a/bsp/apm32/apm32f407ig-minibroard/project.uvprojx
+++ b/bsp/apm32/apm32f407ig-minibroard/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32f407zg-evalboard/project.ewp b/bsp/apm32/apm32f407zg-evalboard/project.ewp
index 9aee2032cac..345bf7900ea 100644
--- a/bsp/apm32/apm32f407zg-evalboard/project.ewp
+++ b/bsp/apm32/apm32f407zg-evalboard/project.ewp
@@ -2264,6 +2264,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32f407zg-evalboard/project.uvprojx b/bsp/apm32/apm32f407zg-evalboard/project.uvprojx
index ed82a3ed309..4704a8ffc5f 100644
--- a/bsp/apm32/apm32f407zg-evalboard/project.uvprojx
+++ b/bsp/apm32/apm32f407zg-evalboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/apm32s103vb-miniboard/project.ewp b/bsp/apm32/apm32s103vb-miniboard/project.ewp
index 04d7a144cdf..9a089720d45 100644
--- a/bsp/apm32/apm32s103vb-miniboard/project.ewp
+++ b/bsp/apm32/apm32s103vb-miniboard/project.ewp
@@ -2262,6 +2262,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/apm32/apm32s103vb-miniboard/project.uvprojx b/bsp/apm32/apm32s103vb-miniboard/project.uvprojx
index b4cd951fe27..43f24881fe2 100644
--- a/bsp/apm32/apm32s103vb-miniboard/project.uvprojx
+++ b/bsp/apm32/apm32s103vb-miniboard/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.c b/bsp/apm32/libraries/Drivers/drv_gpio.c
index c00ac26c54e..9555dd08055 100644
--- a/bsp/apm32/libraries/Drivers/drv_gpio.c
+++ b/bsp/apm32/libraries/Drivers/drv_gpio.c
@@ -173,7 +173,7 @@ static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_T *gpio_port;
uint16_t gpio_pin;
@@ -185,6 +185,10 @@ static rt_int8_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_APMPIN(pin);
value = GPIO_ReadInputBit(gpio_port, gpio_pin);
}
+ else
+ {
+ return -RT_EINVAL;
+ }
return value;
}
diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c
index 08bcdfdbfcf..ad87b6310d7 100644
--- a/bsp/apollo2/board/gpio.c
+++ b/bsp/apollo2/board/gpio.c
@@ -59,9 +59,9 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-rt_int8_t am_pin_read(rt_device_t dev, rt_base_t pin)
+rt_ssize_t am_pin_read(rt_device_t dev, rt_base_t pin)
{
- rt_int8_t value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
if (am_hal_gpio_pin_config_read(pin) == AM_HAL_GPIO_OUTPUT)
{
diff --git a/bsp/apollo2/project.uvprojx b/bsp/apollo2/project.uvprojx
index 88ab45403e7..80824fddc77 100644
--- a/bsp/apollo2/project.uvprojx
+++ b/bsp/apollo2/project.uvprojx
@@ -576,6 +576,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -790,23 +809,23 @@
Drivers
- led.c
+ board_rtc.c
1
- board\led.c
+ board\rtc.c
- uart.c
+ i2c.c
1
- board\uart.c
+ board\i2c.c
- board.c
+ pdm.c
1
- board\board.c
+ board\pdm.c
@@ -818,23 +837,23 @@
- gpio.c
+ pwm.c
1
- board\gpio.c
+ board\pwm.c
- spi.c
+ flash.c
1
- board\spi.c
+ board\flash.c
- pdm.c
+ spi.c
1
- board\pdm.c
+ board\spi.c
@@ -846,30 +865,30 @@
- flash.c
+ led.c
1
- board\flash.c
+ board\led.c
- board_rtc.c
+ gpio.c
1
- board\rtc.c
+ board\gpio.c
- pwm.c
+ uart.c
1
- board\pwm.c
+ board\uart.c
- i2c.c
+ board.c
1
- board\i2c.c
+ board\board.c
diff --git a/bsp/asm9260t/project.ewp b/bsp/asm9260t/project.ewp
index 134d3e06b81..d46508e3ab9 100644
--- a/bsp/asm9260t/project.ewp
+++ b/bsp/asm9260t/project.ewp
@@ -2128,6 +2128,9 @@
$PROJ_DIR$\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/asm9260t/project.uvproj b/bsp/asm9260t/project.uvproj
index 0b6f2185600..4bbe4edc980 100644
--- a/bsp/asm9260t/project.uvproj
+++ b/bsp/asm9260t/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f402-start/project.ewp b/bsp/at32/at32f402-start/project.ewp
index 3085c43e852..bc804088b70 100644
--- a/bsp/at32/at32f402-start/project.ewp
+++ b/bsp/at32/at32f402-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f402-start/project.uvproj b/bsp/at32/at32f402-start/project.uvproj
index fd8979767ac..dae82f04254 100644
--- a/bsp/at32/at32f402-start/project.uvproj
+++ b/bsp/at32/at32f402-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f402-start/project.uvprojx b/bsp/at32/at32f402-start/project.uvprojx
index 07528c398d8..b7740dce373 100644
--- a/bsp/at32/at32f402-start/project.uvprojx
+++ b/bsp/at32/at32f402-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f403a-start/project.ewp b/bsp/at32/at32f403a-start/project.ewp
index 7c4f032a7c1..522b1d579bb 100644
--- a/bsp/at32/at32f403a-start/project.ewp
+++ b/bsp/at32/at32f403a-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f403a-start/project.uvproj b/bsp/at32/at32f403a-start/project.uvproj
index 17bbf2a1972..eeb9357d2a9 100644
--- a/bsp/at32/at32f403a-start/project.uvproj
+++ b/bsp/at32/at32f403a-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f403a-start/project.uvprojx b/bsp/at32/at32f403a-start/project.uvprojx
index ff3bb9aafb0..8c9ee790592 100644
--- a/bsp/at32/at32f403a-start/project.uvprojx
+++ b/bsp/at32/at32f403a-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f405-start/project.ewp b/bsp/at32/at32f405-start/project.ewp
index 7ed1e1f1364..2ce614d151c 100644
--- a/bsp/at32/at32f405-start/project.ewp
+++ b/bsp/at32/at32f405-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f405-start/project.uvproj b/bsp/at32/at32f405-start/project.uvproj
index aaabcf2a577..767665d18ea 100644
--- a/bsp/at32/at32f405-start/project.uvproj
+++ b/bsp/at32/at32f405-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f405-start/project.uvprojx b/bsp/at32/at32f405-start/project.uvprojx
index b9f49ae1603..852822e56ea 100644
--- a/bsp/at32/at32f405-start/project.uvprojx
+++ b/bsp/at32/at32f405-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f407-start/project.ewp b/bsp/at32/at32f407-start/project.ewp
index 746e8f4f078..7f0ae3a13ee 100644
--- a/bsp/at32/at32f407-start/project.ewp
+++ b/bsp/at32/at32f407-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f407-start/project.uvproj b/bsp/at32/at32f407-start/project.uvproj
index d1b6e448798..40f636f5098 100644
--- a/bsp/at32/at32f407-start/project.uvproj
+++ b/bsp/at32/at32f407-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f407-start/project.uvprojx b/bsp/at32/at32f407-start/project.uvprojx
index e36635088fc..3a3ed33893b 100644
--- a/bsp/at32/at32f407-start/project.uvprojx
+++ b/bsp/at32/at32f407-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f413-start/project.ewp b/bsp/at32/at32f413-start/project.ewp
index a4f9c6b0f7d..7257fa0b827 100644
--- a/bsp/at32/at32f413-start/project.ewp
+++ b/bsp/at32/at32f413-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f413-start/project.uvproj b/bsp/at32/at32f413-start/project.uvproj
index 61b9ef61214..f30c655ee82 100644
--- a/bsp/at32/at32f413-start/project.uvproj
+++ b/bsp/at32/at32f413-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f413-start/project.uvprojx b/bsp/at32/at32f413-start/project.uvprojx
index 17098e8548f..e5ad69c2fd4 100644
--- a/bsp/at32/at32f413-start/project.uvprojx
+++ b/bsp/at32/at32f413-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f415-start/project.ewp b/bsp/at32/at32f415-start/project.ewp
index 12bb1795cc3..8c144c80842 100644
--- a/bsp/at32/at32f415-start/project.ewp
+++ b/bsp/at32/at32f415-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f415-start/project.uvproj b/bsp/at32/at32f415-start/project.uvproj
index 1815ec90eba..7b92efa2993 100644
--- a/bsp/at32/at32f415-start/project.uvproj
+++ b/bsp/at32/at32f415-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f415-start/project.uvprojx b/bsp/at32/at32f415-start/project.uvprojx
index 5984ce20682..89061a0681d 100644
--- a/bsp/at32/at32f415-start/project.uvprojx
+++ b/bsp/at32/at32f415-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f421-start/project.ewp b/bsp/at32/at32f421-start/project.ewp
index 0955bdac562..a501a9389c9 100644
--- a/bsp/at32/at32f421-start/project.ewp
+++ b/bsp/at32/at32f421-start/project.ewp
@@ -2158,6 +2158,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f421-start/project.uvproj b/bsp/at32/at32f421-start/project.uvproj
index 4787615fa6e..f129883d4a3 100644
--- a/bsp/at32/at32f421-start/project.uvproj
+++ b/bsp/at32/at32f421-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f421-start/project.uvprojx b/bsp/at32/at32f421-start/project.uvprojx
index 4f1f88dc2ee..f5ad54dc84b 100644
--- a/bsp/at32/at32f421-start/project.uvprojx
+++ b/bsp/at32/at32f421-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f423-start/project.ewp b/bsp/at32/at32f423-start/project.ewp
index 8b67c23136c..d7c04c4d544 100644
--- a/bsp/at32/at32f423-start/project.ewp
+++ b/bsp/at32/at32f423-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f423-start/project.uvproj b/bsp/at32/at32f423-start/project.uvproj
index 8ece1e06e38..63d0fb81fd2 100644
--- a/bsp/at32/at32f423-start/project.uvproj
+++ b/bsp/at32/at32f423-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f423-start/project.uvprojx b/bsp/at32/at32f423-start/project.uvprojx
index 81646924c1c..c40b327fddd 100644
--- a/bsp/at32/at32f423-start/project.uvprojx
+++ b/bsp/at32/at32f423-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f425-start/project.ewp b/bsp/at32/at32f425-start/project.ewp
index bcca1ab32ae..253fdb1ad05 100644
--- a/bsp/at32/at32f425-start/project.ewp
+++ b/bsp/at32/at32f425-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f425-start/project.uvproj b/bsp/at32/at32f425-start/project.uvproj
index db2c447666e..2ae2c18a965 100644
--- a/bsp/at32/at32f425-start/project.uvproj
+++ b/bsp/at32/at32f425-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f425-start/project.uvprojx b/bsp/at32/at32f425-start/project.uvprojx
index 5f263093d2f..3886ed930a8 100644
--- a/bsp/at32/at32f425-start/project.uvprojx
+++ b/bsp/at32/at32f425-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f435-start/project.ewp b/bsp/at32/at32f435-start/project.ewp
index ee879169772..ceeb4bf4cb3 100644
--- a/bsp/at32/at32f435-start/project.ewp
+++ b/bsp/at32/at32f435-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f435-start/project.uvproj b/bsp/at32/at32f435-start/project.uvproj
index 81a9c822818..27f3e9ddb2a 100644
--- a/bsp/at32/at32f435-start/project.uvproj
+++ b/bsp/at32/at32f435-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f435-start/project.uvprojx b/bsp/at32/at32f435-start/project.uvprojx
index 9009646ae49..0e328bbdff4 100644
--- a/bsp/at32/at32f435-start/project.uvprojx
+++ b/bsp/at32/at32f435-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f437-start/project.ewp b/bsp/at32/at32f437-start/project.ewp
index 40c055baf7a..48384f69d3a 100644
--- a/bsp/at32/at32f437-start/project.ewp
+++ b/bsp/at32/at32f437-start/project.ewp
@@ -2160,6 +2160,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/at32/at32f437-start/project.uvproj b/bsp/at32/at32f437-start/project.uvproj
index 8904bbc756c..afa087d3c76 100644
--- a/bsp/at32/at32f437-start/project.uvproj
+++ b/bsp/at32/at32f437-start/project.uvproj
@@ -508,6 +508,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/at32f437-start/project.uvprojx b/bsp/at32/at32f437-start/project.uvprojx
index eb3ef0cff68..da97bf83815 100644
--- a/bsp/at32/at32f437-start/project.uvprojx
+++ b/bsp/at32/at32f437-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/at32/libraries/rt_drivers/drv_adc.c b/bsp/at32/libraries/rt_drivers/drv_adc.c
index 73a9c1184c8..1a67c490e80 100644
--- a/bsp/at32/libraries/rt_drivers/drv_adc.c
+++ b/bsp/at32/libraries/rt_drivers/drv_adc.c
@@ -135,8 +135,10 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_int8_t chann
/* adc_x regular channels configuration */
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423)
+ adc_flag_clear(adc_x, ADC_OCCE_FLAG);
adc_ordinary_channel_set(adc_x, (adc_channel_select_type)channel, 1, ADC_SAMPLETIME_247_5);
#else
+ adc_flag_clear(adc_x, ADC_CCE_FLAG);
adc_ordinary_channel_set(adc_x, (adc_channel_select_type)channel, 1, ADC_SAMPLETIME_239_5);
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_gpio.c b/bsp/at32/libraries/rt_drivers/drv_gpio.c
index ddbd4bb5523..a35569441f0 100644
--- a/bsp/at32/libraries/rt_drivers/drv_gpio.c
+++ b/bsp/at32/libraries/rt_drivers/drv_gpio.c
@@ -184,7 +184,7 @@ static void at32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
gpio_bits_write(gpio_port, gpio_pin, (confirm_state)value);
}
-static rt_int8_t at32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t at32_pin_read(rt_device_t dev, rt_base_t pin)
{
gpio_type *gpio_port;
uint16_t gpio_pin;
@@ -198,6 +198,11 @@ static rt_int8_t at32_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_ATPIN(pin);
value = gpio_input_data_bit_read(gpio_port, gpio_pin);
}
+ else
+ {
+ return -RT_EINVAL;
+ }
+
return value;
}
diff --git a/bsp/at91/at91sam9g45/project.uvproj b/bsp/at91/at91sam9g45/project.uvproj
index b2668f42318..3225844b71c 100644
--- a/bsp/at91/at91sam9g45/project.uvproj
+++ b/bsp/at91/at91sam9g45/project.uvproj
@@ -525,6 +525,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1070,23 +1089,23 @@
ktime
- hrtimer.c
+ cputimer.c
1
- ..\..\..\components\drivers\ktime\src\hrtimer.c
+ ..\..\..\components\drivers\ktime\src\cputimer.c
- boottime.c
+ hrtimer.c
1
- ..\..\..\components\drivers\ktime\src\boottime.c
+ ..\..\..\components\drivers\ktime\src\hrtimer.c
- cputimer.c
+ boottime.c
1
- ..\..\..\components\drivers\ktime\src\cputimer.c
+ ..\..\..\components\drivers\ktime\src\boottime.c
@@ -1160,30 +1179,30 @@
Platform
- interrupt.c
+ reset.c
1
- platform\interrupt.c
+ platform\reset.c
- rt_low_level_init.c
+ system_clock.c
1
- platform\rt_low_level_init.c
+ platform\system_clock.c
- system_clock.c
+ interrupt.c
1
- platform\system_clock.c
+ platform\interrupt.c
- reset.c
+ rt_low_level_init.c
1
- platform\reset.c
+ platform\rt_low_level_init.c
diff --git a/bsp/avr32/drivers/drv_gpio.c b/bsp/avr32/drivers/drv_gpio.c
index 4f84a48bf4f..0f9ce2ac321 100644
--- a/bsp/avr32/drivers/drv_gpio.c
+++ b/bsp/avr32/drivers/drv_gpio.c
@@ -59,7 +59,7 @@ static void at32uc3_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t v
}
}
-static rt_int8_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin)
{
RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
return (gpio_get_pin_value(pin) ? PIN_HIGH : PIN_LOW);
diff --git a/bsp/avr32/drivers/drv_soft_i2c.c b/bsp/avr32/drivers/drv_soft_i2c.c
index 756d0db04c3..1aa9bd18566 100644
--- a/bsp/avr32/drivers/drv_soft_i2c.c
+++ b/bsp/avr32/drivers/drv_soft_i2c.c
@@ -34,7 +34,7 @@ static void avr32_i2c_gpio_init(struct avr32_i2c *i2c)
rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
gpio_set_gpio_open_drain_pin(cfg->scl);
-
+
rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
gpio_set_gpio_open_drain_pin(cfg->sda);
}
@@ -50,11 +50,11 @@ static void avr32_set_sda(void *data, rt_int32_t state)
struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data;
if (state)
{
- gpio_set_gpio_open_drain_pin(cfg->sda);
+ gpio_set_gpio_open_drain_pin(cfg->sda);
}
else
{
- gpio_clr_gpio_open_drain_pin(cfg->sda);
+ gpio_clr_gpio_open_drain_pin(cfg->sda);
}
}
@@ -69,11 +69,11 @@ static void avr32_set_scl(void *data, rt_int32_t state)
struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data;
if (state)
{
- gpio_set_gpio_open_drain_pin(cfg->scl);
+ gpio_set_gpio_open_drain_pin(cfg->scl);
}
else
{
- gpio_clr_gpio_open_drain_pin(cfg->scl);
+ gpio_clr_gpio_open_drain_pin(cfg->scl);
}
}
@@ -126,10 +126,10 @@ static rt_err_t avr32_i2c_bus_unlock(const struct avr32_soft_i2c_config *cfg)
{
while (i++ < 9)
{
- gpio_set_gpio_open_drain_pin(cfg->scl);
- rt_hw_us_delay(100);
- gpio_clr_gpio_open_drain_pin(cfg->scl);
- rt_hw_us_delay(100);
+ gpio_set_gpio_open_drain_pin(cfg->scl);
+ rt_hw_us_delay(100);
+ gpio_clr_gpio_open_drain_pin(cfg->scl);
+ rt_hw_us_delay(100);
}
}
if (PIN_LOW == gpio_get_gpio_open_drain_pin_output_value(cfg->sda))
diff --git a/bsp/beaglebone/drivers/gpio.c b/bsp/beaglebone/drivers/gpio.c
index 1add5015326..90c62a0cf6c 100644
--- a/bsp/beaglebone/drivers/gpio.c
+++ b/bsp/beaglebone/drivers/gpio.c
@@ -170,7 +170,7 @@ static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t
}
}
-static rt_int8_t am33xx_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t am33xx_pin_read(struct rt_device *device, rt_base_t pin)
{
RT_ASSERT(pin >= 0 && pin < 128);
rt_base_t gpiox = pin >> 5;
diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c
index c297b743718..5cf0a72aa57 100644
--- a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c
+++ b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c
@@ -106,7 +106,7 @@ static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
hal_gpio_write(PORT_SFR(port), gpio_pin, (rt_uint8_t)value);
}
-static rt_int8_t ab32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t ab32_pin_read(rt_device_t dev, rt_base_t pin)
{
rt_uint8_t port = PIN_PORT(pin);
rt_uint8_t gpio_pin = pin - port_table[port].total_pin;
diff --git a/bsp/bouffalo_lab/bl808/d0/.config b/bsp/bouffalo_lab/bl808/d0/.config
index 653919eb5db..4762aa135ea 100644
--- a/bsp/bouffalo_lab/bl808/d0/.config
+++ b/bsp/bouffalo_lab/bl808/d0/.config
@@ -129,6 +129,7 @@ CONFIG_RT_USING_DFS_V2=y
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_PTYFS=y
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
@@ -159,8 +160,6 @@ CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
-CONFIG_RT_USING_TTY=y
-# CONFIG_RT_TTY_DEBUG is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
@@ -300,10 +299,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024
CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
CONFIG_LWP_TID_MAX_NR=64
CONFIG_RT_LWP_SHM_MAX_NR=64
-# CONFIG_LWP_UNIX98_PTY is not set
CONFIG_RT_USING_LDSO=y
# CONFIG_ELF_DEBUG_ENABLE is not set
# CONFIG_ELF_LOAD_RANDOMIZE is not set
+CONFIG_LWP_USING_TERMINAL=y
+CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
#
# Memory management
diff --git a/bsp/bouffalo_lab/bl808/d0/rtconfig.h b/bsp/bouffalo_lab/bl808/d0/rtconfig.h
index 8cd622a8b66..e6bb7edf01a 100755
--- a/bsp/bouffalo_lab/bl808/d0/rtconfig.h
+++ b/bsp/bouffalo_lab/bl808/d0/rtconfig.h
@@ -91,6 +91,7 @@
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_PTYFS
#define RT_USING_PAGECACHE
/* page cache config */
@@ -113,7 +114,6 @@
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_TTY
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
@@ -180,6 +180,8 @@
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
+#define LWP_USING_TERMINAL
+#define LWP_PTY_MAX_PARIS_LIMIT 64
/* Memory management */
diff --git a/bsp/bouffalo_lab/bl808/m0/.config b/bsp/bouffalo_lab/bl808/m0/.config
index 5da01fa7812..5238482c911 100755
--- a/bsp/bouffalo_lab/bl808/m0/.config
+++ b/bsp/bouffalo_lab/bl808/m0/.config
@@ -218,6 +218,7 @@ CONFIG_RT_WLAN_SCAN_WAIT_MS=10000
CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000
CONFIG_RT_WLAN_SCAN_SORT=y
CONFIG_RT_WLAN_MSH_CMD_ENABLE=y
+CONFIG_RT_WLAN_JOIN_SCAN_BY_MGNT=y
CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y
CONFIG_AUTO_CONNECTION_PERIOD_MS=2000
CONFIG_RT_WLAN_CFG_ENABLE=y
diff --git a/bsp/bouffalo_lab/bl808/m0/rtconfig.h b/bsp/bouffalo_lab/bl808/m0/rtconfig.h
index a4a0de1b800..3b81f39eaa4 100644
--- a/bsp/bouffalo_lab/bl808/m0/rtconfig.h
+++ b/bsp/bouffalo_lab/bl808/m0/rtconfig.h
@@ -133,6 +133,7 @@
#define RT_WLAN_CONNECT_WAIT_MS 10000
#define RT_WLAN_SCAN_SORT
#define RT_WLAN_MSH_CMD_ENABLE
+#define RT_WLAN_JOIN_SCAN_BY_MGNT
#define RT_WLAN_AUTO_CONNECT_ENABLE
#define AUTO_CONNECTION_PERIOD_MS 2000
#define RT_WLAN_CFG_ENABLE
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c
index 7cbe6dddfce..c9b5db6d4f6 100644
--- a/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c
@@ -49,7 +49,7 @@ static struct bl_adc bl_adc_obj;
struct _adc_channel_cfg
{
struct bflb_adc_channel_s chan;
- uint16_t chan_gpio;
+ uint16_t chan_gpio;
};
static struct _adc_channel_cfg chan[] = {
@@ -197,7 +197,7 @@ int rt_hw_adc_init(void)
LOG_E("adc dma device not found");
return -RT_ERROR;
}
-
+
bl_adc_obj.sem = rt_sem_create("adc_sem", 0, RT_IPC_FLAG_PRIO);
if(bl_adc_obj.sem == RT_NULL)
{
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c
index 406cf3e384e..763dd1dd75c 100755
--- a/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c
@@ -48,7 +48,7 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
bflb_gpio_reset(gpio, pin);
}
-static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin)
{
return bflb_gpio_read(gpio, pin);
}
diff --git a/bsp/ck802/libraries/include/drv_eth.h b/bsp/ck802/libraries/include/drv_eth.h
index 12b5d182139..2c106fea733 100644
--- a/bsp/ck802/libraries/include/drv_eth.h
+++ b/bsp/ck802/libraries/include/drv_eth.h
@@ -33,17 +33,17 @@ typedef struct csi_driver_version {
} csi_drv_version_t;
/* General return codes */
-#define CSI_ETH_OK 0 ///< Operation succeeded
+#define CSI_ETH_OK 0 ///< Operation succeeded
#define CSI_ETH_ERROR CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error
#define CSI_ETH_ERROR_BUSY CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy
#define CSI_ETH_ERROR_TIMEOUT CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred
#define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported
#define CSI_ETH_ERROR_PARAMETER CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error
-#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors
+#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors
/**
\brief General power states
-*/
+*/
typedef enum eth_power_state {
CSI_ETH_POWER_OFF, ///< Power off: no operation possible
CSI_ETH_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
diff --git a/bsp/ck802/libraries/include/drv_eth_phy.h b/bsp/ck802/libraries/include/drv_eth_phy.h
index adf4aa01714..27ef4155954 100644
--- a/bsp/ck802/libraries/include/drv_eth_phy.h
+++ b/bsp/ck802/libraries/include/drv_eth_phy.h
@@ -65,8 +65,8 @@ csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle);
/**
\brief Initialize Ethernet PHY Device.
- \param[in] fn_read
- \param[in] fn_write
+ \param[in] fn_read
+ \param[in] fn_write
\return ethernet phy handle
*/
eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write);
diff --git a/bsp/cvitek/.gitignore b/bsp/cvitek/.gitignore
index 97d926d9575..93694d216fc 100755
--- a/bsp/cvitek/.gitignore
+++ b/bsp/cvitek/.gitignore
@@ -1,2 +1,6 @@
+cvitek_bootloader
fip.bin
-boot.sd
\ No newline at end of file
+boot.sd
+output
+c906_little/board/script
+Image.lzma
\ No newline at end of file
diff --git a/bsp/cvitek/README.md b/bsp/cvitek/README.md
index d9c7ae10777..f1bb1ee3cea 100755
--- a/bsp/cvitek/README.md
+++ b/bsp/cvitek/README.md
@@ -8,20 +8,43 @@
| 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 |
| ------- | ------- |------- | -------- | -------- |
-| cv1800b | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU,运行 RT-SMART 模式 |
+| cv180x | RISC-V C906 | 64MByte | uart0 | 支持 MMU, 支持 RT-Thread 标准版 和 RT-SMART 模式,默认运行 RT-Thread 标准版本 |
+| cv181x | RISC-V C906 或 Cortex A53 通过硬件 IO 二选一 | 64MByte | uart0 | 支持 MMU, 支持 RT-Thread 标准版 和 RT-SMART 版,默认运行 RT-Thread 标准版本 |
- 小核
| 目录 | 内存大小 | 默认日志串口 | 备注 |
| ---- | ------- | -------- | --- |
-| c906-little | 与大核共享 | uart1 | 无 MMU,运行 RT-Thread 标准 |
+| c906-little | 与大核共享 | uart1 | 无 MMU,运行 RT-Thread 标准版 |
> 注:异构芯片需单独编译每个核的 OS
+## 编译
+异构芯片需单独编译每个核的 OS,在大/小核对应的目录下,依次执行:
+
+1. 开发板选择
+Linux平台下,可以先执行:
+```shell
+$ scons --menuconfig
+```
+
+选择当前需要编译的目标开发板类型
+```shell
+Board Type (milkv-duo) --->
+ ( ) milkv-duo
+ ( ) milkv-duo-spinor
+ (X) milkv-duo256m
+ ( ) milkv-duo256m-spinor
+```
+
+2. 编译
+```shell
+$ scons
+```
## 运行
-编译成功后,会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件,其中大核运行文件在 `boot.sd` 中,小核的运行文件在 `fip.bin` 中。
+编译成功后,会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件,其中大核运行文件在 `boot.sd` 中,小核的运行文件在 `fip.bin` 中。
1. 将 SD 卡分为 2 个分区,第 1 个分区用于存放 bin 文件,第 2 个分区用于作为数据存储分区,分区格式为 `FAT32`。
2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。
@@ -36,13 +59,28 @@
| gpio | 支持 | |
| i2c | 支持 | |
| adc | 支持 | |
+| spi | 支持 | 默认CS引脚,每个数据之间CS会拉高,请根据时序选择GPIO作为CS。若读取数据,tx需持续dummy数据。|
## 支持开发板
- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
+- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m)
## FAQ
1. 如遇到不能正常编译,请先使用 `scons --menuconfig` 重新生成配置。
+2. 错误:./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory
+
+可在 [http://security.ubuntu.com/ubuntu/pool/main/o/openssl](http://security.ubuntu.com/ubuntu/pool/main/o/openssl) 下载 `libssl1.1_1.1.1f-1ubuntu2_amd64.deb` 文件后安装即可解决。
+或使用以下命令下载安装:
+```shell
+$ wget http://security.ubuntu.com/ubuntu/pool/main/o/openssl/libssl1.1_1.1.1f-1ubuntu2_amd64.deb
+$ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb
+```
+
+3. 如发现切换开发板编译正常,但无法正常打包,请切换至自动下载的 `cvi_bootloader` 目录,并手工运行 `git pull` 更新,或删除该目录后重新自动下载。
+
## 联系人信息
-维护人:[flyingcys](https://github.com/flyingcys)
\ No newline at end of file
+维护人:[flyingcys](https://github.com/flyingcys)
+
+更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io)
\ No newline at end of file
diff --git a/bsp/cvitek/board_env.sh b/bsp/cvitek/board_env.sh
new file mode 100755
index 00000000000..dcd4572702c
--- /dev/null
+++ b/bsp/cvitek/board_env.sh
@@ -0,0 +1,45 @@
+#!/bin/bash
+
+function get_board_type()
+{
+ BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M" "CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINAND")
+ BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m" "milkv-duo256m-spinor" "milkv-duo256m-spinand")
+ STORAGE_VAUE=("sd" "spinor" "spinand" "sd" "spinor" "spinand")
+
+ for ((i=0;i<${#BOARD_CONFIG[@]};i++))
+ do
+ config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2)
+ if [ "$config_value" == "y" ]; then
+ BOARD_TYPE=${BOARD_VALUE[i]}
+ STORAGE_TYPE=${STORAGE_VAUE[i]}
+ break
+ fi
+ done
+ export BOARD_TYPE=${BOARD_TYPE}
+ export STORAGE_TYPE=${STORAGE_TYPE}
+}
+
+function check_bootloader()
+{
+ restult=$(curl -m 10 -s http://www.ip-api.com/json)
+ COUNTRY=$(echo $restult | sed 's/.*"country":"\([^"]*\)".*/\1/')
+ echo "Country: $COUNTRY"
+
+ if [ "$COUNTRY" == "China" ]; then
+ BOOTLOADER_URL=https://gitee.com/flyingcys/cvitek_bootloader
+ else
+ BOOTLOADER_URL=https://github.com/flyingcys/cvitek_bootloader
+ fi
+
+ if [ ! -d cvitek_bootloader ]; then
+ echo "cvitek_bootloader not exist, clone it from ${BOOTLOADER_URL}"
+ git clone ${BOOTLOADER_URL}
+
+ if [ $? -ne 0 ]; then
+ echo "Failed to clone ${BOOTLOADER_URL} !"
+ exit 1
+ fi
+fi
+}
+
+
diff --git a/bsp/cvitek/c906_little/.config b/bsp/cvitek/c906_little/.config
index 56756b1f7d2..0944943d7fe 100644
--- a/bsp/cvitek/c906_little/.config
+++ b/bsp/cvitek/c906_little/.config
@@ -1080,6 +1080,7 @@ CONFIG_RT_USING_UART1=y
CONFIG_UART_IRQ_BASE=30
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_RTC is not set
@@ -1087,3 +1088,7 @@ CONFIG_BSP_USING_C906_LITTLE=y
CONFIG_PLIC_PHY_ADDR=0x70000000
CONFIG_IRQ_MAX_NR=128
CONFIG_TIMER_CLK_FREQ=25000000
+# CONFIG_BOARD_TYPE_MILKV_DUO is not set
+# CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set
+CONFIG_BOARD_TYPE_MILKV_DUO256M=y
+# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set
diff --git a/bsp/cvitek/c906_little/Kconfig b/bsp/cvitek/c906_little/Kconfig
index 2e6980adea4..d981d97abe7 100755
--- a/bsp/cvitek/c906_little/Kconfig
+++ b/bsp/cvitek/c906_little/Kconfig
@@ -37,4 +37,22 @@ config IRQ_MAX_NR
config TIMER_CLK_FREQ
int
- default 25000000
\ No newline at end of file
+ default 25000000
+
+choice
+ prompt "Board Type"
+ default BOARD_TYPE_MILKV_DUO256M
+
+ config BOARD_TYPE_MILKV_DUO
+ bool "milkv-duo"
+
+ config BOARD_TYPE_MILKV_DUO_SPINOR
+ bool "milkv-duo-spinor"
+
+ config BOARD_TYPE_MILKV_DUO256M
+ bool "milkv-duo256m"
+
+ config BOARD_TYPE_MILKV_DUO256M_SPINOR
+ bool "milkv-duo256m-spinor"
+
+endchoice
diff --git a/bsp/cvitek/c906_little/README.md b/bsp/cvitek/c906_little/README.md
index 71a3d6135d3..14bd1a7e499 100755
--- a/bsp/cvitek/c906_little/README.md
+++ b/bsp/cvitek/c906_little/README.md
@@ -17,20 +17,39 @@ $ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin
```
## 编译
-1. Linux平台下,可以先执行:
+1. 依赖安装
+
+```shell
+$ sudo apt install -y scons libncurses5-dev wget flex bison
+```
+
+
+2. Linux平台下,先执行:
```shell
$ scons --menuconfig
```
-它会自动下载env相关脚本到~/.env目录,然后执行
+选择当前需要编译的目标开发板类型:
+```shell
+Board Type (milkv-duo) --->
+ ( ) milkv-duo
+ ( ) milkv-duo-spinor
+ (X) milkv-duo256m
+ ( ) milkv-duo256m-spinor
+```
+
+它会自动下载 env 相关脚本到 ~/.env 目录,然后执行
```shell
$ source ~/.env/env.sh
$ pkgs --update
```
-更新完软件包后,执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令,在指定工具链位置的同时直接编译。编译正确无误,会产生rtthread.elf文件。
+更新完软件包后,执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令,在指定工具链位置的同时直接编译。编译正确无误,会产生rtthread.elf 文件。
编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包,并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。
+第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录,请耐心等待。
+
+下载完成后会自动解压、编译,后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件,可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。
## 运行
1. 将 SD 卡分为 2 个分区,第 1 个分区用于存放 bin 文件,第 2 个分区用于作为数据存储分区,分区格式为 `FAT32`。
@@ -49,4 +68,6 @@ HW_HEAP_BEGIN:83f74dc0 RT_HW_HEAP_END:84000000 size: 569920
2006 - 2022 Copyright by RT-Thread team
Hello, RISC-V!
msh />
-```
\ No newline at end of file
+```
+
+> 注:c906 小核默认日志串口为 uart1
\ No newline at end of file
diff --git a/bsp/cvitek/c906_little/README_en.md b/bsp/cvitek/c906_little/README_en.md
new file mode 100755
index 00000000000..df6d28fa9c8
--- /dev/null
+++ b/bsp/cvitek/c906_little/README_en.md
@@ -0,0 +1,72 @@
+# c906_little bsp
+This BSP is a coprocessor in the cv18xx series processor, using RISCV C906 @ 700Mhz.
+Features:
+- No MMU
+- Integrated Floating-point Unit (FPU)
+
+## Toolchain Download
+Download the toolchain for `riscv64-unknown-elf-gcc`: [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz)
+
+> Note:
+Current BSP only supports Linux compilation.
+
+After correct decompression, add the local path of the `riscv64-unknown-elf-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable.
+
+```shell
+$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin
+```
+
+## Compilation
+1. Dependency Installation
+
+```shell
+$ sudo apt install -y scons libncurses5-dev wget flex bison
+```
+
+2. On Linux platform, execute:
+```shell
+$ scons --menuconfig
+```
+
+Choose the target development board type that needs to be compiled:
+```shell
+Board Type (milkv-duo) --->
+ ( ) milkv-duo
+ ( ) milkv-duo-spinor
+ (X) milkv-duo256m
+ ( ) milkv-duo256m-spinor
+```
+
+It will automatically download env related scripts to the ~/.env directory, then execute
+```shell
+$ source ~/.env/env.sh
+$ pkgs --update
+```
+After updating the software packages, execute `scons -j10` or `scons -j10 --verbose` to compile this BSP. Or use the `scons --exec-path="GCC toolchain path"` command to compile directly while specifying the toolchain location. If the compilation is correct, the rtthread.elf file will be generated.
+
+After the compilation is completed, the script automatically calls the `combine-fip.sh` script for packaging, and generates `fip.sd`, which is the c906_little file for SD card startup.
+
+The first time the `combine-fip.sh` script is called, it will automatically download the required `opsbsbi`, `fsbl`, `uboot`, and other related files to the `bsp/cvitek/cvitek_bootloader` directory, please be patient.
+
+After downloading, it will automatically decompress and compile. Subsequently, when compiling the same type of development board again, only the relevant files will be called to package and synthesize `fip.bin`. If you need to manually compile the related `cvitek_bootloader` files, you can execute `bash build.sh lunch` in the `bsp/cvitek/cvitek_bootloader` directory to choose the corresponding development board for compilation.
+
+## Running
+1. Divide the SD card into 2 partitions, the 1st partition is used to store bin files, and the 2nd partition is used as a data storage partition, with the partition format being `FAT32`.
+2. Copy the `fip.bin` and `boot.sd` from the root directory into the 1st partition of the SD card. Subsequent firmware updates only require copying the `fip.sd` file.
+Where:
+- fip.bin: fsbl, opensbi, uboot, c906_little packaged bin file
+- boot.sd: bin file packaged by the main kernel
+
+After updating `fip.sd`, restarting will show the output information on the serial port:
+```shell
+HW_HEAP_BEGIN:83f74dc0 RT_HW_HEAP_END:84000000 size: 569920
+
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.1.0 build Jan 27 2024 22:45:49
+ 2006 - 2022 Copyright by RT-Thread team
+Hello, RISC-V!
+msh />
+```
+
+> Note: The default log serial port for the c906 little core is uart1
\ No newline at end of file
diff --git a/bsp/cvitek/c906_little/SConstruct b/bsp/cvitek/c906_little/SConstruct
index b331ef4db85..0a1878479d0 100755
--- a/bsp/cvitek/c906_little/SConstruct
+++ b/bsp/cvitek/c906_little/SConstruct
@@ -37,5 +37,9 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
# include libraries
objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))
+if GetDepend('BOARD_TYPE_MILKV_DUO256M'):
+ env['LINKFLAGS'] = env['LINKFLAGS'].replace('cv180x_lscript.ld', 'cv181x_lscript.ld')
+ env['LINKFLAGS'] = env['LINKFLAGS'].replace('-L board/script/cv180x', '-L board/script/cv181x')
+
# make a building
DoBuilding(TARGET, objs)
diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig
index 3780246c591..6a0d10c0f30 100755
--- a/bsp/cvitek/c906_little/board/Kconfig
+++ b/bsp/cvitek/c906_little/board/Kconfig
@@ -45,6 +45,11 @@ menu "General Drivers Configuration"
select RT_USING_ADC
default n
+ config BSP_USING_SPI
+ bool "Using SPI"
+ select RT_USING_SPI
+ default n
+
menuconfig BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
diff --git a/bsp/cvitek/c906_little/cv180x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld
similarity index 98%
rename from bsp/cvitek/c906_little/cv180x_lscript.ld
rename to bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld
index 180e3193119..a91067f7250 100755
--- a/bsp/cvitek/c906_little/cv180x_lscript.ld
+++ b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld
@@ -7,6 +7,8 @@
* Date Author Notes
* 2024/01/11 flyingcys The first version
*/
+INCLUDE ./cvi_board_memmap.ld
+
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;
/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */
/*_HEAP_SIZE = 0x20000;*/
@@ -15,9 +17,6 @@ _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
-CVIMMAP_FREERTOS_ADDR = 0x83f40000;
-CVIMMAP_FREERTOS_SIZE = 0xc0000;
-
/* Define Memories in the system */
MEMORY
diff --git a/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld
new file mode 100755
index 00000000000..9f2f1558260
--- /dev/null
+++ b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld
@@ -0,0 +1,30 @@
+CONFIG_SYS_TEXT_BASE = 0x80200000;
+CVIMMAP_ATF_SIZE = 0x80000;
+CVIMMAP_BOOTLOGO_ADDR = 0x82473000;
+CVIMMAP_BOOTLOGO_SIZE = 0x0;
+CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82300000;
+CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x813ffc00;
+CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400;
+CVIMMAP_DRAM_BASE = 0x80000000;
+CVIMMAP_DRAM_SIZE = 0x4000000;
+CVIMMAP_FREERTOS_ADDR = 0x83f40000;
+CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x0;
+CVIMMAP_FREERTOS_SIZE = 0xc0000;
+CVIMMAP_FSBL_C906L_START_ADDR = 0x83f40000;
+CVIMMAP_FSBL_UNZIP_ADDR = 0x81400000;
+CVIMMAP_FSBL_UNZIP_SIZE = 0xf00000;
+CVIMMAP_H26X_BITSTREAM_ADDR = 0x82473000;
+CVIMMAP_H26X_BITSTREAM_SIZE = 0x0;
+CVIMMAP_H26X_ENC_BUFF_ADDR = 0x82473000;
+CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0;
+CVIMMAP_ION_ADDR = 0x82473000;
+CVIMMAP_ION_SIZE = 0x1acd000;
+CVIMMAP_ISP_MEM_BASE_ADDR = 0x82473000;
+CVIMMAP_ISP_MEM_BASE_SIZE = 0x0;
+CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000;
+CVIMMAP_KERNEL_MEMORY_SIZE = 0x3f40000;
+CVIMMAP_MONITOR_ADDR = 0x80000000;
+CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000;
+CVIMMAP_OPENSBI_SIZE = 0x80000;
+CVIMMAP_UIMAG_ADDR = 0x81400000;
+CVIMMAP_UIMAG_SIZE = 0xf00000;
\ No newline at end of file
diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld
new file mode 100755
index 00000000000..a91067f7250
--- /dev/null
+++ b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024/01/11 flyingcys The first version
+ */
+INCLUDE ./cvi_board_memmap.ld
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;
+/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */
+/*_HEAP_SIZE = 0x20000;*/
+
+_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
+_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
+_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE
+}
+
+/* Specify the default entry point to the program */
+
+/*ENTRY(_vector_table)*/
+ENTRY(_start)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+ KEEP (*(.vectors))
+ *(.boot)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu_warning)
+ *(.gcc_execpt_table)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.ARM.extab)
+ *(.gnu.linkonce.armextab.*)
+
+ /* section information for finsh shell */
+ . = ALIGN(8);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(8);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(8);
+
+ /* section information for initial. */
+ . = ALIGN(8);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(8);
+
+ __rt_utest_tc_tab_start = .;
+ KEEP(*(UtestTcTab))
+ __rt_utest_tc_tab_end = .;
+} > psu_ddr_0_MEM_0
+
+.init (ALIGN(64)) : {
+ KEEP (*(.init))
+} > psu_ddr_0_MEM_0
+
+.fini (ALIGN(64)) : {
+ KEEP (*(.fini))
+} > psu_ddr_0_MEM_0
+
+.interp : {
+ KEEP (*(.interp))
+} > psu_ddr_0_MEM_0
+
+.note-ABI-tag : {
+ KEEP (*(.note-ABI-tag))
+} > psu_ddr_0_MEM_0
+
+.rodata : {
+ . = ALIGN(64);
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.srodata*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > psu_ddr_0_MEM_0
+
+.rodata1 : {
+ . = ALIGN(64);
+ __rodata1_start = .;
+ *(.rodata1)
+ *(.rodata1.*)
+ __rodata1_end = .;
+} > psu_ddr_0_MEM_0
+
+.data : {
+ . = ALIGN(64);
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.d.*)
+ *(.jcr)
+ *(.got)
+ *(.got.plt)
+ _edata = .;
+} > psu_ddr_0_MEM_0
+
+.data1 : {
+ . = ALIGN(64);
+ __data1_start = .;
+ *(.data1)
+ *(.data1.*)
+ __data1_end = .;
+} > psu_ddr_0_MEM_0
+
+.got : {
+ *(.got)
+} > psu_ddr_0_MEM_0
+
+.got1 : {
+ *(.got1)
+} > psu_ddr_0_MEM_0
+
+.got2 : {
+ *(.got2)
+} > psu_ddr_0_MEM_0
+
+.ctors : {
+ . = ALIGN(64);
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.dtors : {
+ . = ALIGN(64);
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.fixup : {
+ __fixup_start = .;
+ *(.fixup)
+ __fixup_end = .;
+} > psu_ddr_0_MEM_0
+
+.eh_frame : {
+ *(.eh_frame)
+} > psu_ddr_0_MEM_0
+
+.eh_framehdr : {
+ __eh_framehdr_start = .;
+ *(.eh_framehdr)
+ __eh_framehdr_end = .;
+} > psu_ddr_0_MEM_0
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > psu_ddr_0_MEM_0
+
+.bss (NOLOAD) : {
+ . = ALIGN(64);
+ _bss = .;
+ *(.bss)
+ *(.bss.*)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(64);
+ _ebss = .;
+} > psu_ddr_0_MEM_0
+
+/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/
+ _data_lma = LOADADDR(.data);
+
+/* Generate Stack and Heap definitions */
+.stack (NOLOAD) : {
+ . = ALIGN(64);
+ _stack_end_end = .;
+ . += _STACK_SIZE;
+ _stack_top = .;
+ __rt_rvstack = .;
+} > psu_ddr_0_MEM_0
+
+.heap (NOLOAD) : {
+ . = ALIGN(64);
+ _heap = .;
+ HeapBase = .;
+ _heap_start = .;
+ *(.heap*)
+ /*. += _HEAP_SIZE;*/
+ /*_heap_size = _HEAP_SIZE; */
+ _heap_end = .;
+ HeapLimit = .;
+} > psu_ddr_0_MEM_0
+
+HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0);
+_end = .;
+}
+
diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld
new file mode 100755
index 00000000000..d2b87440447
--- /dev/null
+++ b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld
@@ -0,0 +1,32 @@
+CONFIG_SYS_TEXT_BASE = 0x80200000;
+CVIMMAP_ATF_SIZE = 0x80000;
+CVIMMAP_BOOTLOGO_ADDR = 0x8b13e000;
+CVIMMAP_BOOTLOGO_SIZE = 0x1c2000;
+CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82800000;
+CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x817ffc00;
+CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400;
+CVIMMAP_DRAM_BASE = 0x80000000;
+CVIMMAP_DRAM_SIZE = 0x10000000;
+CVIMMAP_FRAMEBUFFER_ADDR = 0x8b13e000;
+CVIMMAP_FRAMEBUFFER_SIZE = 0x1c2000;
+CVIMMAP_FREERTOS_ADDR = 0x8fe00000;
+CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x1600000;
+CVIMMAP_FREERTOS_SIZE = 0x200000;
+CVIMMAP_FSBL_C906L_START_ADDR = 0x8fe00000;
+CVIMMAP_FSBL_UNZIP_ADDR = 0x81800000;
+CVIMMAP_FSBL_UNZIP_SIZE = 0x1000000;
+CVIMMAP_H26X_BITSTREAM_ADDR = 0x8b300000;
+CVIMMAP_H26X_BITSTREAM_SIZE = 0x200000;
+CVIMMAP_H26X_ENC_BUFF_ADDR = 0x8b500000;
+CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0;
+CVIMMAP_ION_ADDR = 0x8b300000;
+CVIMMAP_ION_SIZE = 0x4b00000;
+CVIMMAP_ISP_MEM_BASE_ADDR = 0x8b500000;
+CVIMMAP_ISP_MEM_BASE_SIZE = 0x1400000;
+CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000;
+CVIMMAP_KERNEL_MEMORY_SIZE = 0xfe00000;
+CVIMMAP_MONITOR_ADDR = 0x80000000;
+CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000;
+CVIMMAP_OPENSBI_SIZE = 0x80000;
+CVIMMAP_UIMAG_ADDR = 0x81800000;
+CVIMMAP_UIMAG_SIZE = 0x1000000;
\ No newline at end of file
diff --git a/bsp/cvitek/c906_little/rtconfig.h b/bsp/cvitek/c906_little/rtconfig.h
index 40db54549b1..d4fced8b338 100755
--- a/bsp/cvitek/c906_little/rtconfig.h
+++ b/bsp/cvitek/c906_little/rtconfig.h
@@ -268,5 +268,6 @@
#define PLIC_PHY_ADDR 0x70000000
#define IRQ_MAX_NR 128
#define TIMER_CLK_FREQ 25000000
+#define BOARD_TYPE_MILKV_DUO256M
#endif
diff --git a/bsp/cvitek/c906_little/rtconfig.py b/bsp/cvitek/c906_little/rtconfig.py
index dd7ed95f05a..50c32d55617 100755
--- a/bsp/cvitek/c906_little/rtconfig.py
+++ b/bsp/cvitek/c906_little/rtconfig.py
@@ -18,7 +18,7 @@
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
- EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin'
+ EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
@@ -47,9 +47,10 @@
CFLAGS += ' -DCONFIG_64BIT'
LINKER_SCRIPTS = r'cv180x_lscript.ld'
+ LINKER_SCRIPTS_PATH = r' -L board/script/cv180x'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
- LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+ LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LINKER_SCRIPTS_PATH
CPATH = ''
LPATH = ''
@@ -63,4 +64,4 @@
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-POST_ACTION += 'cd .. && ./combine-fip.sh c906_little/rtthread.bin\n'
\ No newline at end of file
+POST_ACTION += 'cd .. && bash combine-fip.sh ' + os.getcwd() + ' rtthread.bin' + ' \n'
\ No newline at end of file
diff --git a/bsp/cvitek/combine-fip.sh b/bsp/cvitek/combine-fip.sh
index fee521077c0..414da79eb34 100755
--- a/bsp/cvitek/combine-fip.sh
+++ b/bsp/cvitek/combine-fip.sh
@@ -1,23 +1,49 @@
#!/bin/bash
-set -e
-
-LITTLE_BIN=$1
-
-. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \
-./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \
- 'fip.bin' \
- --MONITOR_RUNADDR="${MONITOR_RUNADDR}" \
- --BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \
- --CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \
- --NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \
- --NAND_INFO='00000000'\
- --BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \
- --BLCP_IMG_RUNADDR=0x05200200 \
- --BLCP_PARAM_LOADADDR=0 \
- --BLCP=pre-build/fsbl/test/empty.bin \
- --DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \
- --BLCP_2ND=$LITTLE_BIN \
- --MONITOR='pre-build/fw_dynamic.bin' \
- --LOADER_2ND='pre-build/u-boot-raw.bin' \
- --compress='lzma'
\ No newline at end of file
+PROJECT_PATH=$1
+IMAGE_NAME=$2
+
+if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then
+ echo "Usage: $0 "
+ exit 1
+fi
+
+ROOT_PATH=$(pwd)
+echo $ROOT_PATH
+
+. board_env.sh
+
+get_board_type
+echo "board_type: ${BOARD_TYPE}"
+
+check_bootloader || exit 0
+
+export BLCP_2ND_PATH=${PROJECT_PATH}/${IMAGE_NAME}
+
+pushd cvitek_bootloader
+
+. env.sh
+
+get_build_board ${BOARD_TYPE}
+
+echo "board: ${MV_BOARD_LINK}"
+
+if [ ! -d opensbi/build/platform/generic ] || [ ! -d fsbl/build/${MV_BOARD_LINK} ] || [ ! -d u-boot-2021.10/build/${MV_BOARD_LINK} ]; then
+ do_build
+
+ CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]')
+ cp -rf build/output/${MV_BOARD_LINK}/cvi_board_memmap.ld ${ROOT_PATH}/c906_little/board/script/${CHIP_ARCH_L}
+else
+ echo "Build already done, skip build"
+
+ do_combine
+
+ if [ $? -ne 0 ]; then
+ do_build
+ fi
+fi
+
+popd
+
+mkdir -p output/${MV_BOARD}
+cp -rf cvitek_bootloader/install/soc_${MV_BOARD_LINK}/fip.bin output/${MV_BOARD}/fip.bin
\ No newline at end of file
diff --git a/bsp/cvitek/cv1800b/.gitignore b/bsp/cvitek/cv1800b/.gitignore
deleted file mode 100755
index f58350d6cff..00000000000
--- a/bsp/cvitek/cv1800b/.gitignore
+++ /dev/null
@@ -1,5 +0,0 @@
-cv1800b_milkv_duo_sd.dtb
-Image
-Image.lzma
-multi.its
-boot.sd
\ No newline at end of file
diff --git a/bsp/cvitek/cv1800b/README_en.md b/bsp/cvitek/cv1800b/README_en.md
deleted file mode 100755
index 19da2982c83..00000000000
--- a/bsp/cvitek/cv1800b/README_en.md
+++ /dev/null
@@ -1,130 +0,0 @@
-[中文](README.md) | **English**
-
-## Overview
-CV180ZB/CV1800B/CV1801B are high-performance, low-power chips designed for consumer surveillance IP cameras, smart home devices, and other product areas. They integrate H.264/H.265 video compression encoders and ISPs, and support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing professional-grade video image quality to customers.
-
-1. Processor Core
-- Main processor: RISCV C906 @ 1.0Ghz
- - 32KB I-cache, 64KB D-Cache
- - Integrated vector and floating-point units (FPU).
-- Coprocessor: RISCV C906 @ 700Mhz
- - Integrated floating-point unit (FPU).
-
-2. Memory Interface
-- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, capacity of 512Mbit (64MB).
-- Support for SPI NOR flash interface (1.8V / 3.0V)
- - Support for 1, 2, 4-wire modes
- - Maximum support of 256MBytes
-- Support for SPI Nand flash interface (1.8V / 3.0V)
- - Support for 1KB/2KB/4KB page (corresponding to a maximum capacity of 16GB/32GB/64GB)
- - Use the built-in ECC module of the device itself
-
-3. Peripherals
-- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART.
-- Up to 3x I2C
-- Up to 5x UART
-- Up to 1x SDIO1
-- Up to 1x SPI
-- Up to 2x ADC
-- Up to 7x PWM
-- Up to 1x RUN
-- Up to 1x JTAG
-- Integrated MAC PHY supporting 10/100Mbps full-duplex or half-duplex mode
-- One USB Host / device interface
-
-## Toolchain Download
-Download the `riscv64-unknown-linux-musl-gcc` toolchain from: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2)
-
-> Note:
-The current BSP only supports Linux compilation.
-
-After correct extraction, add the local path of the `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable.
-
-```shell
-$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin
-```
-
-## Compilation
-1. Installing Dependencies
-```shell
-$ sudo apt install -y device-tree-compiler
-```
-On the Linux platform, you can execute:
-
-```shell
-$ scons --menuconfig
-```
-It will automatically download environment-related scripts to the ~/.env directory, and then execute
-```shell
-$ source ~/.env/env.sh
-$ pkgs --update
-```
-
-After updating the software packages, use `scons -j10` or `scons -j10 --verbose` to compile this board support package. Alternatively, you can use the command `scons --exec-path="GCC_toolchain_path"` to specify the toolchain location for compilation. If the compilation is successful, an rtthread.elf file will be generated.
-
-After the compilation is completed, the script automatically calls the `./mksdimg.sh` script to package and generate the `boot.sd` file, which is the kernel file for SD card boot.
-
-## Running
-1. Divide the SD card into 2 partitions, with the first partition used to store bin files and the second partition used as a data storage partition. The partition format is FAT32.
-
-2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. For subsequent firmware updates, you only need to copy the `boot.sd` file.
-Where:
-- fip.bin: the bin file after fsbl、opensbi and U-Boot are packaged
-- boot.sd: the bin file after the kernel is packaged
-
-After updating `boot.sd`, power on again and you will see the serial output information:
-
-```shell
-U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x
-
-DRAM: 63.3 MiB
-gd->relocaddr=0x82435000. offset=0x2235000
-MMC: cv-sd@4310000: 0
-Loading Environment from ... OK
-In: serial
-Out: serial
-Err: serial
-Net:
-Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64
-eth0: ethernet@4070000
-Hit any key to stop autoboot: 0
-Boot from SD ...
-switch to partitions #0, OK
-mmc0 is current device
-132692 bytes read in 12 ms (10.5 MiB/s)
-## Loading kernel from FIT Image at 81400000 ...
- Using 'config-cv1800b_milkv_duo_sd' configuration
- Trying 'kernel-1' kernel subimage
- Verifying Hash Integrity ... crc32+ OK
-## Loading fdt from FIT Image at 81400000 ...
- Using 'config-cv1800b_milkv_duo_sd' configuration
- Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage
- Verifying Hash Integrity ... sha256+ OK
- Booting using the fdt blob at 0x8141b590
- Uncompressing Kernel Image
- Decompressing 296768 bytes used 42ms
- Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK
-
-Starting kernel ...
-
-heap: [0x802766b0 - 0x812766b0]
-
- \ | /
-- RT - Thread Smart Operating System
- / | \ 5.0.1 build Jun 28 2023 23:44:36
- 2006 - 2022 Copyright by RT-Thread team
-Hello RT-Smart!
-msh />
-```
-## Driver Support List
-
-| Driver | Support Status | Remarks |
-| :----- | :------------- | :--------------------- |
-| UART | Supported | Default baud rate 115200 |
-
-## Supported Development Boards
-- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
-
-## Contact information
-
-Maintenance person:[flyingcys](https://github.com/flyingcys)
diff --git a/bsp/cvitek/cv1800b/mksdimg.sh b/bsp/cvitek/cv1800b/mksdimg.sh
deleted file mode 100755
index 60dd65a076d..00000000000
--- a/bsp/cvitek/cv1800b/mksdimg.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#/bin/sh
-set -e
-echo "start compress kernel..."
-
-lzma -c -9 -f -k Image > Image.lzma
-
-./mkimage -f multi.its -r ../boot.sd
\ No newline at end of file
diff --git a/bsp/cvitek/cv18xx_aarch64/.config b/bsp/cvitek/cv18xx_aarch64/.config
new file mode 100644
index 00000000000..969cda0784b
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/.config
@@ -0,0 +1,1156 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=8192
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_MEMTRACE=y
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_DEVICE_OPS=y
+CONFIG_RT_USING_INTERRUPT_INFO=y
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+CONFIG_RT_USING_SCHED_THREAD_CTX=y
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50100
+CONFIG_RT_USING_STDC_ATOMIC=y
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+
+#
+# AArch64 Architecture Configuration
+#
+CONFIG_ARCH_TEXT_OFFSET=0x200000
+CONFIG_ARCH_RAM_OFFSET=0x80000000
+CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096
+CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+# CONFIG_RT_USING_HW_ATOMIC is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_ARCH_ARMV8=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=10
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=256
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FD_MAX=32
+# CONFIG_RT_USING_DFS_V1 is not set
+CONFIG_RT_USING_DFS_V2=y
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+# CONFIG_RT_DFS_ELM_USE_EXFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+CONFIG_RT_USING_DFS_ROMFS=y
+# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_DFS_MQUEUE is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=256
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+CONFIG_RT_USING_PM=y
+CONFIG_PM_TICKLESS_THRESHOLD_TIME=2
+# CONFIG_PM_USING_CUSTOM_CONFIG is not set
+# CONFIG_PM_ENABLE_DEBUG is not set
+# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set
+# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+CONFIG_RT_USING_DEV_BUS=y
+# CONFIG_RT_USING_WIFI is not set
+CONFIG_RT_USING_VIRTIO=y
+CONFIG_RT_USING_VIRTIO10=y
+CONFIG_RT_USING_VIRTIO_MMIO_ALIGN=y
+CONFIG_RT_USING_VIRTIO_BLK=y
+# CONFIG_RT_USING_VIRTIO_NET is not set
+CONFIG_RT_USING_VIRTIO_CONSOLE=y
+CONFIG_RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR=4
+CONFIG_RT_USING_VIRTIO_GPU=y
+CONFIG_RT_USING_VIRTIO_INPUT=y
+CONFIG_RT_USING_PIN=y
+CONFIG_RT_USING_KTIME=y
+# CONFIG_RT_USING_HWTIMER is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_EVENTFD is not set
+# CONFIG_RT_USING_POSIX_TIMERFD is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_RESOURCE_ID=y
+CONFIG_RT_USING_ADT=y
+CONFIG_RT_USING_ADT_AVL=y
+CONFIG_RT_USING_ADT_BITMAP=y
+CONFIG_RT_USING_ADT_HASHMAP=y
+CONFIG_RT_USING_ADT_REF=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_NCNN is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_CV18XX_AARCH64=y
+CONFIG_BOARD_TYPE_MILKV_DUO256M=y
+# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_SUPPORT_FPU=y
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GICV2=y
+# CONFIG_BSP_USING_GICV3 is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART0=y
+CONFIG_UART_IRQ_BASE=60
+# CONFIG_RT_USING_UART1 is not set
+# CONFIG_RT_USING_UART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+# CONFIG_RT_USING_UART4 is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_PWM is not set
diff --git a/bsp/cvitek/cv18xx_aarch64/Kconfig b/bsp/cvitek/cv18xx_aarch64/Kconfig
new file mode 100644
index 00000000000..ea607ee38a3
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/Kconfig
@@ -0,0 +1,46 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_CV18XX_AARCH64
+ bool
+ select ARCH_ARMV8
+ select ARCH_CPU_64BIT
+ select ARCH_ARM_MMU
+ select RT_USING_CACHE
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ select RT_USING_GIC
+ select BSP_USING_GIC
+ select ARCH_MM_MMU
+ default y
+
+choice
+ prompt "Board Type"
+ default BOARD_TYPE_MILKV_DUO256M
+
+ config BOARD_TYPE_MILKV_DUO256M
+ bool "milkv-duo256m"
+
+ config BOARD_TYPE_MILKV_DUO256M_SPINOR
+ bool "milkv-duo256m-spinor"
+
+endchoice
+
+source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/cvitek/cv18xx_aarch64/README.md b/bsp/cvitek/cv18xx_aarch64/README.md
new file mode 100644
index 00000000000..4d85cb2d791
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/README.md
@@ -0,0 +1,119 @@
+# Milkv-Duo256M 板级支持包说明
+
+## 1. 简介
+
+Milk-V Duo 256M 是 Duo 的升级版本,内存提升至 256M,满足需要更大内存容量的应用。采用 SG2002 计算系列芯片,计算能力提升至 1.0TOPS@INT8。它可以实现 RISC-V/ARM 架构之间的无缝切换,并支持双系统同时运行。此外,它还包含 SPI、UART 等一系列丰富的 GPIO 接口,适合边缘智能监控领域的各种硬件开发,包括 IP 摄像头、智能猫眼锁、可视门铃等。
+
+该板级支持包主要是针对**ARM架构的大核**实现的一份移植,支持RT-Thread标准版和Smart版内核。
+
+## 2. 编译说明
+
+推荐使用ubuntu20的[env环境](https://github.com/RT-Thread/env),当然也可以使用windows上的[env工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)进行编译。下面介绍**标准版**和**Smart版本**的编译流程。
+
+### 2.1 RT-Thread编译
+
+**1.menuconfig配置工程:**
+
+该BSP默认menuconfig支持的就是RT-Thread标准版,无需配置工程。
+
+**2.配置工具链相关环境:**
+
+依次执行下面命令进行环境变量的相关配置:
+
+```shell
+export RTT_CC=gcc
+export RTT_EXEC_PATH="/opt/tools/gnu_gcc/arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-elf/bin"
+export RTT_CC_PREFIX=aarch64-none-elf-
+export PATH=$PATH:$RTT_EXEC_PATH
+```
+
+**3.编译:**
+
+```shell
+scons -j12
+```
+
+### 2.2 RT-Smart编译
+
+**1.menuconfig配置工程:**
+
+```shell
+RT-Thread Kernel --->
+ [*] Enable RT-Thread Smart (microkernel on kernel/userland)
+```
+
+**2.配置工具链相关环境:**
+
+依次执行下面命令进行环境变量的相关配置:
+
+```shell
+export RTT_CC=gcc
+export RTT_EXEC_PATH="/opt/tools/gnu_gcc/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin"
+export RTT_CC_PREFIX=aarch64-linux-musleabi-
+export PATH=$PATH:$RTT_EXEC_PATH
+```
+
+**3.编译:**
+
+```shell
+scons -j12
+```
+
+如果编译正确无误,会产生 `rtthread.elf`, `rtthread.bin` 文件。
+
+## 3. 运行
+
+> 目前仅支持使用uboot对 `rtthread.bin` 文件进行加载,uboot对 `boot.sd` 的加载方式后续会实现。
+
+1. 将 SD 卡分为 2 个分区,第 1 个分区用于存放 bin 文件,第 2 个分区用于作为数据存储分区,分区格式为 `FAT32`。
+
+2. 将bsp的boot目录下的 `fip.bin` 和编译生成的 `rtthread.bin` 复制 SD 卡第一个分区中。后续更新固件只需要复制 `rtthread.bin` 文件即可。
+
+配置**串口0**参数: 115200 8N1 ,硬件和软件流控为关。
+
+进入uboot命令行后依次输入以下命令。
+
+```shell
+fatload mmc 0:1 0x80200000 rtthread.bin
+dcache flush
+go 0x80200000
+```
+
+> 0x80200000为rtthread.bin加载到内存的位置,可在menuconfig中自己修改,注意不能与小核固件加载位置重叠。
+
+完成后可以看到串口的输出信息:
+
+**标准版log信息:**
+
+```shell
+heap: [0x8028f2b0 - 0x84000000]
+
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.1.0 build Apr 16 2024 00:05:56
+ 2006 - 2024 Copyright by RT-Thread team
+hello rt-thread!
+msh />
+```
+
+**Smart版log信息:**
+
+```shell
+heap: [0x002f62c0 - 0x04000000]
+
+ \ | /
+- RT - Thread Smart Operating System
+ / | \ 5.1.0 build Apr 16 2024 00:04:47
+ 2006 - 2024 Copyright by RT-Thread team
+[E/lwp] lwp_startup: init program not found
+Switching to legacy mode...
+hello rt-thread!
+msh />
+```
+## 4. 注意事项
+
+目前RISC-V(Smart版本)支持外设物理地址映射到完全相同的虚拟地址,而ARM(Smart版本)目前是不支持这样搞的,所以在编写驱动的时候应该使用rt_ioremap这样的函数讲物理地址映射到可访问的虚拟地址上去。为了保证ARM的Smart版本内核能够成功运行,目前仅对uart和pinctrl的驱动进行了适配。其他驱动可能会因为未进行ioremap导致不可用。
+
+## 5. 联系人信息
+
+维护人:[liYony](https://github.com/liYony)
diff --git a/bsp/cvitek/cv1800b/SConscript b/bsp/cvitek/cv18xx_aarch64/SConscript
old mode 100755
new mode 100644
similarity index 100%
rename from bsp/cvitek/cv1800b/SConscript
rename to bsp/cvitek/cv18xx_aarch64/SConscript
diff --git a/bsp/cvitek/cv18xx_aarch64/SConstruct b/bsp/cvitek/cv18xx_aarch64/SConstruct
new file mode 100644
index 00000000000..1642f6ef13b
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/SConstruct
@@ -0,0 +1,53 @@
+import os
+import sys
+import rtconfig
+import re
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+TRACE_CONFIG = ""
+
+content = ""
+with open("rtconfig.h") as f:
+ for line in f.readlines():
+ if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1:
+ for token in line.split(" "):
+ if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0):
+ TRACE_CONFIG = " "
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG,
+ CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG,
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/drivers'):
+ drivers_path_prefix = SDK_ROOT + '/drivers'
+else:
+ drivers_path_prefix = os.path.dirname(SDK_ROOT) + '/drivers'
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# include libraries
+objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/cvitek/cv1800b/applications/SConscript b/bsp/cvitek/cv18xx_aarch64/applications/SConscript
old mode 100755
new mode 100644
similarity index 100%
rename from bsp/cvitek/cv1800b/applications/SConscript
rename to bsp/cvitek/cv18xx_aarch64/applications/SConscript
diff --git a/bsp/cvitek/cv18xx_aarch64/applications/main.c b/bsp/cvitek/cv18xx_aarch64/applications/main.c
new file mode 100644
index 00000000000..d7414cd58a4
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/applications/main.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020/10/7 bernard the first version
+ */
+
+#include
+
+int main(void)
+{
+ rt_kprintf("hello rt-thread!\n");
+
+ return 0;
+}
diff --git a/bsp/cvitek/cv18xx_aarch64/board/Kconfig b/bsp/cvitek/cv18xx_aarch64/board/Kconfig
new file mode 100755
index 00000000000..a7e559a1a40
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/board/Kconfig
@@ -0,0 +1,87 @@
+menu "General Drivers Configuration"
+ config BSP_SUPPORT_FPU
+ bool "Using Float"
+ default y
+
+ config BSP_USING_GIC
+ bool
+ default y
+
+ choice
+ prompt "GIC Version"
+ default BSP_USING_GICV2
+
+ config BSP_USING_GICV2
+ bool "GICv2"
+
+ config BSP_USING_GICV3
+ bool "GICv3"
+ endchoice
+
+ menuconfig BSP_USING_UART
+ bool "Using UART"
+ select RT_USING_SERIAL
+ default y
+
+ if BSP_USING_UART
+ config RT_USING_UART0
+ bool "Enable UART 0"
+ default y
+
+ config UART_IRQ_BASE
+ int
+ default 60
+
+ config RT_USING_UART1
+ bool "Enable UART 1"
+ default n
+
+ config RT_USING_UART2
+ bool "Enable UART 2"
+ default n
+
+ config RT_USING_UART3
+ bool "Enable UART 3"
+ default n
+
+ config RT_USING_UART4
+ bool "Enable UART 4"
+ default n
+
+ endif
+
+ config BSP_USING_ADC
+ bool "Using ADC"
+ select RT_USING_ADC
+ default n
+
+ config BSP_USING_SPI
+ bool "Using SPI"
+ select RT_USING_SPI
+ default n
+
+ menuconfig BSP_USING_PWM
+ bool "Using PWM"
+ select RT_USING_PWM
+ default n
+
+ if BSP_USING_PWM
+ config BSP_USING_PWM0
+ bool "Enable PWM 0"
+ default n
+
+ config BSP_USING_PWM1
+ bool "Enable PWM 1"
+ default n
+
+ config BSP_USING_PWM2
+ bool "Enable PWM 2"
+ default n
+
+ config BSP_USING_PWM3
+ bool "Enable PWM 3"
+ default n
+
+ endif
+
+endmenu
diff --git a/bsp/cvitek/cv1800b/board/SConscript b/bsp/cvitek/cv18xx_aarch64/board/SConscript
similarity index 100%
rename from bsp/cvitek/cv1800b/board/SConscript
rename to bsp/cvitek/cv18xx_aarch64/board/SConscript
diff --git a/bsp/cvitek/cv18xx_aarch64/board/board.c b/bsp/cvitek/cv18xx_aarch64/board/board.c
new file mode 100644
index 00000000000..ce4eb86dd38
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/board/board.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-15 liYony the first version
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+extern size_t MMUTable[];
+
+#ifdef RT_USING_SMART
+struct mem_desc platform_mem_desc[] = {
+ {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0FFFFFFF, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},
+};
+#else
+struct mem_desc platform_mem_desc[] =
+{
+ {0x80200000, 0x90200000 - 1, 0x80200000, NORMAL_MEM}, /* memory size 256M */
+ {0x01000000, 0x80000000 - 1, 0x01000000, DEVICE_MEM},
+};
+#endif
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
+
+void idle_wfi(void)
+{
+ asm volatile("wfi");
+}
+
+static rt_ubase_t pinmux_base = RT_NULL;
+
+void rt_hw_board_init(void)
+{
+#ifdef RT_USING_SMART
+ rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
+#else
+ rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xffffd0000000, 0x10000000, MMUTable, 0);
+#endif
+ rt_region_t init_page_region;
+ init_page_region.start = PAGE_START;
+ init_page_region.end = PAGE_END;
+ rt_page_init(init_page_region);
+
+ rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
+
+#ifdef RT_USING_HEAP
+ /* initialize system heap */
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+ /* initialize hardware interrupt */
+ rt_hw_interrupt_init();
+
+ /* initialize uart */
+ rt_hw_uart_init();
+
+ /* initialize timer for os tick */
+ rt_hw_gtimer_init();
+
+ rt_thread_idle_sethook(idle_wfi);
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+ /* set console device */
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+ rt_kprintf("heap: [0x%08x - 0x%08x]\n", HEAP_BEGIN, HEAP_END);
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+}
+
+rt_ubase_t pinmux_base_ioremap(void)
+{
+ if (pinmux_base == RT_NULL)
+ {
+ pinmux_base = (rt_size_t)rt_ioremap((void*)0x03001000, 0x1000);
+ }
+
+ return pinmux_base;
+}
diff --git a/bsp/cvitek/cv18xx_aarch64/board/board.h b/bsp/cvitek/cv18xx_aarch64/board/board.h
new file mode 100644
index 00000000000..c38920b19a0
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/board/board.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-15 liYony the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+
+extern unsigned char __bss_end;
+
+#define HEAP_BEGIN ((void*)&__bss_end)
+
+#ifdef RT_USING_SMART
+#define HEAP_END ((size_t)KERNEL_VADDR_START + 64 * 1024 * 1024)
+#define PAGE_START HEAP_END
+#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
+#else
+#define HEAP_END (ARCH_RAM_OFFSET + 64 * 1024 * 1024)
+#define PAGE_START HEAP_END
+#define PAGE_END ((size_t)PAGE_START + 64 * 1024 * 1024)
+#endif
+
+void rt_hw_board_init(void);
+
+int rt_hw_uart_init(void);
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/cvitek/cv18xx_aarch64/board/cv18xx.h b/bsp/cvitek/cv18xx_aarch64/board/cv18xx.h
new file mode 100644
index 00000000000..bf7b52631ec
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/board/cv18xx.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-15 liYony the first version
+ */
+
+#ifndef __CV18XX_H__
+#define __CV18XX_H__
+
+#include
+#include
+
+#ifdef RT_USING_SMART
+#include
+#endif
+
+#define __REG32(x) (*((volatile unsigned int *)(x)))
+#define __REG16(x) (*((volatile unsigned short *)(x)))
+
+/* GIC */
+#define MAX_HANDLERS 116
+#define GIC_IRQ_START 0
+#define ARM_GIC_NR_IRQS 116
+#define ARM_GIC_MAX_NR 1
+
+/* GICv2 */
+#define GIC400_DISTRIBUTOR_PPTR 0x01F01000U
+#define GIC400_CONTROLLER_PPTR 0x01F02000U
+#define GIC400_SIZE 0x00001000U
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_ubase_t platform_get_gic_dist_base(void)
+{
+ return GIC400_DISTRIBUTOR_PPTR;
+}
+
+rt_inline rt_ubase_t platform_get_gic_cpu_base(void)
+{
+ return GIC400_CONTROLLER_PPTR;
+}
+
+#endif /* __CV18XX_H__ */
diff --git a/bsp/cvitek/cv18xx_aarch64/boot/fip.bin b/bsp/cvitek/cv18xx_aarch64/boot/fip.bin
new file mode 100644
index 00000000000..c406223010f
Binary files /dev/null and b/bsp/cvitek/cv18xx_aarch64/boot/fip.bin differ
diff --git a/bsp/cvitek/cv18xx_aarch64/rtconfig.h b/bsp/cvitek/cv18xx_aarch64/rtconfig.h
new file mode 100644
index 00000000000..2d35ff261c7
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/rtconfig.h
@@ -0,0 +1,342 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 8192
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 8192
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_MEMHEAP_AS_HEAP
+#define RT_USING_MEMHEAP_AUTO_BINDING
+#define RT_USING_MEMTRACE
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
+#define RT_USING_INTERRUPT_INFO
+#define RT_USING_SCHED_THREAD_CTX
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50100
+#define RT_USING_STDC_ATOMIC
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+
+/* AArch64 Architecture Configuration */
+
+#define ARCH_TEXT_OFFSET 0x200000
+#define ARCH_RAM_OFFSET 0x80000000
+#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
+#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define RT_USING_CPU_FFS
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 10
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 256
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 32
+#define RT_USING_DFS_V2
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_ROMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 256
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_PM
+#define PM_TICKLESS_THRESHOLD_TIME 2
+#define RT_USING_DEV_BUS
+#define RT_USING_VIRTIO
+#define RT_USING_VIRTIO10
+#define RT_USING_VIRTIO_MMIO_ALIGN
+#define RT_USING_VIRTIO_BLK
+#define RT_USING_VIRTIO_CONSOLE
+#define RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR 4
+#define RT_USING_VIRTIO_GPU
+#define RT_USING_VIRTIO_INPUT
+#define RT_USING_PIN
+#define RT_USING_KTIME
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Memory protection */
+
+
+/* Utilities */
+
+#define RT_USING_RESOURCE_ID
+#define RT_USING_ADT
+#define RT_USING_ADT_AVL
+#define RT_USING_ADT_BITMAP
+#define RT_USING_ADT_HASHMAP
+#define RT_USING_ADT_REF
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+
+/* Kendryte SDK */
+
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_CV18XX_AARCH64
+#define BOARD_TYPE_MILKV_DUO256M
+
+/* General Drivers Configuration */
+
+#define BSP_SUPPORT_FPU
+#define BSP_USING_GIC
+#define BSP_USING_GICV2
+#define BSP_USING_UART
+#define RT_USING_UART0
+#define UART_IRQ_BASE 60
+
+#endif
diff --git a/bsp/cvitek/cv18xx_aarch64/rtconfig.py b/bsp/cvitek/cv18xx_aarch64/rtconfig.py
new file mode 100644
index 00000000000..c363513a185
--- /dev/null
+++ b/bsp/cvitek/cv18xx_aarch64/rtconfig.py
@@ -0,0 +1,47 @@
+import os
+
+# toolchains options
+ARCH ='aarch64'
+CPU ='cortex-a'
+CROSS_TOOL = 'gcc'
+PLATFORM = 'gcc'
+EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin'
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
+ CC = PREFIX + 'gcc'
+ CXX = PREFIX + 'g++'
+ CPP = PREFIX + 'cpp'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+ STRIP = PREFIX + 'strip'
+ CFPFLAGS = ' '
+ AFPFLAGS = ' '
+ DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
+
+ CPPFLAGS= ' -E -P -x assembler-with-cpp'
+ CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
+ CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always'
+ AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2'
+ CXXFLAGS += ' -O0 -gdwarf-2'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -Os'
+ CXXFLAGS += ' -Os'
+ CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/cvitek/cv1800b/.config b/bsp/cvitek/cv18xx_risc-v/.config
similarity index 96%
rename from bsp/cvitek/cv1800b/.config
rename to bsp/cvitek/cv18xx_risc-v/.config
index fd58346a239..c2da459eee4 100644
--- a/bsp/cvitek/cv1800b/.config
+++ b/bsp/cvitek/cv18xx_risc-v/.config
@@ -8,7 +8,7 @@
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-CONFIG_RT_USING_SMART=y
+# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_AMP is not set
# CONFIG_RT_USING_SMP is not set
@@ -25,10 +25,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_IDLE_THREAD_STACK_SIZE=8192
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
#
# kservice optimization
@@ -89,7 +89,6 @@ CONFIG_RT_USING_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_MM_MMU=y
-CONFIG_KERNEL_VADDR_START=0x80000000
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV64=y
@@ -98,7 +97,7 @@ CONFIG_ARCH_RISCV64=y
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=6144
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
@@ -125,6 +124,7 @@ CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_V1 is not set
CONFIG_RT_USING_DFS_V2=y
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
@@ -132,17 +132,6 @@ CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
-CONFIG_RT_USING_PAGECACHE=y
-
-#
-# page cache config
-#
-CONFIG_RT_PAGECACHE_COUNT=4096
-CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024
-CONFIG_RT_PAGECACHE_PRELOAD=4
-CONFIG_RT_PAGECACHE_HASH_NR=1024
-CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90
-CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70
# CONFIG_RT_USING_FAL is not set
#
@@ -152,15 +141,13 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
-CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
-CONFIG_RT_USING_TTY=y
-# CONFIG_RT_TTY_DEBUG is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
@@ -224,11 +211,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
CONFIG_RT_USING_POSIX_FS=y
CONFIG_RT_USING_POSIX_DEVIO=y
CONFIG_RT_USING_POSIX_STDIO=y
-# CONFIG_RT_USING_POSIX_POLL is not set
+CONFIG_RT_USING_POSIX_POLL=y
# CONFIG_RT_USING_POSIX_SELECT is not set
# CONFIG_RT_USING_POSIX_EVENTFD is not set
-# CONFIG_RT_USING_POSIX_EPOLL is not set
-# CONFIG_RT_USING_POSIX_SIGNALFD is not set
# CONFIG_RT_USING_POSIX_TIMERFD is not set
# CONFIG_RT_USING_POSIX_SOCKET is not set
CONFIG_RT_USING_POSIX_TERMIOS=y
@@ -281,23 +266,6 @@ CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
-CONFIG_RT_USING_LWP=y
-# CONFIG_LWP_DEBUG is not set
-CONFIG_RT_LWP_MAX_NR=30
-CONFIG_LWP_TASK_STACK_SIZE=16384
-CONFIG_RT_CH_MSG_MAX_NR=1024
-CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
-CONFIG_LWP_TID_MAX_NR=64
-CONFIG_RT_LWP_SHM_MAX_NR=64
-# CONFIG_LWP_UNIX98_PTY is not set
-CONFIG_RT_USING_LDSO=y
-# CONFIG_ELF_DEBUG_ENABLE is not set
-# CONFIG_ELF_LOAD_RANDOMIZE is not set
-
-#
-# Memory management
-#
-# CONFIG_RT_USING_MEMBLOCK is not set
#
# RT-Thread Utestcases
@@ -1129,9 +1097,14 @@ CONFIG_UART_IRQ_BASE=44
# CONFIG_RT_USING_UART3 is not set
# CONFIG_RT_USING_UART4 is not set
# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_PWM is not set
-CONFIG_BSP_USING_CV1800B=y
+CONFIG_BSP_USING_CV18XX=y
CONFIG_C906_PLIC_PHY_ADDR=0x70000000
CONFIG_IRQ_MAX_NR=64
CONFIG_TIMER_CLK_FREQ=25000000
-CONFIG___STACKSIZE__=4096
+CONFIG___STACKSIZE__=8192
+# CONFIG_BOARD_TYPE_MILKV_DUO is not set
+# CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set
+CONFIG_BOARD_TYPE_MILKV_DUO256M=y
+# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set
diff --git a/bsp/cvitek/cv18xx_risc-v/.gitignore b/bsp/cvitek/cv18xx_risc-v/.gitignore
new file mode 100755
index 00000000000..5a70c2b55ff
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/.gitignore
@@ -0,0 +1,2 @@
+dtb/
+Image
\ No newline at end of file
diff --git a/bsp/cvitek/cv1800b/Kconfig b/bsp/cvitek/cv18xx_risc-v/Kconfig
similarity index 67%
rename from bsp/cvitek/cv1800b/Kconfig
rename to bsp/cvitek/cv18xx_risc-v/Kconfig
index 18394dca61a..19774422733 100755
--- a/bsp/cvitek/cv1800b/Kconfig
+++ b/bsp/cvitek/cv18xx_risc-v/Kconfig
@@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"
-config BSP_USING_CV1800B
+config BSP_USING_CV18XX
bool
select ARCH_RISCV64
select RT_USING_SYSTEM_WORKQUEUE
@@ -45,3 +45,21 @@ config TIMER_CLK_FREQ
config __STACKSIZE__
int "stack size for interrupt"
default 4096
+
+choice
+ prompt "Board Type"
+ default BOARD_TYPE_MILKV_DUO256M
+
+ config BOARD_TYPE_MILKV_DUO
+ bool "milkv-duo"
+
+ config BOARD_TYPE_MILKV_DUO_SPINOR
+ bool "milkv-duo-spinor"
+
+ config BOARD_TYPE_MILKV_DUO256M
+ bool "milkv-duo256m"
+
+ config BOARD_TYPE_MILKV_DUO256M_SPINOR
+ bool "milkv-duo256m-spinor"
+
+endchoice
diff --git a/bsp/cvitek/cv1800b/README.md b/bsp/cvitek/cv18xx_risc-v/README.md
similarity index 57%
rename from bsp/cvitek/cv1800b/README.md
rename to bsp/cvitek/cv18xx_risc-v/README.md
index 9293cf2e29f..336b6439acf 100755
--- a/bsp/cvitek/cv1800b/README.md
+++ b/bsp/cvitek/cv18xx_risc-v/README.md
@@ -1,7 +1,7 @@
**中文** | [English](README_en.md)
## 概述
-CV180ZB/CV1800B/CV1801B 是面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片,集成了 H.264/H.265 视频压缩编码器和 ISP;支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法,为客户提供专业级的视频图像质量。
+CV18xx 系列芯片面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片,集成了 H.264/H.265 视频压缩编码器和 ISP;支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法,为客户提供专业级的视频图像质量。
1. 处理器内核
@@ -34,34 +34,62 @@ CV180ZB/CV1800B/CV1801B 是面向民用消费监控 IP 摄像机、居家智能
- 一个 USB Host / device 接口
## Toolchain 下载
-下载 `riscv64-unknown-linux-musl-gcc` 的工具链: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2)
+1. RT-Thread 标准版工具链:`riscv64-unknown-elf-gcc` 下载地址 [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz)
+
+2. RT-Smart 版工具链: `riscv64-unknown-linux-musl-gcc` 下载地址 [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2)
> 注:
-当前 bsp 只支持 Linux 编译
+当前 bsp 只支持 Linux 编译,推荐 ubuntu 22.04
-正确解压后,在`rtconfig.py`中将 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。
+正确解压后,在`rtconfig.py`中将 `riscv64-unknown-elf-gcc` 或 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。
```shell
+# RT-Thread 标准版按照以下配置:
+$ export RTT_CC_PREFIX=riscv64-unknown-elf-
+$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin
+
+# RT-Samrt 版按照以下配置:
+$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl-
$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin
```
## 编译
-1. 依赖安装
+### 依赖安装
```shell
-$ sudo apt install -y device-tree-compiler
+$ sudo apt install -y scons libncurses5-dev device-tree-compiler
```
-2. Linux平台下,可以先执行:
+
+## 修改当前工程配置
+
+Linux平台下,执行:
```shell
$ scons --menuconfig
```
+1. 默认编译为 RT-Thread 标准版,如果需要编译为 RT-Smart 版,请按照如下方式修改:
+```shell
+RT-Thread Kernel --->
+ [*] Enable RT-Thread Smart (microkernel on kernel/userland)
+
+ (0x80000000) The virtural address of kernel start
+```
+
+2. 选择当前需要编译的目标开发板类型:
+```shell
+Board Type (milkv-duo) --->
+ ( ) milkv-duo
+ ( ) milkv-duo-spinor
+ (X) milkv-duo256m
+ ( ) milkv-duo256m-spinor
+```
+
它会自动下载env相关脚本到~/.env目录,然后执行
```shell
$ source ~/.env/env.sh
$ pkgs --update
```
-更新完软件包后,执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令,在指定工具链位置的同时直接编译。编译正确无误,会产生rtthread.elf文件。
+更新完软件包后,执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包,编译正确无误,会产生 rtthread.elf 文件。
编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包,并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。
@@ -110,22 +138,9 @@ Starting kernel ...
heap: [0x802766b0 - 0x812766b0]
\ | /
-- RT - Thread Smart Operating System
- / | \ 5.0.1 build Jun 28 2023 23:44:36
- 2006 - 2022 Copyright by RT-Thread team
-Hello RT-Smart!
+- RT - Thread Operating System
+ / | \ 5.1.0 build Apr 7 2024 23:33:20
+ 2006 - 2024 Copyright by RT-Thread team
+Hello RISC-V!
msh />
```
-## 驱动支持列表
-
-| 驱动 | 支持情况 | 备注 |
-| :--- | :------- | :---------------- |
-| UART | 支持 | 默认波特率115200 |
-
-
-## 支持开发板
-- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
-
-## 联系人信息
-
-维护人:[flyingcys](https://github.com/flyingcys)
\ No newline at end of file
diff --git a/bsp/cvitek/cv18xx_risc-v/README_en.md b/bsp/cvitek/cv18xx_risc-v/README_en.md
new file mode 100755
index 00000000000..3b19462de00
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/README_en.md
@@ -0,0 +1,145 @@
+[中文](README.md) | **English**
+
+## Overview
+The CV18xx series of chips are high-performance, low-power chips launched for various products in the field of civilian consumer surveillance IP cameras, smart homes, and more. These chips integrate H.264/H.265 video compression encoders, as well as ISP; they support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing customers with professional-level video image quality.
+
+1. Processor Core
+- Main Processor: RISC-V C906 @ 1.0Ghz
+ - 32KB I-cache, 64KB D-Cache
+ - Integrated Vector and Floating-Point Unit (FPU).
+- Co-processor: RISC-V C906 @ 700Mhz
+ - Integrated Floating-Point Unit (FPU)
+
+2. Storage Interface
+- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, and a capacity of 512Mbit (64MB)
+- Support for SPI NOR flash interface (1.8V / 3.0V)
+ - Supports 1, 2, 4 line modes
+ - Maximum support of 256MByte
+- Support for SPI Nand flash interface (1.8V / 3.0V)
+ - Supports 1KB/2KB/4KB page (corresponding to maximum capacity of 16GB/32GB/64GB)
+ - Utilizes the device's built-in ECC module
+
+3. Peripherals
+- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART
+- Up to 3x I2C
+- Up to 5x UART
+- Up to 1x SDIO1
+- Up to 1x SPI
+- Up to 2x ADC
+- Up to 7x PWM
+- Up to 1x RUN
+- Up to 1x JTAG
+- Integrated MAC PHY supports 10/100Mbps full or half duplex mode
+- One USB host/device interface
+
+## Toolchain Download
+1. RT-Thread Standard Edition Toolchain: `riscv64-unknown-elf-gcc` Download Link [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz)
+
+2. RT-Smart Edition Toolchain: `riscv64-unknown-linux-musl-gcc` Download Link [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2)
+
+> Note:
+The current bsp only supports Linux compilation, and it is recommended to use Ubuntu 22.04
+
+After correctly extracting, add the local path of the `riscv64-unknown-elf-gcc` or `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py` or specify the path through the `RTT_EXEC_PATH` environment variable.
+
+```shell
+# For RT-Thread Standard Edition, use the following configuration:
+$ export RTT_CC_PREFIX=riscv64-unknown-elf-
+$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin
+
+# For RT-Smart Edition, use the following configuration:
+$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl-
+$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin
+```
+
+## Compilation
+
+### Dependency Installation
+```shell
+$ sudo apt install -y scons libncurses5-dev device-tree-compiler
+```
+
+## Modify Current Project Configuration
+
+For the Linux platform, execute:
+```shell
+$ scons --menuconfig
+```
+
+1. By default, compile as RT-Thread Standard Edition. If you need to compile as RT-Smart Edition, modify as follows:
+```shell
+RT-Thread Kernel --->
+ [*] Enable RT-Thread Smart (microkernel on kernel/userland)
+
+ (0x80000000) The virtual address of kernel start
+```
+
+2. Select the current target development board type:
+```shell
+Board Type (milkv-duo) --->
+ ( ) milkv-duo
+ ( ) milkv-duo-spinor
+ (X) milkv-duo256m
+ ( ) milkv-duo256m-spinor
+```
+
+It will automatically download relevant scripts to the ~/.env directory, then execute:
+```shell
+$ source ~/.env/env.sh
+$ pkgs --update
+```
+After updating the software package, execute `scons -j10` or `scons -j10 --verbose` to compile this board support package. If the compilation is successful, an rtthread.elf file will be generated.
+
+After the compilation is complete, the script automatically calls the `./mksdimg.sh` script to package and generate `boot.sd`, which is the kernel file for SD card startup.
+
+## Running
+1. Divide the SD card into 2 partitions, with the first partition used to store bin files, and the second partition used as a data storage partition, with `FAT32` format.
+2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. Subsequent firmware updates only require copying the `boot.sd` file.
+Where:
+- fip.bin: fsbl, opensbi, and uboot packaged bin file
+- boot.sd: kernel packaged bin file
+
+After updating `boot.sd`, restart to see the serial port output:
+
+```shell
+U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x
+
+DRAM: 63.3 MiB
+gd->relocaddr=0x82435000. offset=0x2235000
+MMC: cv-sd@4310000: 0
+Loading Environment from ... OK
+In: serial
+Out: serial
+Err: serial
+Net:
+Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64
+eth0: ethernet@4070000
+Hit any key to stop autoboot: 0
+Boot from SD ...
+switch to partitions #0, OK
+mmc0 is current device
+132692 bytes read in 12 ms (10.5 MiB/s)
+## Loading kernel from FIT Image at 81400000 ...
+ Using 'config-cv1800b_milkv_duo_sd' configuration
+ Trying 'kernel-1' kernel subimage
+ Verifying Hash Integrity ... crc32+ OK
+## Loading fdt from FIT Image at 81400000 ...
+ Using 'config-cv1800b_milkv_duo_sd' configuration
+ Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage
+ Verifying Hash Integrity ... sha256+ OK
+ Booting using the fdt blob at 0x8141b590
+ Uncompressing Kernel Image
+ Decompressing 296768 bytes used 42ms
+ Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK
+
+Starting kernel ...
+
+heap: [0x802766b0 - 0x812766b0]
+
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.1.0 build Apr 7 2024 23:33:20
+ 2006 - 2024 Copyright by RT-Thread team
+Hello RISC-V!
+msh />
+```
\ No newline at end of file
diff --git a/bsp/cvitek/cv18xx_risc-v/SConscript b/bsp/cvitek/cv18xx_risc-v/SConscript
new file mode 100755
index 00000000000..c7ef7659ece
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/cvitek/cv1800b/SConstruct b/bsp/cvitek/cv18xx_risc-v/SConstruct
similarity index 100%
rename from bsp/cvitek/cv1800b/SConstruct
rename to bsp/cvitek/cv18xx_risc-v/SConstruct
diff --git a/bsp/cvitek/cv18xx_risc-v/applications/SConscript b/bsp/cvitek/cv18xx_risc-v/applications/SConscript
new file mode 100755
index 00000000000..c583d3016e0
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/cvitek/cv1800b/applications/main.c b/bsp/cvitek/cv18xx_risc-v/applications/main.c
similarity index 81%
rename from bsp/cvitek/cv1800b/applications/main.c
rename to bsp/cvitek/cv18xx_risc-v/applications/main.c
index a8afc8b0f92..16417b5d08c 100755
--- a/bsp/cvitek/cv1800b/applications/main.c
+++ b/bsp/cvitek/cv18xx_risc-v/applications/main.c
@@ -13,7 +13,10 @@
int main(void)
{
+#ifdef RT_USING_SMART
rt_kprintf("Hello RT-Smart!\n");
-
+#else
+ rt_kprintf("Hello RISC-V!\n");
+#endif
return 0;
}
diff --git a/bsp/cvitek/cv1800b/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig
similarity index 93%
rename from bsp/cvitek/cv1800b/board/Kconfig
rename to bsp/cvitek/cv18xx_risc-v/board/Kconfig
index 82f7886f098..a743c804dea 100755
--- a/bsp/cvitek/cv1800b/board/Kconfig
+++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig
@@ -37,6 +37,11 @@ menu "General Drivers Configuration"
select RT_USING_ADC
default n
+ config BSP_USING_SPI
+ bool "Using SPI"
+ select RT_USING_SPI
+ default n
+
menuconfig BSP_USING_PWM
bool "Using PWM"
select RT_USING_PWM
diff --git a/bsp/cvitek/cv18xx_risc-v/board/SConscript b/bsp/cvitek/cv18xx_risc-v/board/SConscript
new file mode 100755
index 00000000000..4488cae0736
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Driver', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/cvitek/cv1800b/board/board.c b/bsp/cvitek/cv18xx_risc-v/board/board.c
similarity index 100%
rename from bsp/cvitek/cv1800b/board/board.c
rename to bsp/cvitek/cv18xx_risc-v/board/board.c
diff --git a/bsp/cvitek/cv1800b/board/board.h b/bsp/cvitek/cv18xx_risc-v/board/board.h
similarity index 100%
rename from bsp/cvitek/cv1800b/board/board.h
rename to bsp/cvitek/cv18xx_risc-v/board/board.h
diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/cv1800b_milkv_duo_spinor.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/cv1800b_milkv_duo_spinor.dtb
new file mode 100755
index 00000000000..5275da07d2f
Binary files /dev/null and b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/cv1800b_milkv_duo_spinor.dtb differ
diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/multi.its
new file mode 100755
index 00000000000..5dfcc9d0aaf
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/multi.its
@@ -0,0 +1,56 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <2>;
+
+ images {
+ kernel-1 {
+ description = "cvitek kernel";
+ data = /incbin/("./Image.lzma");
+ type = "kernel";
+ arch = "riscv";
+ os = "linux";
+ compression = "lzma";
+ load = <0x0 0x80200000>;
+ entry = <0x0 0x80200000>;
+ hash-2 {
+ algo = "crc32";
+ };
+ };
+
+
+ /*FDT*/
+
+ fdt-cv1800b_milkv_duo_spinor {
+ description = "cvitek device tree - cv1800b_milkv_duo_spinor";
+ data = /incbin/("./cv1800b_milkv_duo_spinor.dtb");
+ type = "flat_dt";
+ arch = "riscv";
+ compression = "none";
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+
+
+
+ };
+
+ /*CFG*/
+ configurations {
+
+ config-cv1800b_milkv_duo_spinor {
+ description = "boot cvitek system with board cv1800b_milkv_duo_spinor";
+ kernel = "kernel-1";
+ fdt = "fdt-cv1800b_milkv_duo_spinor";
+ };
+
+ };
+
+
+};
diff --git a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/cv1800b_milkv_duo_sd.dtb
similarity index 100%
rename from bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb
rename to bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/cv1800b_milkv_duo_sd.dtb
diff --git a/bsp/cvitek/cv1800b/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/multi.its
similarity index 100%
rename from bsp/cvitek/cv1800b/multi.its
rename to bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/multi.its
diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/cv1812cp_milkv_duo256m_spinor.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/cv1812cp_milkv_duo256m_spinor.dtb
new file mode 100755
index 00000000000..e48fe8e3115
Binary files /dev/null and b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/cv1812cp_milkv_duo256m_spinor.dtb differ
diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/multi.its
new file mode 100755
index 00000000000..23f546482cd
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/multi.its
@@ -0,0 +1,56 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <2>;
+
+ images {
+ kernel-1 {
+ description = "cvitek kernel";
+ data = /incbin/("./Image.lzma");
+ type = "kernel";
+ arch = "riscv";
+ os = "linux";
+ compression = "lzma";
+ load = <0x0 0x80200000>;
+ entry = <0x0 0x80200000>;
+ hash-2 {
+ algo = "crc32";
+ };
+ };
+
+
+ /*FDT*/
+
+ fdt-cv1812cp_milkv_duo256m_spinor {
+ description = "cvitek device tree - cv1812cp_milkv_duo256m_spinor";
+ data = /incbin/("./cv1812cp_milkv_duo256m_spinor.dtb");
+ type = "flat_dt";
+ arch = "riscv";
+ compression = "none";
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+
+
+
+ };
+
+ /*CFG*/
+ configurations {
+
+ config-cv1812cp_milkv_duo256m_spinor {
+ description = "boot cvitek system with board cv1812cp_milkv_duo256m_spinor";
+ kernel = "kernel-1";
+ fdt = "fdt-cv1812cp_milkv_duo256m_spinor";
+ };
+
+ };
+
+
+};
diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/cv1812cp_milkv_duo256m_sd.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/cv1812cp_milkv_duo256m_sd.dtb
new file mode 100755
index 00000000000..01af66027b5
Binary files /dev/null and b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/cv1812cp_milkv_duo256m_sd.dtb differ
diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/multi.its
new file mode 100755
index 00000000000..5e01397d554
--- /dev/null
+++ b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/multi.its
@@ -0,0 +1,56 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <2>;
+
+ images {
+ kernel-1 {
+ description = "cvitek kernel";
+ data = /incbin/("./Image.lzma");
+ type = "kernel";
+ arch = "riscv";
+ os = "linux";
+ compression = "lzma";
+ load = <0x0 0x80200000>;
+ entry = <0x0 0x80200000>;
+ hash-2 {
+ algo = "crc32";
+ };
+ };
+
+
+ /*FDT*/
+
+ fdt-cv1812cp_milkv_duo256m_sd {
+ description = "cvitek device tree - cv1812cp_milkv_duo256m_sd";
+ data = /incbin/("./cv1812cp_milkv_duo256m_sd.dtb");
+ type = "flat_dt";
+ arch = "riscv";
+ compression = "none";
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+
+
+
+ };
+
+ /*CFG*/
+ configurations {
+
+ config-cv1812cp_milkv_duo256m_sd {
+ description = "boot cvitek system with board cv1812cp_milkv_duo256m_sd";
+ kernel = "kernel-1";
+ fdt = "fdt-cv1812cp_milkv_duo256m_sd";
+ };
+
+ };
+
+
+};
diff --git a/bsp/cvitek/cv1800b/link.lds b/bsp/cvitek/cv18xx_risc-v/link.lds
similarity index 100%
rename from bsp/cvitek/cv1800b/link.lds
rename to bsp/cvitek/cv18xx_risc-v/link.lds
diff --git a/bsp/cvitek/cv1800b/link_stacksize.lds b/bsp/cvitek/cv18xx_risc-v/link_stacksize.lds
similarity index 100%
rename from bsp/cvitek/cv1800b/link_stacksize.lds
rename to bsp/cvitek/cv18xx_risc-v/link_stacksize.lds
diff --git a/bsp/cvitek/cv1800b/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h
similarity index 85%
rename from bsp/cvitek/cv1800b/rtconfig.h
rename to bsp/cvitek/cv18xx_risc-v/rtconfig.h
index 236544eee34..7fb6e27f8a5 100755
--- a/bsp/cvitek/cv1800b/rtconfig.h
+++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h
@@ -7,7 +7,6 @@
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
-#define RT_USING_SMART
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
@@ -18,10 +17,10 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 1024
+#define IDLE_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
@@ -57,7 +56,6 @@
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define ARCH_MM_MMU
-#define KERNEL_VADDR_START 0x80000000
#define ARCH_RISCV
#define ARCH_RISCV64
@@ -65,7 +63,7 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 6144
+#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
@@ -90,29 +88,18 @@
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_DEVFS
-#define RT_USING_PAGECACHE
-
-/* page cache config */
-
-#define RT_PAGECACHE_COUNT 4096
-#define RT_PAGECACHE_ASPACE_COUNT 1024
-#define RT_PAGECACHE_PRELOAD 4
-#define RT_PAGECACHE_HASH_NR 1024
-#define RT_PAGECACHE_GC_WORK_LEVEL 90
-#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
@@ -139,6 +126,7 @@
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
@@ -164,17 +152,6 @@
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
-#define RT_USING_LWP
-#define RT_LWP_MAX_NR 30
-#define LWP_TASK_STACK_SIZE 16384
-#define RT_CH_MSG_MAX_NR 1024
-#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
-#define LWP_TID_MAX_NR 64
-#define RT_LWP_SHM_MAX_NR 64
-#define RT_USING_LDSO
-
-/* Memory management */
-
/* RT-Thread Utestcases */
@@ -311,10 +288,11 @@
#define BSP_USING_UART
#define RT_USING_UART0
#define UART_IRQ_BASE 44
-#define BSP_USING_CV1800B
+#define BSP_USING_CV18XX
#define C906_PLIC_PHY_ADDR 0x70000000
#define IRQ_MAX_NR 64
#define TIMER_CLK_FREQ 25000000
-#define __STACKSIZE__ 4096
+#define __STACKSIZE__ 8192
+#define BOARD_TYPE_MILKV_DUO256M
#endif
diff --git a/bsp/cvitek/cv1800b/rtconfig.py b/bsp/cvitek/cv18xx_risc-v/rtconfig.py
similarity index 83%
rename from bsp/cvitek/cv1800b/rtconfig.py
rename to bsp/cvitek/cv18xx_risc-v/rtconfig.py
index 0914d5c010f..91667d1bf0e 100755
--- a/bsp/cvitek/cv1800b/rtconfig.py
+++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.py
@@ -16,7 +16,7 @@
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
- EXEC_PATH = r'/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin'
+ EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
@@ -25,11 +25,12 @@
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
+CHIP_TYPE = 'cv180x'
if PLATFORM == 'gcc':
# toolchains
#PREFIX = 'riscv64-unknown-elf-'
- PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-'
+ PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@@ -56,4 +57,5 @@
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET Image \n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'cd .. && bash mksdimg.sh ' + os.getcwd() + ' Image \n'
diff --git a/bsp/cvitek/drivers/.ignore_format.yml b/bsp/cvitek/drivers/.ignore_format.yml
new file mode 100755
index 00000000000..821281b7e92
--- /dev/null
+++ b/bsp/cvitek/drivers/.ignore_format.yml
@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries
\ No newline at end of file
diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript
index 83c882470cc..35979fed548 100755
--- a/bsp/cvitek/drivers/SConscript
+++ b/bsp/cvitek/drivers/SConscript
@@ -2,17 +2,23 @@ from building import *
cwd = GetCurrentDir()
src = Split('''
-drv_uart.c
-drv_por.c
+ drv_uart.c
+ drv_por.c
''')
CPPDEFINES = []
CPPPATH = [cwd]
-if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'):
- CPPPATH += [cwd + r'/cv1800b']
+CHIP_TYPE = 'cv180x'
+if GetDepend('BOARD_TYPE_MILKV_DUO256M') or GetDepend('BOARD_TYPE_MILKV_DUO256M_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO256M_SPINAND'):
+ CHIP_TYPE = 'cv181x'
+elif GetDepend('BOARD_TYPE_MILKV_DUO') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINAND'):
+ CHIP_TYPE = 'cv180x'
-if GetDepend('BSP_USING_CV1800B'):
+CPPPATH += [cwd + r'/libraries']
+CPPPATH += [cwd + r'/libraries/' + CHIP_TYPE]
+
+if GetDepend('BSP_USING_CV18XX'):
src += ['drv_gpio.c']
if GetDepend('BSP_USING_I2C'):
@@ -24,9 +30,13 @@ if GetDepend('BSP_USING_ADC'):
if GetDepend('BSP_USING_WDT'):
src += ['drv_wdt.c']
+if GetDepend(['BSP_USING_SPI']):
+ src += ['drv_spi.c']
+
if GetDepend('BSP_USING_PWM'):
src += ['drv_pwm.c']
- CPPPATH += [cwd + r'/cv1800b/pwm']
+ CPPPATH += [cwd + r'/libraries/cv180x/pwm']
+
CPPDEFINES += ['-DCONFIG_64BIT']
if GetDepend('BSP_USING_RTC'):
diff --git a/bsp/cvitek/drivers/drv_gpio.c b/bsp/cvitek/drivers/drv_gpio.c
index 4a1ae809c77..f6e6752e98d 100755
--- a/bsp/cvitek/drivers/drv_gpio.c
+++ b/bsp/cvitek/drivers/drv_gpio.c
@@ -126,7 +126,7 @@ static void dwapb_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t
dwapb_write32(base_addr + GPIO_SWPORTA_DR, reg_val);
}
-static rt_int8_t dwapb_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t dwapb_pin_read(struct rt_device *device, rt_base_t pin)
{
rt_uint8_t bit, port;
rt_ubase_t base_addr;
diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c
new file mode 100644
index 00000000000..aa6b3dd0b9f
--- /dev/null
+++ b/bsp/cvitek/drivers/drv_spi.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-03-28 qiujingbao first version
+ */
+
+#include "drv_spi.h"
+#ifdef RT_USING_SPI
+
+#define DBG_TAG "drv.spi"
+#define DBG_LVL DBG_INFO
+#include
+
+static struct cv1800_spi cv1800_spi_obj[] =
+{
+#ifdef BSP_USING_SPI
+ {
+ .spi_id = SPI2,
+ .device_name = "spi2",
+ .fifo_len = SPI_TXFTLR,
+ },
+#endif
+};
+
+static struct spi_regs *get_spi_base(uint8_t spi_id)
+{
+ struct spi_regs *spi_base = NULL;
+
+ switch (spi_id)
+ {
+ case SPI0:
+ spi_base = (struct spi_regs *)SPI0_BASE;
+ break;
+ case SPI1:
+ spi_base = (struct spi_regs *)SPI1_BASE;
+ break;
+ case SPI2:
+ spi_base = (struct spi_regs *)SPI2_BASE;
+ break;
+ case SPI3:
+ spi_base = (struct spi_regs *)SPI3_BASE;
+ break;
+ }
+
+ return spi_base;
+}
+
+static rt_err_t drv_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
+{
+ rt_err_t ret = RT_EOK;
+ struct cv1800_spi *spi_dev = RT_NULL;
+ uint32_t mode;
+
+ spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data);
+
+ spi_dev->data_width = configuration->data_width;
+
+ /* disable spi */
+ spi_enable(spi_dev->reg, 0);
+
+ /* clear irq */
+ spi_clear_irq(spi_dev->reg, SPI_IRQ_MSAK);
+
+ /* set clk */
+ ret = spi_set_frequency(spi_dev->reg, configuration->max_hz);
+ if (ret)
+ return ret;
+
+ /* set mode */
+ ret = gen_spi_mode(configuration, &mode);
+ if (ret)
+ return ret;
+
+ spi_set_mode(spi_dev->reg, mode);
+
+ /* set cs */
+ spi_enable_cs(spi_dev->reg, 0x1);
+
+ spi_enable(spi_dev->reg, 0x1);
+
+ mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_ctrl0);
+ LOG_D("mode: %x", mode);
+ mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_baudr);
+ LOG_D("spi_baudr: %x", mode);
+
+ return ret;
+}
+
+int hw_spi_recv(struct cv1800_spi *dev) {
+ uint32_t rever;
+ uint32_t tem;
+ int ret;
+
+ rever = mmio_read_32((uintptr_t)&dev->reg->spi_rxflr);
+ ret = (int)rever;
+
+ while (rever)
+ {
+ tem = mmio_read_32((uintptr_t)&dev->reg->spi_dr);
+
+ if (dev->recv_buf < dev->recv_end)
+ {
+ if (dev->data_width == 8)
+ *(uint8_t *)(dev->recv_buf) = tem;
+ else
+ *(uint16_t *)(dev->recv_buf) = tem;
+ }
+ else
+ {
+ return 0;
+ }
+
+ rever--;
+ dev->recv_buf += dev->data_width >> 3;
+ }
+ return ret;
+}
+
+int hw_spi_send(struct cv1800_spi *dev) {
+ uint32_t txflr;
+ uint32_t max;
+ uint16_t value;
+
+ txflr = mmio_read_32((uintptr_t)&dev->reg->spi_txflr);
+ max = dev->fifo_len - txflr;
+
+ while (max)
+ {
+ if (dev->send_end - dev->send_buf)
+ {
+ if (dev->data_width == 8)
+ value = *(uint8_t *)(dev->send_buf);
+ else
+ value = *(uint16_t *)(dev->send_buf);
+ }
+ else
+ {
+ return 0;
+ }
+
+ mmio_write_32((uintptr_t)&dev->reg->spi_dr, value);
+ dev->send_buf += dev->data_width >> 3;
+ max--;
+ }
+
+ return 0;
+}
+static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) {
+ int ret = 0;
+ struct cv1800_spi *spi_dev;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(device->bus != RT_NULL);
+ RT_ASSERT(message != RT_NULL);
+
+ spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data);
+
+ if (message->send_buf != RT_NULL)
+ {
+ spi_dev->send_buf = message->send_buf;
+ spi_dev->send_end = (void *)((uint8_t *)spi_dev->send_buf + message->length);
+ }
+
+ if (message->recv_buf != RT_NULL)
+ {
+ spi_dev->recv_buf = message->recv_buf;
+ spi_dev->recv_end = (void *)((uint8_t *)spi_dev->recv_buf + message->length);
+ }
+
+ /* if user use their cs */
+ if (message->cs_take && device->cs_pin != PIN_NONE)
+ rt_pin_write(device->cs_pin, PIN_LOW);
+
+ if (message->send_buf)
+ {
+ while (spi_dev->send_buf != spi_dev->send_end)
+ {
+ hw_spi_send(spi_dev);
+ }
+
+ /* wait for complete */
+ while (mmio_read_32((uintptr_t)&spi_dev->reg->spi_txflr)) {}
+
+ ret = message->length;
+ }
+
+ if (message->recv_buf)
+ {
+ while (spi_dev->recv_buf != spi_dev->recv_end)
+ {
+ hw_spi_recv(spi_dev);
+ }
+
+ ret = message->length;
+ }
+
+ if (message->cs_release && device->cs_pin != PIN_NONE)
+ rt_pin_write(device->cs_pin, PIN_HIGH);
+
+ return ret;
+}
+
+const static struct rt_spi_ops drv_spi_ops =
+{
+ drv_spi_configure,
+ spixfer,
+};
+
+int rt_hw_spi_init(void)
+{
+ rt_err_t ret = RT_EOK;
+ struct spi_regs *reg = NULL;
+
+ for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) {
+ /* set reg base addr */
+ reg = get_spi_base(cv1800_spi_obj[i].spi_id);
+ if (!reg)
+ return -RT_ERROR;
+
+ cv1800_spi_obj[i].reg = reg;
+ cv1800_spi_obj[i].spi_bus.parent.user_data = &cv1800_spi_obj[i];
+
+ /* register spix bus */
+ ret = rt_spi_bus_register(&cv1800_spi_obj[i].spi_bus, cv1800_spi_obj[i].device_name, &drv_spi_ops);
+ }
+
+ return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif /* RT_USING_SPI */
diff --git a/bsp/cvitek/drivers/drv_spi.h b/bsp/cvitek/drivers/drv_spi.h
new file mode 100644
index 00000000000..2e20b15b2eb
--- /dev/null
+++ b/bsp/cvitek/drivers/drv_spi.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-03-28 qiujingbao first version
+ */
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include "rtdevice.h"
+#include
+#include
+
+#include "mmio.h"
+#include "pinctrl.h"
+
+#define SPI0 0x0
+#define SPI1 0x1
+#define SPI2 0x2
+#define SPI3 0x3
+
+#define SPI0_BASE 0x04180000
+#define SPI1_BASE 0x04190000
+#define SPI2_BASE 0x041A0000
+#define SPI3_BASE 0x041B0000
+
+#define SPI_IRQ_MSAK 0x3e
+#define SPI_FREQUENCY 187500000
+
+/* Transmit FiFO Threshold Level */
+#define SPI_TXFTLR 0xf
+
+#define SPI_CTRL0_DATA_FREAM_SHIFT 0
+#define SPI_CTRL0_FREAM_FORMAT_SHIFT 4
+#define SPI_CTRL0_CPHA_SHIFT 6
+#define SPI_CTRL0_CPOL_SHIFT 7
+#define SPI_CTRL0_TRANS_MODE 8
+#define SPI_CTRL0_LOOP_SHIFT 11
+#define SPI_CTRL0_CTRL_FREAM_SHIFT 12
+
+struct cv1800_spi {
+ uint8_t spi_id;
+ char *device_name;
+
+ uint8_t fifo_len;
+ uint8_t data_width;
+
+ const void *send_buf;
+ void *recv_buf;
+
+ const void *send_end;
+ void *recv_end;
+
+ struct rt_spi_bus spi_bus;
+ struct spi_regs *reg;
+};
+
+struct spi_regs {
+ uint32_t spi_ctrl0; // 0x00
+ uint32_t spi_ctrl1; // 0x04
+ uint32_t spi_ssienr; // 0x08
+ uint32_t spi_mwcr; // 0x0c
+ uint32_t spi_ser; // 0x10
+ uint32_t spi_baudr; // 0x14
+ uint32_t spi_txftlr; // 0x18
+ uint32_t spi_rxftlr; // 0x1c
+ uint32_t spi_txflr; // 0x20
+ uint32_t spi_rxflr; // 0x24
+ uint32_t spi_sr; // 0x28
+ uint32_t spi_imr; // 0x2c
+ uint32_t spi_isr; // 0x30
+ uint32_t spi_risr; // 0x34
+ uint32_t spi_txoicr; // 0x38
+ uint32_t spi_rxoicr; // 0x3c
+ uint32_t spi_rxuicr; // 0x40
+ uint32_t spi_msticr; // 0x44
+ uint32_t spi_icr; // 0x48
+ uint32_t spi_dmacr; // 0x4c
+ uint32_t spi_dmatdlr; // 0x50
+ uint32_t spi_dmardlr; // 0x54
+ uint32_t spi_idr; // 0x58
+ uint32_t spi_version; // 0x5c
+ uint32_t spi_dr; // 0x60
+ uint32_t spi_rx_sample_dly; // 0xf0
+ uint32_t spi_cs_override; // 0xf4
+};
+
+uint32_t gen_spi_mode(struct rt_spi_configuration *cfg, uint32_t *mode)
+{
+ uint32_t value = 0;
+
+ if (cfg->data_width != 8 && cfg->data_width != 16)
+ return -1;
+
+ value |= (cfg->data_width - 1) >> SPI_CTRL0_DATA_FREAM_SHIFT;
+ value |= cfg->mode >> SPI_CTRL0_CPHA_SHIFT;
+
+ *mode = value;
+ return 0;
+}
+
+/* set spi mode */
+static inline void spi_set_mode(struct spi_regs *reg, uint32_t mode)
+{
+ mmio_write_32((uintptr_t)®->spi_ctrl0, mode);
+}
+
+/* clear irq */
+static inline void spi_clear_irq(struct spi_regs *reg, uint32_t mode)
+{
+ mmio_write_32((uintptr_t)®->spi_imr, mode);
+}
+
+static inline void spi_enable_cs(struct spi_regs *reg, uint32_t enable)
+{
+ if (enable)
+ enable = 0x1;
+ else
+ enable = 0x0;
+
+ mmio_write_32((uintptr_t)®->spi_ser, enable);
+}
+
+/* set spi frequency*/
+static inline rt_err_t spi_set_frequency(struct spi_regs *reg, uint32_t speed)
+{
+ uint16_t value;
+
+ /* The value of the BAUDR register must be an even number between 2-65534 */
+ value = SPI_FREQUENCY / speed;
+ if (value % 2 != 0)
+ value++;
+
+ if (value < 4 || value > 65534)
+ value = 4;
+
+ mmio_write_32((uintptr_t)®->spi_baudr, value);
+
+ return RT_EOK;
+}
+
+static inline void spi_enable(struct spi_regs *reg, uint32_t enable)
+{
+ if (enable)
+ enable = 0x1;
+ else
+ enable = 0x0;
+
+ mmio_write_32((uintptr_t)®->spi_ssienr, enable);
+}
+
+#endif /* __DRV_SPI_H__ */
diff --git a/bsp/cvitek/drivers/drv_uart.c b/bsp/cvitek/drivers/drv_uart.c
index b629cd5a0d0..845e6708f68 100644
--- a/bsp/cvitek/drivers/drv_uart.c
+++ b/bsp/cvitek/drivers/drv_uart.c
@@ -252,30 +252,45 @@ int rt_hw_uart_init(void)
PINMUX_CONFIG(UART0_RX, UART0_RX);
PINMUX_CONFIG(UART0_TX, UART0_TX);
BSP_INSTALL_UART_DEVICE(0);
+#if defined(ARCH_ARM) && defined(RT_USING_SMART)
+ uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000);
+#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */
#endif
#ifdef RT_USING_UART1
PINMUX_CONFIG(IIC0_SDA, UART1_RX);
PINMUX_CONFIG(IIC0_SCL, UART1_TX);
BSP_INSTALL_UART_DEVICE(1);
+#if defined(ARCH_ARM) && defined(RT_USING_SMART)
+ uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000);
+#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */
#endif
#ifdef RT_USING_UART2
PINMUX_CONFIG(SD1_D1, UART2_RX);
PINMUX_CONFIG(SD1_D2, UART2_TX);
BSP_INSTALL_UART_DEVICE(2);
+#if defined(ARCH_ARM) && defined(RT_USING_SMART)
+ uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000);
+#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */
#endif
#ifdef RT_USING_UART3
PINMUX_CONFIG(SD1_D1, UART3_RX);
PINMUX_CONFIG(SD1_D2, UART3_TX);
BSP_INSTALL_UART_DEVICE(3);
+#if defined(ARCH_ARM) && defined(RT_USING_SMART)
+ uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000);
+#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */
#endif
#ifdef RT_USING_UART4
PINMUX_CONFIG(SD1_GP0, UART4_RX);
PINMUX_CONFIG(SD1_GP1, UART4_TX);
BSP_INSTALL_UART_DEVICE(4);
+#if defined(ARCH_ARM) && defined(RT_USING_SMART)
+ uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000);
+#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */
#endif
return 0;
diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h
similarity index 100%
rename from bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h
rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h
diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h
similarity index 100%
rename from bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h
rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h
diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h
similarity index 100%
rename from bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h
rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h
diff --git a/bsp/cvitek/drivers/cv1800b/pinctrl.h b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
similarity index 100%
rename from bsp/cvitek/drivers/cv1800b/pinctrl.h
rename to bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
diff --git a/bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h b/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h
rename to bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h
diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h
new file mode 100755
index 00000000000..64d4ec9cdb2
--- /dev/null
+++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h
@@ -0,0 +1,653 @@
+
+#define CAM_MCLK0__CAM_MCLK0 0
+#define CAM_MCLK0__AUX1 2
+#define CAM_MCLK0__XGPIOA_0 3
+#define CAM_PD0__IIS1_MCLK 1
+#define CAM_PD0__XGPIOA_1 3
+#define CAM_PD0__CAM_HS0 4
+#define CAM_RST0__XGPIOA_2 3
+#define CAM_RST0__CAM_VS0 4
+#define CAM_RST0__IIC4_SCL 6
+#define CAM_MCLK1__CAM_MCLK1 0
+#define CAM_MCLK1__AUX2 2
+#define CAM_MCLK1__XGPIOA_3 3
+#define CAM_MCLK1__CAM_HS0 4
+#define CAM_PD1__IIS1_MCLK 1
+#define CAM_PD1__XGPIOA_4 3
+#define CAM_PD1__CAM_VS0 4
+#define CAM_PD1__IIC4_SDA 6
+#define IIC3_SCL__IIC3_SCL 0
+#define IIC3_SCL__XGPIOA_5 3
+#define IIC3_SDA__IIC3_SDA 0
+#define IIC3_SDA__XGPIOA_6 3
+#define SD0_CLK__SDIO0_CLK 0
+#define SD0_CLK__IIC1_SDA 1
+#define SD0_CLK__SPI0_SCK 2
+#define SD0_CLK__XGPIOA_7 3
+#define SD0_CLK__PWM_15 5
+#define SD0_CLK__EPHY_LNK_LED 6
+#define SD0_CLK__DBG_0 7
+#define SD0_CMD__SDIO0_CMD 0
+#define SD0_CMD__IIC1_SCL 1
+#define SD0_CMD__SPI0_SDO 2
+#define SD0_CMD__XGPIOA_8 3
+#define SD0_CMD__PWM_14 5
+#define SD0_CMD__EPHY_SPD_LED 6
+#define SD0_CMD__DBG_1 7
+#define SD0_D0__SDIO0_D_0 0
+#define SD0_D0__CAM_MCLK1 1
+#define SD0_D0__SPI0_SDI 2
+#define SD0_D0__XGPIOA_9 3
+#define SD0_D0__UART3_TX 4
+#define SD0_D0__PWM_13 5
+#define SD0_D0__WG0_D0 6
+#define SD0_D0__DBG_2 7
+#define SD0_D1__SDIO0_D_1 0
+#define SD0_D1__IIC1_SDA 1
+#define SD0_D1__AUX0 2
+#define SD0_D1__XGPIOA_10 3
+#define SD0_D1__UART1_TX 4
+#define SD0_D1__PWM_12 5
+#define SD0_D1__WG0_D1 6
+#define SD0_D1__DBG_3 7
+#define SD0_D2__SDIO0_D_2 0
+#define SD0_D2__IIC1_SCL 1
+#define SD0_D2__AUX1 2
+#define SD0_D2__XGPIOA_11 3
+#define SD0_D2__UART1_RX 4
+#define SD0_D2__PWM_11 5
+#define SD0_D2__WG1_D0 6
+#define SD0_D2__DBG_4 7
+#define SD0_D3__SDIO0_D_3 0
+#define SD0_D3__CAM_MCLK0 1
+#define SD0_D3__SPI0_CS_X 2
+#define SD0_D3__XGPIOA_12 3
+#define SD0_D3__UART3_RX 4
+#define SD0_D3__PWM_10 5
+#define SD0_D3__WG1_D1 6
+#define SD0_D3__DBG_5 7
+#define SD0_CD__SDIO0_CD 0
+#define SD0_CD__XGPIOA_13 3
+#define SD0_PWR_EN__SDIO0_PWR_EN 0
+#define SD0_PWR_EN__XGPIOA_14 3
+#define SPK_EN__XGPIOA_15 3
+#define UART0_TX__UART0_TX 0
+#define UART0_TX__CAM_MCLK1 1
+#define UART0_TX__PWM_4 2
+#define UART0_TX__XGPIOA_16 3
+#define UART0_TX__UART1_TX 4
+#define UART0_TX__AUX1 5
+#define UART0_TX__DBG_6 7
+#define UART0_RX__UART0_RX 0
+#define UART0_RX__CAM_MCLK0 1
+#define UART0_RX__PWM_5 2
+#define UART0_RX__XGPIOA_17 3
+#define UART0_RX__UART1_RX 4
+#define UART0_RX__AUX0 5
+#define UART0_RX__DBG_7 7
+#define EMMC_RSTN__EMMC_RSTN 0
+#define EMMC_RSTN__XGPIOA_21 3
+#define EMMC_RSTN__AUX2 4
+#define EMMC_DAT2__EMMC_DAT_2 0
+#define EMMC_DAT2__SPINOR_HOLD_X 1
+#define EMMC_DAT2__SPINAND_HOLD 2
+#define EMMC_DAT2__XGPIOA_26 3
+#define EMMC_CLK__EMMC_CLK 0
+#define EMMC_CLK__SPINOR_SCK 1
+#define EMMC_CLK__SPINAND_CLK 2
+#define EMMC_CLK__XGPIOA_22 3
+#define EMMC_DAT0__EMMC_DAT_0 0
+#define EMMC_DAT0__SPINOR_MOSI 1
+#define EMMC_DAT0__SPINAND_MOSI 2
+#define EMMC_DAT0__XGPIOA_25 3
+#define EMMC_DAT3__EMMC_DAT_3 0
+#define EMMC_DAT3__SPINOR_WP_X 1
+#define EMMC_DAT3__SPINAND_WP 2
+#define EMMC_DAT3__XGPIOA_27 3
+#define EMMC_CMD__EMMC_CMD 0
+#define EMMC_CMD__SPINOR_MISO 1
+#define EMMC_CMD__SPINAND_MISO 2
+#define EMMC_CMD__XGPIOA_23 3
+#define EMMC_DAT1__EMMC_DAT_1 0
+#define EMMC_DAT1__SPINOR_CS_X 1
+#define EMMC_DAT1__SPINAND_CS 2
+#define EMMC_DAT1__XGPIOA_24 3
+#define JTAG_CPU_TMS__JTAG_CPU_TMS 0
+#define JTAG_CPU_TMS__CAM_MCLK0 1
+#define JTAG_CPU_TMS__PWM_7 2
+#define JTAG_CPU_TMS__XGPIOA_19 3
+#define JTAG_CPU_TMS__UART1_RTS 4
+#define JTAG_CPU_TMS__AUX0 5
+#define JTAG_CPU_TMS__UART1_TX 6
+#define JTAG_CPU_TMS__VO_D_28 7
+#define JTAG_CPU_TCK__JTAG_CPU_TCK 0
+#define JTAG_CPU_TCK__CAM_MCLK1 1
+#define JTAG_CPU_TCK__PWM_6 2
+#define JTAG_CPU_TCK__XGPIOA_18 3
+#define JTAG_CPU_TCK__UART1_CTS 4
+#define JTAG_CPU_TCK__AUX1 5
+#define JTAG_CPU_TCK__UART1_RX 6
+#define JTAG_CPU_TCK__VO_D_29 7
+#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
+#define JTAG_CPU_TRST__XGPIOA_20 3
+#define JTAG_CPU_TRST__VO_D_30 6
+#define IIC0_SCL__IIC0_SCL 0
+#define IIC0_SCL__UART1_TX 1
+#define IIC0_SCL__UART2_TX 2
+#define IIC0_SCL__XGPIOA_28 3
+#define IIC0_SCL__WG0_D0 5
+#define IIC0_SCL__DBG_10 7
+#define IIC0_SDA__IIC0_SDA 0
+#define IIC0_SDA__UART1_RX 1
+#define IIC0_SDA__UART2_RX 2
+#define IIC0_SDA__XGPIOA_29 3
+#define IIC0_SDA__WG0_D1 5
+#define IIC0_SDA__WG1_D0 6
+#define IIC0_SDA__DBG_11 7
+#define AUX0__AUX0 0
+#define AUX0__XGPIOA_30 3
+#define AUX0__IIS1_MCLK 4
+#define AUX0__VO_D_31 5
+#define AUX0__WG1_D1 6
+#define AUX0__DBG_12 7
+#define PWR_VBAT_DET__PWR_VBAT_DET 0
+#define PWR_RSTN__PWR_RSTN 0
+#define PWR_SEQ1__PWR_SEQ1 0
+#define PWR_SEQ1__PWR_GPIO_3 3
+#define PWR_SEQ2__PWR_SEQ2 0
+#define PWR_SEQ2__PWR_GPIO_4 3
+#define PWR_SEQ3__PWR_SEQ3 0
+#define PWR_SEQ3__PWR_GPIO_5 3
+#define PTEST__PWR_PTEST 0
+#define PWR_WAKEUP0__PWR_WAKEUP0 0
+#define PWR_WAKEUP0__PWR_IR0 1
+#define PWR_WAKEUP0__PWR_UART0_TX 2
+#define PWR_WAKEUP0__PWR_GPIO_6 3
+#define PWR_WAKEUP0__UART1_TX 4
+#define PWR_WAKEUP0__IIC4_SCL 5
+#define PWR_WAKEUP0__EPHY_LNK_LED 6
+#define PWR_WAKEUP0__WG2_D0 7
+#define PWR_WAKEUP1__PWR_WAKEUP1 0
+#define PWR_WAKEUP1__PWR_IR1 1
+#define PWR_WAKEUP1__PWR_GPIO_7 3
+#define PWR_WAKEUP1__UART1_TX 4
+#define PWR_WAKEUP1__IIC4_SCL 5
+#define PWR_WAKEUP1__EPHY_LNK_LED 6
+#define PWR_WAKEUP1__WG0_D0 7
+#define PWR_BUTTON1__PWR_BUTTON1 0
+#define PWR_BUTTON1__PWR_GPIO_8 3
+#define PWR_BUTTON1__UART1_RX 4
+#define PWR_BUTTON1__IIC4_SDA 5
+#define PWR_BUTTON1__EPHY_SPD_LED 6
+#define PWR_BUTTON1__WG2_D1 7
+#define PWR_ON__PWR_ON 0
+#define PWR_ON__PWR_GPIO_9 3
+#define PWR_ON__UART1_RX 4
+#define PWR_ON__IIC4_SDA 5
+#define PWR_ON__EPHY_SPD_LED 6
+#define PWR_ON__WG0_D1 7
+#define XTAL_XIN__PWR_XTAL_CLKIN 0
+#define PWR_GPIO0__PWR_GPIO_0 0
+#define PWR_GPIO0__UART2_TX 1
+#define PWR_GPIO0__PWR_UART0_RX 2
+#define PWR_GPIO0__PWM_8 4
+#define PWR_GPIO1__PWR_GPIO_1 0
+#define PWR_GPIO1__UART2_RX 1
+#define PWR_GPIO1__EPHY_LNK_LED 3
+#define PWR_GPIO1__PWM_9 4
+#define PWR_GPIO1__PWR_IIC_SCL 5
+#define PWR_GPIO1__IIC2_SCL 6
+#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7
+#define PWR_GPIO2__PWR_GPIO_2 0
+#define PWR_GPIO2__PWR_SECTICK 2
+#define PWR_GPIO2__EPHY_SPD_LED 3
+#define PWR_GPIO2__PWM_10 4
+#define PWR_GPIO2__PWR_IIC_SDA 5
+#define PWR_GPIO2__IIC2_SDA 6
+#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7
+#define CLK32K__CLK32K 0
+#define CLK32K__AUX0 1
+#define CLK32K__PWR_MCU_JTAG_TDI 2
+#define CLK32K__PWR_GPIO_10 3
+#define CLK32K__PWM_2 4
+#define CLK32K__KEY_COL0 5
+#define CLK32K__CAM_MCLK0 6
+#define CLK32K__DBG_0 7
+#define CLK25M__CLK25M 0
+#define CLK25M__AUX1 1
+#define CLK25M__PWR_MCU_JTAG_TDO 2
+#define CLK25M__PWR_GPIO_11 3
+#define CLK25M__PWM_3 4
+#define CLK25M__KEY_COL1 5
+#define CLK25M__CAM_MCLK1 6
+#define CLK25M__DBG_1 7
+#define IIC2_SCL__IIC2_SCL 0
+#define IIC2_SCL__PWM_14 1
+#define IIC2_SCL__PWR_GPIO_12 3
+#define IIC2_SCL__UART2_RX 4
+#define IIC2_SCL__KEY_COL2 7
+#define IIC2_SDA__IIC2_SDA 0
+#define IIC2_SDA__PWM_15 1
+#define IIC2_SDA__PWR_GPIO_13 3
+#define IIC2_SDA__UART2_TX 4
+#define IIC2_SDA__IIS1_MCLK 5
+#define IIC2_SDA__IIS2_MCLK 6
+#define IIC2_SDA__KEY_COL3 7
+#define UART2_TX__UART2_TX 0
+#define UART2_TX__PWM_11 1
+#define UART2_TX__PWR_UART1_TX 2
+#define UART2_TX__PWR_GPIO_14 3
+#define UART2_TX__KEY_ROW3 4
+#define UART2_TX__UART4_TX 5
+#define UART2_TX__IIS2_BCLK 6
+#define UART2_TX__WG2_D0 7
+#define UART2_RTS__UART2_RTS 0
+#define UART2_RTS__PWM_8 1
+#define UART2_RTS__PWR_GPIO_15 3
+#define UART2_RTS__KEY_ROW0 4
+#define UART2_RTS__UART4_RTS 5
+#define UART2_RTS__IIS2_DO 6
+#define UART2_RTS__WG1_D0 7
+#define UART2_RX__UART2_RX 0
+#define UART2_RX__PWM_10 1
+#define UART2_RX__PWR_UART1_RX 2
+#define UART2_RX__PWR_GPIO_16 3
+#define UART2_RX__KEY_COL3 4
+#define UART2_RX__UART4_RX 5
+#define UART2_RX__IIS2_DI 6
+#define UART2_RX__WG2_D1 7
+#define UART2_CTS__UART2_CTS 0
+#define UART2_CTS__PWM_9 1
+#define UART2_CTS__PWR_GPIO_17 3
+#define UART2_CTS__KEY_ROW1 4
+#define UART2_CTS__UART4_CTS 5
+#define UART2_CTS__IIS2_LRCK 6
+#define UART2_CTS__WG1_D1 7
+#define SD1_D3__PWR_SD1_D3_VO32 0
+#define SD1_D3__SPI2_CS_X 1
+#define SD1_D3__IIC1_SCL 2
+#define SD1_D3__PWR_GPIO_18 3
+#define SD1_D3__CAM_MCLK0 4
+#define SD1_D3__UART3_CTS 5
+#define SD1_D3__PWR_SPINOR1_CS_X 6
+#define SD1_D3__PWM_4 7
+#define SD1_D2__PWR_SD1_D2_VO33 0
+#define SD1_D2__IIC1_SCL 1
+#define SD1_D2__UART2_TX 2
+#define SD1_D2__PWR_GPIO_19 3
+#define SD1_D2__CAM_MCLK0 4
+#define SD1_D2__UART3_TX 5
+#define SD1_D2__PWR_SPINOR1_HOLD_X 6
+#define SD1_D2__PWM_5 7
+#define SD1_D1__PWR_SD1_D1_VO34 0
+#define SD1_D1__IIC1_SDA 1
+#define SD1_D1__UART2_RX 2
+#define SD1_D1__PWR_GPIO_20 3
+#define SD1_D1__CAM_MCLK1 4
+#define SD1_D1__UART3_RX 5
+#define SD1_D1__PWR_SPINOR1_WP_X 6
+#define SD1_D1__PWM_6 7
+#define SD1_D0__PWR_SD1_D0_VO35 0
+#define SD1_D0__SPI2_SDI 1
+#define SD1_D0__IIC1_SDA 2
+#define SD1_D0__PWR_GPIO_21 3
+#define SD1_D0__CAM_MCLK1 4
+#define SD1_D0__UART3_RTS 5
+#define SD1_D0__PWR_SPINOR1_MISO 6
+#define SD1_D0__PWM_7 7
+#define SD1_CMD__PWR_SD1_CMD_VO36 0
+#define SD1_CMD__SPI2_SDO 1
+#define SD1_CMD__IIC3_SCL 2
+#define SD1_CMD__PWR_GPIO_22 3
+#define SD1_CMD__CAM_VS0 4
+#define SD1_CMD__EPHY_LNK_LED 5
+#define SD1_CMD__PWR_SPINOR1_MOSI 6
+#define SD1_CMD__PWM_8 7
+#define SD1_CLK__PWR_SD1_CLK_VO37 0
+#define SD1_CLK__SPI2_SCK 1
+#define SD1_CLK__IIC3_SDA 2
+#define SD1_CLK__PWR_GPIO_23 3
+#define SD1_CLK__CAM_HS0 4
+#define SD1_CLK__EPHY_SPD_LED 5
+#define SD1_CLK__PWR_SPINOR1_SCK 6
+#define SD1_CLK__PWM_9 7
+#define RSTN__RSTN 0
+#define PWM0_BUCK__PWM_0 0
+#define PWM0_BUCK__XGPIOB_0 3
+#define ADC3__CAM_MCLK0 1
+#define ADC3__IIC4_SCL 2
+#define ADC3__XGPIOB_1 3
+#define ADC3__PWM_12 4
+#define ADC3__EPHY_LNK_LED 5
+#define ADC3__WG2_D0 6
+#define ADC3__UART3_TX 7
+#define ADC2__CAM_MCLK1 1
+#define ADC2__IIC4_SDA 2
+#define ADC2__XGPIOB_2 3
+#define ADC2__PWM_13 4
+#define ADC2__EPHY_SPD_LED 5
+#define ADC2__WG2_D1 6
+#define ADC2__UART3_RX 7
+#define ADC1__XGPIOB_3 3
+#define ADC1__KEY_COL2 4
+#define USB_ID__USB_ID 0
+#define USB_ID__XGPIOB_4 3
+#define USB_VBUS_EN__USB_VBUS_EN 0
+#define USB_VBUS_EN__XGPIOB_5 3
+#define PKG_TYPE0__PKG_TYPE0 0
+#define USB_VBUS_DET__USB_VBUS_DET 0
+#define USB_VBUS_DET__XGPIOB_6 3
+#define USB_VBUS_DET__CAM_MCLK0 4
+#define USB_VBUS_DET__CAM_MCLK1 5
+#define PKG_TYPE1__PKG_TYPE1 0
+#define PKG_TYPE2__PKG_TYPE2 0
+#define MUX_SPI1_MISO__UART3_RTS 1
+#define MUX_SPI1_MISO__IIC1_SDA 2
+#define MUX_SPI1_MISO__XGPIOB_8 3
+#define MUX_SPI1_MISO__PWM_9 4
+#define MUX_SPI1_MISO__KEY_COL1 5
+#define MUX_SPI1_MISO__SPI1_SDI 6
+#define MUX_SPI1_MISO__DBG_14 7
+#define MUX_SPI1_MOSI__UART3_RX 1
+#define MUX_SPI1_MOSI__IIC1_SCL 2
+#define MUX_SPI1_MOSI__XGPIOB_7 3
+#define MUX_SPI1_MOSI__PWM_8 4
+#define MUX_SPI1_MOSI__KEY_COL0 5
+#define MUX_SPI1_MOSI__SPI1_SDO 6
+#define MUX_SPI1_MOSI__DBG_13 7
+#define MUX_SPI1_CS__UART3_CTS 1
+#define MUX_SPI1_CS__CAM_MCLK0 2
+#define MUX_SPI1_CS__XGPIOB_10 3
+#define MUX_SPI1_CS__PWM_11 4
+#define MUX_SPI1_CS__KEY_ROW3 5
+#define MUX_SPI1_CS__SPI1_CS_X 6
+#define MUX_SPI1_CS__DBG_16 7
+#define MUX_SPI1_SCK__UART3_TX 1
+#define MUX_SPI1_SCK__CAM_MCLK1 2
+#define MUX_SPI1_SCK__XGPIOB_9 3
+#define MUX_SPI1_SCK__PWM_10 4
+#define MUX_SPI1_SCK__KEY_ROW2 5
+#define MUX_SPI1_SCK__SPI1_SCK 6
+#define MUX_SPI1_SCK__DBG_15 7
+#define PAD_ETH_TXM__UART3_RTS 1
+#define PAD_ETH_TXM__IIC1_SDA 2
+#define PAD_ETH_TXM__XGPIOB_24 3
+#define PAD_ETH_TXM__PWM_12 4
+#define PAD_ETH_TXM__CAM_MCLK1 5
+#define PAD_ETH_TXM__SPI1_SDI 6
+#define PAD_ETH_TXM__IIS2_BCLK 7
+#define PAD_ETH_TXP__UART3_RX 1
+#define PAD_ETH_TXP__IIC1_SCL 2
+#define PAD_ETH_TXP__XGPIOB_25 3
+#define PAD_ETH_TXP__PWM_13 4
+#define PAD_ETH_TXP__CAM_MCLK0 5
+#define PAD_ETH_TXP__SPI1_SDO 6
+#define PAD_ETH_TXP__IIS2_LRCK 7
+#define PAD_ETH_RXM__UART3_CTS 1
+#define PAD_ETH_RXM__CAM_MCLK0 2
+#define PAD_ETH_RXM__XGPIOB_26 3
+#define PAD_ETH_RXM__PWM_14 4
+#define PAD_ETH_RXM__CAM_VS0 5
+#define PAD_ETH_RXM__SPI1_CS_X 6
+#define PAD_ETH_RXM__IIS2_DI 7
+#define PAD_ETH_RXP__UART3_TX 1
+#define PAD_ETH_RXP__CAM_MCLK1 2
+#define PAD_ETH_RXP__XGPIOB_27 3
+#define PAD_ETH_RXP__PWM_15 4
+#define PAD_ETH_RXP__CAM_HS0 5
+#define PAD_ETH_RXP__SPI1_SCK 6
+#define PAD_ETH_RXP__IIS2_DO 7
+#define VIVO_D10__PWM_1 0
+#define VIVO_D10__VI1_D_10 1
+#define VIVO_D10__VO_D_23 2
+#define VIVO_D10__XGPIOB_11 3
+#define VIVO_D10__RMII0_IRQ 4
+#define VIVO_D10__CAM_MCLK0 5
+#define VIVO_D10__IIC1_SDA 6
+#define VIVO_D10__UART2_TX 7
+#define VIVO_D9__PWM_2 0
+#define VIVO_D9__VI1_D_9 1
+#define VIVO_D9__VO_D_22 2
+#define VIVO_D9__XGPIOB_12 3
+#define VIVO_D9__CAM_MCLK1 5
+#define VIVO_D9__IIC1_SCL 6
+#define VIVO_D9__UART2_RX 7
+#define VIVO_D8__PWM_3 0
+#define VIVO_D8__VI1_D_8 1
+#define VIVO_D8__VO_D_21 2
+#define VIVO_D8__XGPIOB_13 3
+#define VIVO_D8__RMII0_MDIO 4
+#define VIVO_D8__SPI3_SDO 5
+#define VIVO_D8__IIC2_SCL 6
+#define VIVO_D8__CAM_VS0 7
+#define VIVO_D7__VI2_D_7 0
+#define VIVO_D7__VI1_D_7 1
+#define VIVO_D7__VO_D_20 2
+#define VIVO_D7__XGPIOB_14 3
+#define VIVO_D7__RMII0_RXD1 4
+#define VIVO_D7__SPI3_SDI 5
+#define VIVO_D7__IIC2_SDA 6
+#define VIVO_D7__CAM_HS0 7
+#define VIVO_D6__VI2_D_6 0
+#define VIVO_D6__VI1_D_6 1
+#define VIVO_D6__VO_D_19 2
+#define VIVO_D6__XGPIOB_15 3
+#define VIVO_D6__RMII0_REFCLKI 4
+#define VIVO_D6__SPI3_SCK 5
+#define VIVO_D6__UART2_TX 6
+#define VIVO_D6__CAM_VS0 7
+#define VIVO_D5__VI2_D_5 0
+#define VIVO_D5__VI1_D_5 1
+#define VIVO_D5__VO_D_18 2
+#define VIVO_D5__XGPIOB_16 3
+#define VIVO_D5__RMII0_RXD0 4
+#define VIVO_D5__SPI3_CS_X 5
+#define VIVO_D5__UART2_RX 6
+#define VIVO_D5__CAM_HS0 7
+#define VIVO_D4__VI2_D_4 0
+#define VIVO_D4__VI1_D_4 1
+#define VIVO_D4__VO_D_17 2
+#define VIVO_D4__XGPIOB_17 3
+#define VIVO_D4__RMII0_MDC 4
+#define VIVO_D4__IIC1_SDA 5
+#define VIVO_D4__UART2_CTS 6
+#define VIVO_D4__CAM_VS0 7
+#define VIVO_D3__VI2_D_3 0
+#define VIVO_D3__VI1_D_3 1
+#define VIVO_D3__VO_D_16 2
+#define VIVO_D3__XGPIOB_18 3
+#define VIVO_D3__RMII0_TXD0 4
+#define VIVO_D3__IIC1_SCL 5
+#define VIVO_D3__UART2_RTS 6
+#define VIVO_D3__CAM_HS0 7
+#define VIVO_D2__VI2_D_2 0
+#define VIVO_D2__VI1_D_2 1
+#define VIVO_D2__VO_D_15 2
+#define VIVO_D2__XGPIOB_19 3
+#define VIVO_D2__RMII0_TXD1 4
+#define VIVO_D2__CAM_MCLK1 5
+#define VIVO_D2__PWM_2 6
+#define VIVO_D2__UART2_TX 7
+#define VIVO_D1__VI2_D_1 0
+#define VIVO_D1__VI1_D_1 1
+#define VIVO_D1__VO_D_14 2
+#define VIVO_D1__XGPIOB_20 3
+#define VIVO_D1__RMII0_RXDV 4
+#define VIVO_D1__IIC3_SDA 5
+#define VIVO_D1__PWM_3 6
+#define VIVO_D1__IIC4_SCL 7
+#define VIVO_D0__VI2_D_0 0
+#define VIVO_D0__VI1_D_0 1
+#define VIVO_D0__VO_D_13 2
+#define VIVO_D0__XGPIOB_21 3
+#define VIVO_D0__RMII0_TXCLK 4
+#define VIVO_D0__IIC3_SCL 5
+#define VIVO_D0__WG1_D0 6
+#define VIVO_D0__IIC4_SDA 7
+#define VIVO_CLK__VI2_CLK 0
+#define VIVO_CLK__VI1_CLK 1
+#define VIVO_CLK__VO_CLK1 2
+#define VIVO_CLK__XGPIOB_22 3
+#define VIVO_CLK__RMII0_TXEN 4
+#define VIVO_CLK__CAM_MCLK0 5
+#define VIVO_CLK__WG1_D1 6
+#define VIVO_CLK__UART2_RX 7
+#define PAD_MIPIRX5N__VI1_D_11 1
+#define PAD_MIPIRX5N__VO_D_12 2
+#define PAD_MIPIRX5N__XGPIOC_0 3
+#define PAD_MIPIRX5N__CAM_MCLK0 5
+#define PAD_MIPIRX5N__WG0_D0 6
+#define PAD_MIPIRX5N__DBG_0 7
+#define PAD_MIPIRX5P__VI1_D_12 1
+#define PAD_MIPIRX5P__VO_D_11 2
+#define PAD_MIPIRX5P__XGPIOC_1 3
+#define PAD_MIPIRX5P__IIS1_MCLK 4
+#define PAD_MIPIRX5P__CAM_MCLK1 5
+#define PAD_MIPIRX5P__WG0_D1 6
+#define PAD_MIPIRX5P__DBG_1 7
+#define PAD_MIPIRX4N__VI0_CLK 1
+#define PAD_MIPIRX4N__VI1_D_13 2
+#define PAD_MIPIRX4N__XGPIOC_2 3
+#define PAD_MIPIRX4N__IIC1_SDA 4
+#define PAD_MIPIRX4N__CAM_MCLK0 5
+#define PAD_MIPIRX4N__KEY_ROW0 6
+#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
+#define PAD_MIPIRX4P__VI0_D_0 1
+#define PAD_MIPIRX4P__VI1_D_14 2
+#define PAD_MIPIRX4P__XGPIOC_3 3
+#define PAD_MIPIRX4P__IIC1_SCL 4
+#define PAD_MIPIRX4P__CAM_MCLK1 5
+#define PAD_MIPIRX4P__KEY_ROW1 6
+#define PAD_MIPIRX4P__MUX_SPI1_CS 7
+#define PAD_MIPIRX3N__VI0_D_1 1
+#define PAD_MIPIRX3N__VI1_D_15 2
+#define PAD_MIPIRX3N__XGPIOC_4 3
+#define PAD_MIPIRX3N__CAM_MCLK0 4
+#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
+#define PAD_MIPIRX3P__VI0_D_2 1
+#define PAD_MIPIRX3P__VI1_D_16 2
+#define PAD_MIPIRX3P__XGPIOC_5 3
+#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
+#define PAD_MIPIRX2N__VI0_D_3 1
+#define PAD_MIPIRX2N__VO_D_10 2
+#define PAD_MIPIRX2N__XGPIOC_6 3
+#define PAD_MIPIRX2N__VI1_D_17 4
+#define PAD_MIPIRX2N__IIC4_SCL 5
+#define PAD_MIPIRX2N__DBG_6 7
+#define PAD_MIPIRX2P__VI0_D_4 1
+#define PAD_MIPIRX2P__VO_D_9 2
+#define PAD_MIPIRX2P__XGPIOC_7 3
+#define PAD_MIPIRX2P__VI1_D_18 4
+#define PAD_MIPIRX2P__IIC4_SDA 5
+#define PAD_MIPIRX2P__DBG_7 7
+#define PAD_MIPIRX1N__VI0_D_5 1
+#define PAD_MIPIRX1N__VO_D_8 2
+#define PAD_MIPIRX1N__XGPIOC_8 3
+#define PAD_MIPIRX1N__KEY_ROW3 6
+#define PAD_MIPIRX1N__DBG_8 7
+#define PAD_MIPIRX1P__VI0_D_6 1
+#define PAD_MIPIRX1P__VO_D_7 2
+#define PAD_MIPIRX1P__XGPIOC_9 3
+#define PAD_MIPIRX1P__IIC1_SDA 4
+#define PAD_MIPIRX1P__KEY_ROW2 6
+#define PAD_MIPIRX1P__DBG_9 7
+#define PAD_MIPIRX0N__VI0_D_7 1
+#define PAD_MIPIRX0N__VO_D_6 2
+#define PAD_MIPIRX0N__XGPIOC_10 3
+#define PAD_MIPIRX0N__IIC1_SCL 4
+#define PAD_MIPIRX0N__CAM_MCLK1 5
+#define PAD_MIPIRX0N__DBG_10 7
+#define PAD_MIPIRX0P__VI0_D_8 1
+#define PAD_MIPIRX0P__VO_D_5 2
+#define PAD_MIPIRX0P__XGPIOC_11 3
+#define PAD_MIPIRX0P__CAM_MCLK0 4
+#define PAD_MIPIRX0P__DBG_11 7
+#define PAD_MIPI_TXM4__SD1_CLK 1
+#define PAD_MIPI_TXM4__VO_D_24 2
+#define PAD_MIPI_TXM4__XGPIOC_18 3
+#define PAD_MIPI_TXM4__CAM_MCLK1 4
+#define PAD_MIPI_TXM4__PWM_12 5
+#define PAD_MIPI_TXM4__IIC1_SDA 6
+#define PAD_MIPI_TXM4__DBG_18 7
+#define PAD_MIPI_TXP4__SD1_CMD 1
+#define PAD_MIPI_TXP4__VO_D_25 2
+#define PAD_MIPI_TXP4__XGPIOC_19 3
+#define PAD_MIPI_TXP4__CAM_MCLK0 4
+#define PAD_MIPI_TXP4__PWM_13 5
+#define PAD_MIPI_TXP4__IIC1_SCL 6
+#define PAD_MIPI_TXP4__DBG_19 7
+#define PAD_MIPI_TXM3__SD1_D0 1
+#define PAD_MIPI_TXM3__VO_D_26 2
+#define PAD_MIPI_TXM3__XGPIOC_20 3
+#define PAD_MIPI_TXM3__IIC2_SDA 4
+#define PAD_MIPI_TXM3__PWM_14 5
+#define PAD_MIPI_TXM3__IIC1_SDA 6
+#define PAD_MIPI_TXM3__CAM_VS0 7
+#define PAD_MIPI_TXP3__SD1_D1 1
+#define PAD_MIPI_TXP3__VO_D_27 2
+#define PAD_MIPI_TXP3__XGPIOC_21 3
+#define PAD_MIPI_TXP3__IIC2_SCL 4
+#define PAD_MIPI_TXP3__PWM_15 5
+#define PAD_MIPI_TXP3__IIC1_SCL 6
+#define PAD_MIPI_TXP3__CAM_HS0 7
+#define PAD_MIPI_TXM2__VI0_D_13 1
+#define PAD_MIPI_TXM2__VO_D_0 2
+#define PAD_MIPI_TXM2__XGPIOC_16 3
+#define PAD_MIPI_TXM2__IIC1_SDA 4
+#define PAD_MIPI_TXM2__PWM_8 5
+#define PAD_MIPI_TXM2__SPI0_SCK 6
+#define PAD_MIPI_TXM2__SD1_D2 7
+#define PAD_MIPI_TXP2__VI0_D_14 1
+#define PAD_MIPI_TXP2__VO_CLK0 2
+#define PAD_MIPI_TXP2__XGPIOC_17 3
+#define PAD_MIPI_TXP2__IIC1_SCL 4
+#define PAD_MIPI_TXP2__PWM_9 5
+#define PAD_MIPI_TXP2__SPI0_CS_X 6
+#define PAD_MIPI_TXP2__SD1_D3 7
+#define PAD_MIPI_TXM1__VI0_D_11 1
+#define PAD_MIPI_TXM1__VO_D_2 2
+#define PAD_MIPI_TXM1__XGPIOC_14 3
+#define PAD_MIPI_TXM1__IIC2_SDA 4
+#define PAD_MIPI_TXM1__PWM_10 5
+#define PAD_MIPI_TXM1__SPI0_SDO 6
+#define PAD_MIPI_TXM1__DBG_14 7
+#define PAD_MIPI_TXP1__VI0_D_12 1
+#define PAD_MIPI_TXP1__VO_D_1 2
+#define PAD_MIPI_TXP1__XGPIOC_15 3
+#define PAD_MIPI_TXP1__IIC2_SCL 4
+#define PAD_MIPI_TXP1__PWM_11 5
+#define PAD_MIPI_TXP1__SPI0_SDI 6
+#define PAD_MIPI_TXP1__DBG_15 7
+#define PAD_MIPI_TXM0__VI0_D_9 1
+#define PAD_MIPI_TXM0__VO_D_4 2
+#define PAD_MIPI_TXM0__XGPIOC_12 3
+#define PAD_MIPI_TXM0__CAM_MCLK1 4
+#define PAD_MIPI_TXM0__PWM_14 5
+#define PAD_MIPI_TXM0__CAM_VS0 6
+#define PAD_MIPI_TXM0__DBG_12 7
+#define PAD_MIPI_TXP0__VI0_D_10 1
+#define PAD_MIPI_TXP0__VO_D_3 2
+#define PAD_MIPI_TXP0__XGPIOC_13 3
+#define PAD_MIPI_TXP0__CAM_MCLK0 4
+#define PAD_MIPI_TXP0__PWM_15 5
+#define PAD_MIPI_TXP0__CAM_HS0 6
+#define PAD_MIPI_TXP0__DBG_13 7
+#define PAD_AUD_AINL_MIC__XGPIOC_23 3
+#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
+#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
+#define PAD_AUD_AINR_MIC__XGPIOC_22 3
+#define PAD_AUD_AINR_MIC__IIS1_DO 4
+#define PAD_AUD_AINR_MIC__IIS2_DI 5
+#define PAD_AUD_AINR_MIC__IIS1_DI 6
+#define PAD_AUD_AOUTL__XGPIOC_25 3
+#define PAD_AUD_AOUTL__IIS1_LRCK 4
+#define PAD_AUD_AOUTL__IIS2_LRCK 5
+#define PAD_AUD_AOUTR__XGPIOC_24 3
+#define PAD_AUD_AOUTR__IIS1_DI 4
+#define PAD_AUD_AOUTR__IIS2_DO 5
+#define PAD_AUD_AOUTR__IIS1_DO 6
+#define GPIO_RTX__XGPIOB_23 3
+#define GPIO_RTX__PWM_1 4
+#define GPIO_RTX__CAM_MCLK0 5
+#define GPIO_ZQ__PWR_GPIO_24 3
+#define GPIO_ZQ__PWM_2 4
diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h
new file mode 100755
index 00000000000..9b3e81ef424
--- /dev/null
+++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h
@@ -0,0 +1,46 @@
+#ifndef _CV181X_PINMUX_H_
+#define _CV181X_PINMUX_H_
+
+#define PINMUX_UART0 0
+#define PINMUX_UART1 1
+#define PINMUX_UART2 2
+#define PINMUX_UART3 3
+#define PINMUX_UART3_2 4
+#define PINMUX_I2C0 5
+#define PINMUX_I2C1 6
+#define PINMUX_I2C2 7
+#define PINMUX_I2C3 8
+#define PINMUX_I2C4 9
+#define PINMUX_I2C4_2 10
+#define PINMUX_SPI0 11
+#define PINMUX_SPI1 12
+#define PINMUX_SPI2 13
+#define PINMUX_SPI2_2 14
+#define PINMUX_SPI3 15
+#define PINMUX_SPI3_2 16
+#define PINMUX_I2S0 17
+#define PINMUX_I2S1 18
+#define PINMUX_I2S2 19
+#define PINMUX_I2S3 20
+#define PINMUX_USBID 21
+#define PINMUX_SDIO0 22
+#define PINMUX_SDIO1 23
+#define PINMUX_ND 24
+#define PINMUX_EMMC 25
+#define PINMUX_SPI_NOR 26
+#define PINMUX_SPI_NAND 27
+#define PINMUX_CAM0 28
+#define PINMUX_CAM1 29
+#define PINMUX_PCM0 30
+#define PINMUX_PCM1 31
+#define PINMUX_CSI0 32
+#define PINMUX_CSI1 33
+#define PINMUX_CSI2 34
+#define PINMUX_DSI 35
+#define PINMUX_VI0 36
+#define PINMUX_VO 37
+#define PINMUX_PWM1 38
+#define PINMUX_UART4 39
+#define PINMUX_SPI_NOR1 40
+
+#endif // end of _CV181X_PINMUX_H_
diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h
new file mode 100755
index 00000000000..5dbf34be305
--- /dev/null
+++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h
@@ -0,0 +1,475 @@
+// $Module: fmux_gpio $
+// $RegisterBank Version: V 1.0.00 $
+// $Author: ghost $
+// $Date: Fri, 30 Jul 2021 08:58:54 PM $
+//
+
+//GEN REG ADDR/OFFSET/MASK
+#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK0 0x0
+#define FMUX_GPIO_REG_IOCTRL_CAM_PD0 0x4
+#define FMUX_GPIO_REG_IOCTRL_CAM_RST0 0x8
+#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK1 0xc
+#define FMUX_GPIO_REG_IOCTRL_CAM_PD1 0x10
+#define FMUX_GPIO_REG_IOCTRL_IIC3_SCL 0x14
+#define FMUX_GPIO_REG_IOCTRL_IIC3_SDA 0x18
+#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x1c
+#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x20
+#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x24
+#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0x28
+#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x2c
+#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x30
+#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x34
+#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x38
+#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x3c
+#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x40
+#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x44
+#define FMUX_GPIO_REG_IOCTRL_EMMC_RSTN 0x48
+#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT2 0x4c
+#define FMUX_GPIO_REG_IOCTRL_EMMC_CLK 0x50
+#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT0 0x54
+#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT3 0x58
+#define FMUX_GPIO_REG_IOCTRL_EMMC_CMD 0x5c
+#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT1 0x60
+#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x64
+#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x68
+#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST 0x6c
+#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x70
+#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x74
+#define FMUX_GPIO_REG_IOCTRL_AUX0 0x78
+#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x7c
+#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x80
+#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x84
+#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x88
+#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ3 0x8c
+#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x90
+#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1 0x94
+#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x98
+#define FMUX_GPIO_REG_IOCTRL_PWR_ON 0x9c
+#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0xa0
+#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0xa4
+#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0xa8
+#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0xac
+#define FMUX_GPIO_REG_IOCTRL_CLK32K 0xb0
+#define FMUX_GPIO_REG_IOCTRL_CLK25M 0xb4
+#define FMUX_GPIO_REG_IOCTRL_IIC2_SCL 0xb8
+#define FMUX_GPIO_REG_IOCTRL_IIC2_SDA 0xbc
+#define FMUX_GPIO_REG_IOCTRL_UART2_TX 0xc0
+#define FMUX_GPIO_REG_IOCTRL_UART2_RTS 0xc4
+#define FMUX_GPIO_REG_IOCTRL_UART2_RX 0xc8
+#define FMUX_GPIO_REG_IOCTRL_UART2_CTS 0xcc
+#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0xd0
+#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0xd4
+#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0xd8
+#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0xdc
+#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0xe0
+#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xe4
+#define FMUX_GPIO_REG_IOCTRL_RSTN 0xe8
+#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xec
+#define FMUX_GPIO_REG_IOCTRL_ADC3 0xf0
+#define FMUX_GPIO_REG_IOCTRL_ADC2 0xf4
+#define FMUX_GPIO_REG_IOCTRL_ADC1 0xf8
+#define FMUX_GPIO_REG_IOCTRL_USB_ID 0xfc
+#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN 0x100
+#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x104
+#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0x108
+#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x10c
+#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x110
+#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0x114
+#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0x118
+#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0x11c
+#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0x120
+#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0x124
+#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0x128
+#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0x12c
+#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0x130
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D10 0x134
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D9 0x138
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D8 0x13c
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D7 0x140
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D6 0x144
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D5 0x148
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D4 0x14c
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D3 0x150
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D2 0x154
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D1 0x158
+#define FMUX_GPIO_REG_IOCTRL_VIVO_D0 0x15c
+#define FMUX_GPIO_REG_IOCTRL_VIVO_CLK 0x160
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N 0x164
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P 0x168
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0x16c
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0x170
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0x174
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0x178
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0x17c
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0x180
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0x184
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0x188
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0x18c
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0x190
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4 0x194
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4 0x198
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3 0x19c
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3 0x1a0
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0x1a4
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x1a8
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x1ac
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x1b0
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x1b4
+#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x1b8
+#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1bc
+#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1c0
+#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x1c4
+#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x1c8
+#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0x1cc
+#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x1d0
+#define FMUX_GPIO_FUNCSEL_CAM_MCLK0 0x0
+#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_CAM_PD0 0x4
+#define FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CAM_PD0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_CAM_RST0 0x8
+#define FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CAM_RST0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_CAM_MCLK1 0xc
+#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_CAM_PD1 0x10
+#define FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CAM_PD1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_IIC3_SCL 0x14
+#define FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_IIC3_SDA 0x18
+#define FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x1c
+#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x20
+#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_D0 0x24
+#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_D1 0x28
+#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_D2 0x2c
+#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_D3 0x30
+#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_CD 0x34
+#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x38
+#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SPK_EN 0x3c
+#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_UART0_TX 0x40
+#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_UART0_RX 0x44
+#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_RSTN 0x48
+#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT2 0x4c
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_CLK 0x50
+#define FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT0 0x54
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT3 0x58
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_CMD 0x5c
+#define FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT1 0x60
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x64
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x68
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST 0x6c
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x70
+#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x74
+#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_AUX0 0x78
+#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x7c
+#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x80
+#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x84
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x88
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ3 0x8c
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x90
+#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1 0x94
+#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x98
+#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_ON 0x9c
+#define FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_ON_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0xa0
+#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0xa4
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0xa8
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0xac
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_CLK32K 0xb0
+#define FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CLK32K_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_CLK25M 0xb4
+#define FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_CLK25M_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_IIC2_SCL 0xb8
+#define FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_IIC2_SDA 0xbc
+#define FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_UART2_TX 0xc0
+#define FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_UART2_TX_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_UART2_RTS 0xc4
+#define FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_UART2_RTS_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_UART2_RX 0xc8
+#define FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_UART2_RX_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_UART2_CTS 0xcc
+#define FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_UART2_CTS_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD1_D3 0xd0
+#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD1_D2 0xd4
+#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD1_D1 0xd8
+#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD1_D0 0xdc
+#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD1_CMD 0xe0
+#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xe4
+#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_RSTN 0xe8
+#define FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_RSTN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xec
+#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_ADC3 0xf0
+#define FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_ADC3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_ADC2 0xf4
+#define FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_ADC2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_ADC1 0xf8
+#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_USB_ID 0xfc
+#define FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_USB_ID_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN 0x100
+#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x104
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0x108
+#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x10c
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x110
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0x114
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0x118
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0x11c
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0x120
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0x124
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0x128
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0x12c
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0x130
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D10 0x134
+#define FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D10_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D9 0x138
+#define FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D9_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D8 0x13c
+#define FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D8_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D7 0x140
+#define FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D7_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D6 0x144
+#define FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D6_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D5 0x148
+#define FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D5_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D4 0x14c
+#define FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D4_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D3 0x150
+#define FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D2 0x154
+#define FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D1 0x158
+#define FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_D0 0x15c
+#define FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_D0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_VIVO_CLK 0x160
+#define FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N 0x164
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P 0x168
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0x16c
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0x170
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0x174
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0x178
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0x17c
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0x180
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0x184
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0x188
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0x18c
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0x190
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4 0x194
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4 0x198
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3 0x19c
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3 0x1a0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0x1a4
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x1a8
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x1ac
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x1b0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x1b4
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x1b8
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x1bc
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x1c0
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x1c4
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x1c8
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0x1cc
+#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7
+#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x1d0
+#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
+#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7
diff --git a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
new file mode 100755
index 00000000000..1f064ebd737
--- /dev/null
+++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
+ *
+ * File Name: pinctrl.h
+ * Description:
+ */
+
+#ifndef __PINCTRL_CV181X_H__
+#define __PINCTRL_CV181X_H__
+
+//#include "../core.h"
+#include "cv181x_pinlist_swconfig.h"
+#include "cv181x_reg_fmux_gpio.h"
+
+#define PAD_MIPI_TXM4__MIPI_TXM4 0
+#define PAD_MIPI_TXP4__MIPI_TXP4 0
+#define PAD_MIPI_TXM3__MIPI_TXM3 0
+#define PAD_MIPI_TXP3__MIPI_TXP3 0
+#define PAD_MIPI_TXM2__MIPI_TXM2 0
+#define PAD_MIPI_TXP2__MIPI_TXP2 0
+#define PAD_MIPI_TXM1__MIPI_TXM1 0
+#define PAD_MIPI_TXP1__MIPI_TXP1 0
+#define PAD_MIPI_TXM0__MIPI_TXM0 0
+#define PAD_MIPI_TXP0__MIPI_TXP0 0
+
+#if defined(ARCH_ARM) && defined(RT_USING_SMART)
+extern rt_ubase_t pinmux_base_ioremap(void);
+#define PINMUX_BASE pinmux_base_ioremap()
+#else
+#define PINMUX_BASE 0x03001000
+#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */
+#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
+#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
+#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
+#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
+ mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
+ PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \
+ PINMUX_VALUE(PIN_NAME, FUNC_NAME))
+
+#endif /* __PINCTRL_CV181X_H__ */
diff --git a/bsp/cvitek/drivers/cv1800b/mmio.h b/bsp/cvitek/drivers/libraries/mmio.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/cvitek/drivers/cv1800b/mmio.h
rename to bsp/cvitek/drivers/libraries/mmio.h
index bc36d5a3ca9..2ef1930a1c1
--- a/bsp/cvitek/drivers/cv1800b/mmio.h
+++ b/bsp/cvitek/drivers/libraries/mmio.h
@@ -9,6 +9,7 @@
#include
#include "types.h"
+#ifndef ARCH_ARM
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
@@ -39,13 +40,12 @@
#define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); })
#define writel(v, c) ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); })
-
#ifdef CONFIG_64BIT
#define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; })
#define writeq(v, c) ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); })
#endif // CONFIG_64BIT
-/*
+#else
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
@@ -69,7 +69,7 @@
#define cpu_write8(a, v) writeb(a, v)
#define cpu_write16(a, v) writew(a, v)
#define cpu_write32(a, v) writel(a, v)
-*/
+#endif /* ARCH_ARM */
#define mmio_wr32 mmio_write_32
#define mmio_rd32 mmio_read_32
diff --git a/bsp/cvitek/drivers/cv1800b/types.h b/bsp/cvitek/drivers/libraries/types.h
similarity index 100%
rename from bsp/cvitek/drivers/cv1800b/types.h
rename to bsp/cvitek/drivers/libraries/types.h
diff --git a/bsp/cvitek/cv1800b/mkimage b/bsp/cvitek/mkimage
similarity index 100%
rename from bsp/cvitek/cv1800b/mkimage
rename to bsp/cvitek/mkimage
diff --git a/bsp/cvitek/mksdimg.sh b/bsp/cvitek/mksdimg.sh
new file mode 100755
index 00000000000..26e70bba620
--- /dev/null
+++ b/bsp/cvitek/mksdimg.sh
@@ -0,0 +1,44 @@
+#/bin/sh
+set -e
+
+PROJECT_PATH=$1
+IMAGE_NAME=$2
+
+if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then
+ echo "Usage: $0 "
+ exit 1
+fi
+
+ROOT_PATH=$(pwd)
+echo ${ROOT_PATH}
+
+. board_env.sh
+
+get_board_type
+
+echo "start compress kernel..."
+
+lzma -c -9 -f -k ${PROJECT_PATH}/${IMAGE_NAME} > ${PROJECT_PATH}/dtb/${BOARD_TYPE}/Image.lzma
+
+mkdir -p ${ROOT_PATH}/output/${BOARD_TYPE}
+./mkimage -f ${PROJECT_PATH}/dtb/${BOARD_TYPE}/multi.its -r ${ROOT_PATH}/output/${BOARD_TYPE}/boot.${STORAGE_TYPE}
+
+if [ "${STORAGE_TYPE}" == "spinor" ] || [ "${STORAGE_TYPE}" == "spinand" ]; then
+
+ check_bootloader || exit 0
+
+ pushd cvitek_bootloader
+
+ . env.sh
+ get_build_board ${BOARD_TYPE}
+
+ CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]')
+
+ echo "board: ${MV_BOARD_LINK}"
+
+ IMGTOOL_PATH=build/tools/common/image_tool
+ FLASH_PARTITION_XML=build/boards/"${CHIP_ARCH_L}"/"${MV_BOARD_LINK}"/partition/partition_"${STORAGE_TYPE}".xml
+ python3 "$IMGTOOL_PATH"/raw2cimg.py "${ROOT_PATH}"/output/"${BOARD_TYPE}"/boot."$STORAGE_TYPE" "${ROOT_PATH}/output/${BOARD_TYPE}" "$FLASH_PARTITION_XML"
+
+ popd
+fi
\ No newline at end of file
diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin
deleted file mode 100755
index 84ea0561c04..00000000000
Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin and /dev/null differ
diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin
deleted file mode 100755
index c9902e4a9e5..00000000000
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin
+++ /dev/null
@@ -1 +0,0 @@
-ᆳ
\ No newline at end of file
diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env
deleted file mode 100755
index cff9e11100b..00000000000
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env
+++ /dev/null
@@ -1,2 +0,0 @@
-MONITOR_RUNADDR=0x0000000080000000
-BLCP_2ND_RUNADDR=0x0000000083f40000
diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin
deleted file mode 100755
index d2dabd68683..00000000000
Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin and /dev/null differ
diff --git a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h b/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h
deleted file mode 100755
index 906c5b0ba6a..00000000000
--- a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __BOARD_MMAP__83494f74__
-#define __BOARD_MMAP__83494f74__
-
-#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */
-#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */
-#define CVIMMAP_BOOTLOGO_ADDR 0x82473000 /* offset 36.44921875MiB */
-#define CVIMMAP_BOOTLOGO_SIZE 0x0 /* 0.0KiB */
-#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000 /* offset 35.0MiB */
-#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00 /* offset 19.9990234375MiB */
-#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */
-#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */
-#define CVIMMAP_DRAM_SIZE 0x4000000 /* 64.0MiB */
-#define CVIMMAP_FREERTOS_ADDR 0x83f40000 /* offset 63.25MiB */
-#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0 /* 0.0KiB */
-#define CVIMMAP_FREERTOS_SIZE 0xc0000 /* 768.0KiB */
-#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000 /* offset 63.25MiB */
-#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000 /* offset 20.0MiB */
-#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000 /* 15.0MiB */
-#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000 /* offset 36.44921875MiB */
-#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0 /* 0.0KiB */
-#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000 /* offset 36.44921875MiB */
-#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */
-#define CVIMMAP_ION_ADDR 0x82473000 /* offset 36.44921875MiB */
-#define CVIMMAP_ION_SIZE 0x1acd000 /* 26.80078125MiB */
-#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000 /* offset 36.44921875MiB */
-#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0 /* 0.0KiB */
-#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */
-#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000 /* 63.25MiB */
-#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */
-#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */
-#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */
-#define CVIMMAP_UIMAG_ADDR 0x81400000 /* offset 20.0MiB */
-#define CVIMMAP_UIMAG_SIZE 0xf00000 /* 15.0MiB */
-
-#endif /* __BOARD_MMAP__83494f74__ */
diff --git a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py b/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py
deleted file mode 100755
index 2c487eda69a..00000000000
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/usr/bin/env python3
-
-import logging
-import struct
-import argparse
-
-CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD
-CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE
-
-CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0
-
-
-def gen_chip_conf(args):
- logging.info("gen_chip_conf")
- regs = [
- (0x0E00000C, 0xA0000001), # ATF_DBG_REG = 0x0E00000C
- (0x0E00000C, 0xA0000002),
- # (CHIP_CONF_CMD_DELAY_MS, 100),
- # (CHIP_CONF_CMD_DELAY_US, 100),
- (CHIP_CONF_SCAN_START_1, 0xFFFFFFFF),
- ]
-
- chip_conf = b"".join(struct.pack("= %r is required" % (PYTHON_MIN_VERSION,))
- sys.exit(-1)
-
-
-try:
- import coloredlogs
-except ImportError:
- coloredlogs = None
-
-try:
- import argcomplete
-except ImportError:
- argcomplete = None
-
-
-LOADER_2ND_MAGIC_ORIG = b"BL33"
-LOADER_2ND_MAGIC_LZMA = b"B3MA"
-LOADER_2ND_MAGIC_LZ4 = b"B3Z4"
-
-LOADER_2ND_MAGIC_LIST = [
- LOADER_2ND_MAGIC_ORIG,
- LOADER_2ND_MAGIC_LZMA,
- LOADER_2ND_MAGIC_LZ4,
-]
-
-IMAGE_ALIGN = 512
-PARAM1_SIZE = 0x1000
-PARAM1_SIZE_WO_SIG = 0x800
-PARAM2_SIZE = 0x1000
-
-
-def round_up(divident, divisor):
- return ((divident + divisor - 1) // divisor) * divisor
-
-
-def lzma_compress(body):
- z = lzma.LZMACompressor(lzma.FORMAT_ALONE, preset=lzma.PRESET_EXTREME)
- compressed = z.compress(body)
- compressed += z.flush()
-
- return compressed
-
-
-def lz4_compress(body):
- try:
- import lz4.frame
- except ImportError:
- logging.error("lz4 is not installed. Run 'pip install lz4'.")
- raise
-
- compressed = lz4.frame.compress(body)
- return compressed
-
-
-class Entry:
- __slots__ = "name", "type", "addr", "_content", "entry_size"
-
- def __init__(self):
- self.addr = None
- self._content = None
-
- @property
- def end(self):
- return self.addr + self.entry_size
-
- @property
- def content(self):
- return self._content
-
- @content.setter
- def content(self, value):
- if type(value) == int:
- value = value.to_bytes(self.entry_size, "little")
-
- if self.entry_size is not None:
- if len(value) > self.entry_size:
- raise ValueError("%s (%d bytes) must <= %#r" % (self.name, len(value), self.entry_size))
- value = value + b"\0" * (self.entry_size - len(value))
-
- self._content = value
-
- @classmethod
- def make(cls, name, entry_size, _type, init=None):
- entry = Entry()
- entry.name = name
- entry.type = _type
- entry.entry_size = entry_size
-
- if type(init) in (bytes, bytearray):
- entry.content = bytes(init)
- elif entry_size is not None:
- entry.content = b"\0" * entry.entry_size
- else:
- entry.content = b""
-
- return (name, entry)
-
- def toint(self):
- if self.type != int:
- raise TypeError("%s is not int type" % self.name)
-
- return int.from_bytes(self.content, "little")
-
- def tostr(self):
- v = self.content
- if self.type == int:
- v = "%#08x" % self.toint()
- elif type(self.content) in [bytes, bytearray]:
- v = v.hex()
- if len(v) > 32:
- v = v[:32] + "..."
-
- return v
-
- def __str__(self):
- v = self.tostr()
- return "<%s=%s (%dbytes)>" % (self.name, v, self.entry_size)
-
- def __repr__(self):
- v = self.tostr()
- return "<%s: a=%#x s=%#x c=%s %r>" % (self.name, self.addr, self.entry_size, v, self.type)
-
-
-class FIP:
- param1 = OrderedDict(
- [
- Entry.make("MAGIC1", 8, int, b"CVBL01\n\0"),
- Entry.make("MAGIC2", 4, int),
- Entry.make("PARAM_CKSUM", 4, int),
- Entry.make("NAND_INFO", 128, int),
- Entry.make("NOR_INFO", 36, int),
- Entry.make("FIP_FLAGS", 8, int),
- Entry.make("CHIP_CONF_SIZE", 4, int),
- Entry.make("BLCP_IMG_CKSUM", 4, int),
- Entry.make("BLCP_IMG_SIZE", 4, int),
- Entry.make("BLCP_IMG_RUNADDR", 4, int),
- Entry.make("BLCP_PARAM_LOADADDR", 4, int),
- Entry.make("BLCP_PARAM_SIZE", 4, int),
- Entry.make("BL2_IMG_CKSUM", 4, int),
- Entry.make("BL2_IMG_SIZE", 4, int),
- Entry.make("BLD_IMG_SIZE", 4, int),
- Entry.make("PARAM2_LOADADDR", 4, int),
- Entry.make("RESERVED1", 4, int),
- Entry.make("CHIP_CONF", 760, bytes),
- Entry.make("BL_EK", 32, bytes),
- Entry.make("ROOT_PK", 512, bytes),
- Entry.make("BL_PK", 512, bytes),
- Entry.make("BL_PK_SIG", 512, bytes),
- Entry.make("CHIP_CONF_SIG", 512, bytes),
- Entry.make("BL2_IMG_SIG", 512, bytes),
- Entry.make("BLCP_IMG_SIG", 512, bytes),
- ]
- )
-
- body1 = OrderedDict(
- [
- Entry.make("BLCP", None, bytes),
- Entry.make("BL2", None, bytes),
- ]
- )
-
- param2 = OrderedDict(
- [
- Entry.make("MAGIC1", 8, int, b"CVLD02\n\0"),
- Entry.make("PARAM2_CKSUM", 4, int),
- Entry.make("RESERVED1", 4, bytes),
- # DDR param
- Entry.make("DDR_PARAM_CKSUM", 4, int),
- Entry.make("DDR_PARAM_LOADADDR", 4, int),
- Entry.make("DDR_PARAM_SIZE", 4, int),
- Entry.make("DDR_PARAM_RESERVED", 4, int),
- # BLCP_2ND
- Entry.make("BLCP_2ND_CKSUM", 4, int),
- Entry.make("BLCP_2ND_LOADADDR", 4, int),
- Entry.make("BLCP_2ND_SIZE", 4, int),
- Entry.make("BLCP_2ND_RUNADDR", 4, int),
- # ATF-BL31 or OpenSBI
- Entry.make("MONITOR_CKSUM", 4, int),
- Entry.make("MONITOR_LOADADDR", 4, int),
- Entry.make("MONITOR_SIZE", 4, int),
- Entry.make("MONITOR_RUNADDR", 4, int),
- # u-boot
- Entry.make("LOADER_2ND_RESERVED0", 4, int),
- Entry.make("LOADER_2ND_LOADADDR", 4, int),
- Entry.make("LOADER_2ND_RESERVED1", 4, int),
- Entry.make("LOADER_2ND_RESERVED2", 4, int),
- # Reserved
- Entry.make("RESERVED_LAST", 4096 - 16 * 5, bytes),
- ]
- )
-
- body2 = OrderedDict(
- [
- Entry.make("DDR_PARAM", None, bytes),
- Entry.make("BLCP_2ND", None, bytes),
- Entry.make("MONITOR", None, bytes),
- Entry.make("LOADER_2ND", None, bytes),
- ]
- )
-
- ldr_2nd_hdr = OrderedDict(
- [
- Entry.make("JUMP0", 4, int),
- Entry.make("MAGIC", 4, int),
- Entry.make("CKSUM", 4, int),
- Entry.make("SIZE", 4, int),
- Entry.make("RUNADDR", 8, int),
- Entry.make("RESERVED1", 4, int),
- Entry.make("RESERVED2", 4, int),
- ]
- )
-
- FIP_FLAGS_SCS_MASK = 0x000c
- FIP_FLAGS_ENCRYPTED_MASK = 0x0030
-
- def _param_size(self, param):
- return max((e.end for e in param.values()))
-
- def _gen_param(self):
- addr = 0
- for entry in self.param1.values():
- entry.addr = addr
- addr += entry.entry_size
-
- assert PARAM1_SIZE_WO_SIG == self.param1["BL_PK_SIG"].addr
-
- addr = 0
- for entry in self.param2.values():
- entry.addr = addr
- addr += entry.entry_size
-
- assert PARAM2_SIZE == self.param2["RESERVED_LAST"].addr + self.param2["RESERVED_LAST"].entry_size
-
- addr = 0
- for entry in self.ldr_2nd_hdr.values():
- entry.addr = addr
- addr += entry.entry_size
-
- def __init__(self):
- self.compress_algo = None
- self._gen_param()
-
- def image_crc(self, image):
- crc = binascii.crc_hqx(image, 0)
- crc = pack("gpio, index->pin, value);
}
-rt_int8_t es32f0_pin_read(rt_device_t dev, rt_base_t pin)
+rt_ssize_t es32f0_pin_read(rt_device_t dev, rt_base_t pin)
{
- rt_int8_t value;
+ rt_ssize_t value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = ald_gpio_read_pin(index->gpio, index->pin);
return value;
diff --git a/bsp/essemi/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx
index b7d8f057d06..c470884e7b2 100644
--- a/bsp/essemi/es32f0654/project.uvprojx
+++ b/bsp/essemi/es32f0654/project.uvprojx
@@ -482,6 +482,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1013,79 +1032,79 @@
Libraries
- ald_calc.c
+ ald_wdt.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c
- ald_gpio.c
+ ald_spi.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c
- utils.c
+ ald_bkpc.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c
- ald_acmp.c
+ ald_gpio.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c
- ald_crc.c
+ ald_rmu.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c
- ald_spi.c
+ ald_smartcard.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c
- ald_tsense.c
+ ald_calc.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c
- ald_can.c
+ ald_rtc.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c
- ald_usart.c
+ ald_acmp.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c
- ald_cmu.c
+ ald_uart.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c
- ald_rmu.c
+ ald_dma.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c
@@ -1097,114 +1116,114 @@
- ald_pis.c
+ ald_tsense.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c
- ald_iap.c
+ ald_can.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c
- ald_timer.c
+ ald_trng.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c
- ald_bkpc.c
+ ald_crc.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c
- ald_flash_ext.c
+ ald_pis.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c
- ald_pmu.c
+ utils.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c
- ald_rtc.c
+ ald_iap.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c
- ald_trng.c
+ ald_crypt.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c
- ald_flash.c
+ ald_timer.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c
- ald_uart.c
+ ald_cmu.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c
- ald_i2c.c
+ ald_flash_ext.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
- ald_adc.c
+ ald_pmu.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c
- ald_dma.c
+ ald_adc.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c
- ald_smartcard.c
+ ald_flash.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c
- ald_wdt.c
+ ald_usart.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c
- ald_crypt.c
+ ald_i2c.c
1
- libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c
+ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c
diff --git a/bsp/essemi/es32f365x/project.ewp b/bsp/essemi/es32f365x/project.ewp
index 97dcfdddee4..9d072964cde 100644
--- a/bsp/essemi/es32f365x/project.ewp
+++ b/bsp/essemi/es32f365x/project.ewp
@@ -2139,6 +2139,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
@@ -2263,109 +2266,109 @@
Libraries
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
$PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
- $PROJ_DIR$\..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
+ $PROJ_DIR$\..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
- $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
+ $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c
diff --git a/bsp/essemi/es32f365x/project.uvprojx b/bsp/essemi/es32f365x/project.uvprojx
index 09222360dc0..74dada4e4eb 100644
--- a/bsp/essemi/es32f365x/project.uvprojx
+++ b/bsp/essemi/es32f365x/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1042,44 +1061,37 @@
Libraries
- ald_tsense.c
- 1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
-
-
-
-
- ald_nor_lcd.c
+ ald_i2s.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
- ald_usb.c
+ ald_ebi.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
- ald_rmu.c
+ ald_iap.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
- ald_calc.c
+ ald_dma.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
- ald_uart.c
+ ald_flash_ext.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
@@ -1091,23 +1103,23 @@
- ald_i2s.c
+ ald_cmu.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
- ald_cmu.c
+ ald_rtc.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
- ald_crypt.c
+ ald_usb.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
@@ -1119,9 +1131,9 @@
- ald_adc.c
+ ald_nor_lcd.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
@@ -1133,16 +1145,16 @@
- ald_qspi.c
+ ald_adc.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
- ald_iap.c
+ ald_flash.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
@@ -1154,44 +1166,51 @@
- ald_sram.c
+ ald_pmu.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
- ald_dac.c
+ ald_rmu.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
- ald_gpio.c
+ ald_acmp.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
- ald_nand.c
+ ald_crypt.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
- ald_timer.c
+ ald_wdt.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
- ald_wdt.c
+ ald_can.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
+
+
+
+
+ ald_spi.c
+ 1
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
@@ -1203,86 +1222,86 @@
- ald_ebi.c
+ ald_timer.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
- ald_flash_ext.c
+ utils.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
- startup_es32f36xx.s
- 2
- ..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s
+ ald_calc.c
+ 1
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c
- utils.c
+ ald_dac.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
- ald_pmu.c
- 1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
+ startup_es32f36xx.s
+ 2
+ ..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s
- ald_dma.c
+ ald_sram.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
- ald_spi.c
+ ald_gpio.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
- ald_acmp.c
+ ald_tsense.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
- ald_flash.c
+ ald_qspi.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
- ald_rtc.c
+ ald_uart.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
- ald_trng.c
+ ald_nand.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
- ald_can.c
+ ald_trng.c
1
- ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
+ ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
diff --git a/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript b/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript
index 25399290275..da85e053c37 100644
--- a/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript
+++ b/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript
@@ -4,6 +4,6 @@ cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
inc = [cwd]
-group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc)
+group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc)
Return('group')
diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c
index ccfae8819b2..f97b89565a5 100644
--- a/bsp/essemi/es32f369x/drivers/drv_gpio.c
+++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c
@@ -247,15 +247,15 @@ void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
ald_gpio_write_pin(index->gpio, index->pin, value);
}
-rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
+rt_ssize_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
{
- rt_int8_t value;
+ rt_ssize_t value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = ald_gpio_read_pin(index->gpio, index->pin);
return value;
diff --git a/bsp/essemi/es32f369x/project.ewp b/bsp/essemi/es32f369x/project.ewp
index 7ec0f7915bf..dad00bfffa8 100644
--- a/bsp/essemi/es32f369x/project.ewp
+++ b/bsp/essemi/es32f369x/project.ewp
@@ -2139,6 +2139,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
@@ -2263,109 +2266,109 @@
Libraries
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
-
-
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c
-
-
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
$PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
$PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
+
+
+ $PROJ_DIR$\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s
$PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
$PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c
- $PROJ_DIR$\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
- $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
+
+
+ $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx
index 18c9a24f739..88578b36b8a 100644
--- a/bsp/essemi/es32f369x/project.uvprojx
+++ b/bsp/essemi/es32f369x/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -1042,23 +1061,23 @@
Libraries
- ald_i2s.c
+ ald_cmu.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
- ald_dac.c
+ ald_spi.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
- ald_i2c.c
+ utils.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
@@ -1070,219 +1089,219 @@
- ald_usb.c
+ ald_acmp.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
- ald_gpio.c
+ ald_crc.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c
- ald_uart.c
+ ald_nand.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
- ald_tsense.c
+ ald_flash.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
- ald_flash_ext.c
+ ald_tsense.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c
- ald_rtc.c
+ ald_gpio.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c
- ald_iap.c
+ ald_sram.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
- ald_rmu.c
+ ald_usb.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c
- ald_adc.c
+ ald_bkpc.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c
- ald_ebi.c
+ ald_flash_ext.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c
- ald_sram.c
+ ald_rtchw.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c
- ald_nand.c
+ ald_adc.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c
- utils.c
+ ald_uart.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c
- ald_can.c
+ ald_i2c.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c
- ald_acmp.c
+ ald_iap.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c
- ald_crypt.c
+ ald_wdt.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
- ald_rtchw.c
+ ald_can.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c
- ald_crc.c
+ ald_rtc.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c
- ald_trng.c
+ ald_nor_lcd.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
- ald_timer.c
+ ald_crypt.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c
- ald_pis.c
+ ald_qspi.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
- ald_cmu.c
+ ald_i2s.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c
- ald_nor_lcd.c
+ ald_pis.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c
- ald_wdt.c
- 1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c
+ startup_es32f36xx.s
+ 2
+ libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s
- startup_es32f36xx.s
- 2
- libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s
+ ald_timer.c
+ 1
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c
- ald_flash.c
+ ald_dma.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
- ald_spi.c
+ ald_pmu.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
- ald_dma.c
+ ald_dac.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c
- ald_qspi.c
+ ald_rmu.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c
- ald_pmu.c
+ ald_ebi.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c
- ald_bkpc.c
+ ald_trng.c
1
- libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c
+ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c
diff --git a/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript b/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript
index 25399290275..da85e053c37 100644
--- a/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript
+++ b/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript
@@ -4,6 +4,6 @@ cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
inc = [cwd]
-group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc)
+group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc)
Return('group')
diff --git a/bsp/essemi/es32vf2264/drivers/drv_gpio.c b/bsp/essemi/es32vf2264/drivers/drv_gpio.c
index dd13df8e094..1d4ca316788 100644
--- a/bsp/essemi/es32vf2264/drivers/drv_gpio.c
+++ b/bsp/essemi/es32vf2264/drivers/drv_gpio.c
@@ -246,7 +246,7 @@ void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
ald_gpio_write_pin(index->gpio, index->pin, value);
}
-rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
+rt_ssize_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
@@ -254,7 +254,7 @@ rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = ald_gpio_read_pin(index->gpio, index->pin);
return value;
@@ -337,7 +337,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
/* pin no. convert to dec no. */
for (irqindex = 0; irqindex < 16; irqindex++)
@@ -349,7 +349,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin,
}
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
@@ -363,7 +363,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin,
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
- return RT_EBUSY;
+ return -RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
@@ -381,7 +381,7 @@ rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
for (irqindex = 0; irqindex < 16; irqindex++)
@@ -393,7 +393,7 @@ rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin)
}
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
@@ -425,7 +425,7 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
@@ -439,13 +439,13 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
@@ -479,14 +479,14 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
/*csi_vic_disable_sirq(irqmap->irqno);*/
}
else
{
- return RT_ENOSYS;
+ return -RT_ENOSYS;
}
return RT_EOK;
}
diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c b/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c
index 9814fc9ff04..c605cc587cc 100644
--- a/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c
@@ -148,11 +148,11 @@ static void fm33_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t fm33_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t fm33_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_Type *gpio_port;
uint16_t gpio_pin;
- rt_int8_t value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
@@ -160,6 +160,10 @@ static rt_int8_t fm33_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_STPIN(pin);
value = FL_GPIO_GetInputPin(gpio_port, gpio_pin);
}
+ else
+ {
+ value = -RT_EINVAL;
+ }
return value;
}
@@ -404,7 +408,7 @@ static rt_err_t fm33_pin_irq_enable(struct rt_device *device, rt_base_t pin,
return RT_EOK;
}
const static struct rt_pin_ops _fm33_pin_ops =
- {
+{
fm33_pin_mode,
fm33_pin_write,
fm33_pin_read,
diff --git a/bsp/fm33lc026/project.uvprojx b/bsp/fm33lc026/project.uvprojx
index b3c9ea738b1..ca1cf579c9e 100644
--- a/bsp/fm33lc026/project.uvprojx
+++ b/bsp/fm33lc026/project.uvprojx
@@ -540,6 +540,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/frdm-k64f/project.uvproj b/bsp/frdm-k64f/project.uvproj
index 35ce81ac79f..2e308623eae 100644
--- a/bsp/frdm-k64f/project.uvproj
+++ b/bsp/frdm-k64f/project.uvproj
@@ -403,16 +403,16 @@
Applications
- application.c
+ startup.c
1
- applications\application.c
+ applications\startup.c
- startup.c
+ application.c
1
- applications\startup.c
+ applications\application.c
@@ -515,6 +515,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/frdm-k64f/project.uvprojx b/bsp/frdm-k64f/project.uvprojx
index 544f9e16975..0005a472890 100644
--- a/bsp/frdm-k64f/project.uvprojx
+++ b/bsp/frdm-k64f/project.uvprojx
@@ -376,16 +376,16 @@
Applications
- startup.c
+ application.c
1
- applications\startup.c
+ applications\application.c
- application.c
+ startup.c
1
- applications\application.c
+ applications\startup.c
@@ -488,6 +488,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/ft2004/drivers/drv_sdctrl.c b/bsp/ft2004/drivers/drv_sdctrl.c
index a1e6740046e..790a38aba06 100644
--- a/bsp/ft2004/drivers/drv_sdctrl.c
+++ b/bsp/ft2004/drivers/drv_sdctrl.c
@@ -598,7 +598,7 @@ int rthw_sdctrl_init(void)
#endif
normalIrqFlgs |= NORMAL_IRQ_CC;
- /* register handler、irq enable bit and wait callback */
+ /* register handler irq enable bit and wait callback */
FSdCtrl_SetHandler(ft_sdctrl_p, FTSDCTRL_CMDIRQID, rthw_sdctrl_nomarl_callback, ft_sdctrl_p);
FSdCtrl_NormalIrqSet(ft_sdctrl_p, normalIrqFlgs);
FSdCtrl_CmdWaitRegister(ft_sdctrl_p, rthw_sdctrl_cmd_wait);
diff --git a/bsp/ft32/ft32f072xb-starter/project.uvprojx b/bsp/ft32/ft32f072xb-starter/project.uvprojx
index 743a721f22d..fdac507ae9a 100644
--- a/bsp/ft32/ft32f072xb-starter/project.uvprojx
+++ b/bsp/ft32/ft32f072xb-starter/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/ft32/libraries/Drivers/drv_gpio.c b/bsp/ft32/libraries/Drivers/drv_gpio.c
index 313da3635ba..479294a3d03 100644
--- a/bsp/ft32/libraries/Drivers/drv_gpio.c
+++ b/bsp/ft32/libraries/Drivers/drv_gpio.c
@@ -135,11 +135,11 @@ static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t ft32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t ft32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
- rt_int8_t value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
@@ -147,6 +147,10 @@ static rt_int8_t ft32_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_FTPIN(pin);
value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
}
+ else
+ {
+ return -RT_EINVAL;
+ }
return value;
}
diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.ewp b/bsp/fujitsu/mb9x/mb9bf506r/project.ewp
index 0df47a10d18..8b3f2c3e6a8 100644
--- a/bsp/fujitsu/mb9x/mb9bf506r/project.ewp
+++ b/bsp/fujitsu/mb9x/mb9bf506r/project.ewp
@@ -160,7 +160,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
__RTTHREAD__
__RT_IPC_SOURCE__
__RT_KERNEL_SOURCE__
@@ -1055,7 +1054,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
__RTTHREAD__
__RT_IPC_SOURCE__
__RT_KERNEL_SOURCE__
@@ -1793,10 +1791,10 @@
Applications
- $PROJ_DIR$\applications\startup.c
+ $PROJ_DIR$\applications\application.c
- $PROJ_DIR$\applications\application.c
+ $PROJ_DIR$\applications\startup.c
@@ -1864,6 +1862,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
@@ -1892,7 +1893,7 @@
Drivers
- $PROJ_DIR$\drivers\board.c
+ $PROJ_DIR$\drivers\fm3_uart.c
$PROJ_DIR$\drivers\nand.c
@@ -1901,7 +1902,7 @@
$PROJ_DIR$\drivers\led.c
- $PROJ_DIR$\drivers\fm3_uart.c
+ $PROJ_DIR$\drivers\board.c
diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj
index 657050fb1b2..fc122185f1f 100644
--- a/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj
+++ b/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj
@@ -384,16 +384,16 @@
Applications
- application.c
+ startup.c
1
- applications\application.c
+ applications\startup.c
- startup.c
+ application.c
1
- applications\startup.c
+ applications\application.c
@@ -513,6 +513,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -670,16 +689,16 @@
Drivers
- nand.c
+ fm3_uart.c
1
- drivers\nand.c
+ drivers\fm3_uart.c
- fm3_uart.c
+ nand.c
1
- drivers\fm3_uart.c
+ drivers\nand.c
diff --git a/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj
index 04b4d710ad1..51f1eac663f 100644
--- a/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj
+++ b/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj
@@ -389,16 +389,16 @@
Applications
- application.c
+ startup.c
1
- applications\application.c
+ applications\startup.c
- startup.c
+ application.c
1
- applications\startup.c
+ applications\application.c
@@ -518,6 +518,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -675,16 +694,16 @@
Drivers
- board.c
+ drivers_serial.c
1
- drivers\board.c
+ drivers\serial.c
- drivers_serial.c
+ board.c
1
- drivers\serial.c
+ drivers\board.c
diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.ewp b/bsp/fujitsu/mb9x/mb9bf618s/project.ewp
index 09bcbb10b64..3df37141902 100644
--- a/bsp/fujitsu/mb9x/mb9bf618s/project.ewp
+++ b/bsp/fujitsu/mb9x/mb9bf618s/project.ewp
@@ -169,7 +169,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
__RTTHREAD__
__RT_IPC_SOURCE__
__RT_KERNEL_SOURCE__
@@ -1114,7 +1113,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
__RTTHREAD__
__RT_IPC_SOURCE__
__RT_KERNEL_SOURCE__
@@ -1893,10 +1891,10 @@
Applications
- $PROJ_DIR$\applications\application.c
+ $PROJ_DIR$\applications\startup.c
- $PROJ_DIR$\applications\startup.c
+ $PROJ_DIR$\applications\application.c
@@ -1964,6 +1962,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
@@ -1992,10 +1993,10 @@
Drivers
- $PROJ_DIR$\drivers\board.c
+ $PROJ_DIR$\drivers\serial.c
- $PROJ_DIR$\drivers\serial.c
+ $PROJ_DIR$\drivers\board.c
$PROJ_DIR$\drivers\led.c
diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj b/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj
index 33073d6d364..3b7f3b495d6 100644
--- a/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj
+++ b/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj
@@ -390,16 +390,16 @@
Applications
- startup.c
+ application.c
1
- applications\startup.c
+ applications\application.c
- application.c
+ startup.c
1
- applications\application.c
+ applications\startup.c
@@ -519,6 +519,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
@@ -676,16 +695,16 @@
Drivers
- board.c
+ drivers_serial.c
1
- drivers\board.c
+ drivers\serial.c
- drivers_serial.c
+ board.c
1
- drivers\serial.c
+ drivers\board.c
diff --git a/bsp/gd32/arm/gd32103c-eval/project.ewp b/bsp/gd32/arm/gd32103c-eval/project.ewp
index 53e5aafe1d4..a20b8c3cb1b 100644
--- a/bsp/gd32/arm/gd32103c-eval/project.ewp
+++ b/bsp/gd32/arm/gd32103c-eval/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32103c-eval/project.uvproj b/bsp/gd32/arm/gd32103c-eval/project.uvproj
index e41dbda2ab0..80fdf64e8ef 100644
--- a/bsp/gd32/arm/gd32103c-eval/project.uvproj
+++ b/bsp/gd32/arm/gd32103c-eval/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32103c-eval/project.uvprojx b/bsp/gd32/arm/gd32103c-eval/project.uvprojx
index b6bae9cc0f6..09bd371cda2 100644
--- a/bsp/gd32/arm/gd32103c-eval/project.uvprojx
+++ b/bsp/gd32/arm/gd32103c-eval/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32105c-eval/project.ewp b/bsp/gd32/arm/gd32105c-eval/project.ewp
index 36e2e83cdc1..20a64d171d0 100644
--- a/bsp/gd32/arm/gd32105c-eval/project.ewp
+++ b/bsp/gd32/arm/gd32105c-eval/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32105c-eval/project.uvproj b/bsp/gd32/arm/gd32105c-eval/project.uvproj
index f08109dcc9f..332c620e0a7 100644
--- a/bsp/gd32/arm/gd32105c-eval/project.uvproj
+++ b/bsp/gd32/arm/gd32105c-eval/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32105c-eval/project.uvprojx b/bsp/gd32/arm/gd32105c-eval/project.uvprojx
index b0197bf684b..555014206bb 100644
--- a/bsp/gd32/arm/gd32105c-eval/project.uvprojx
+++ b/bsp/gd32/arm/gd32105c-eval/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32105r-start/project.ewp b/bsp/gd32/arm/gd32105r-start/project.ewp
index 36e2e83cdc1..20a64d171d0 100644
--- a/bsp/gd32/arm/gd32105r-start/project.ewp
+++ b/bsp/gd32/arm/gd32105r-start/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32105r-start/project.uvproj b/bsp/gd32/arm/gd32105r-start/project.uvproj
index ade82c59b93..ccd25ff36c4 100644
--- a/bsp/gd32/arm/gd32105r-start/project.uvproj
+++ b/bsp/gd32/arm/gd32105r-start/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32105r-start/project.uvprojx b/bsp/gd32/arm/gd32105r-start/project.uvprojx
index 2e6e66a9fae..067b8f86cc7 100644
--- a/bsp/gd32/arm/gd32105r-start/project.uvprojx
+++ b/bsp/gd32/arm/gd32105r-start/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32107c-eval/project.ewp b/bsp/gd32/arm/gd32107c-eval/project.ewp
index e672e9066ea..55603b88131 100644
--- a/bsp/gd32/arm/gd32107c-eval/project.ewp
+++ b/bsp/gd32/arm/gd32107c-eval/project.ewp
@@ -2002,6 +2002,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32107c-eval/project.uvproj b/bsp/gd32/arm/gd32107c-eval/project.uvproj
index 0f6f7e5778d..24e2eaa84c0 100644
--- a/bsp/gd32/arm/gd32107c-eval/project.uvproj
+++ b/bsp/gd32/arm/gd32107c-eval/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32107c-eval/project.uvprojx b/bsp/gd32/arm/gd32107c-eval/project.uvprojx
index fdf48522c40..961a4b6cab8 100644
--- a/bsp/gd32/arm/gd32107c-eval/project.uvprojx
+++ b/bsp/gd32/arm/gd32107c-eval/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32205r-start/project.ewp b/bsp/gd32/arm/gd32205r-start/project.ewp
index 76cc47110b6..257bb46147b 100644
--- a/bsp/gd32/arm/gd32205r-start/project.ewp
+++ b/bsp/gd32/arm/gd32205r-start/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32205r-start/project.uvproj b/bsp/gd32/arm/gd32205r-start/project.uvproj
index e8bbe3002de..105815afea9 100644
--- a/bsp/gd32/arm/gd32205r-start/project.uvproj
+++ b/bsp/gd32/arm/gd32205r-start/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32205r-start/project.uvprojx b/bsp/gd32/arm/gd32205r-start/project.uvprojx
index 9e9015ac9d5..93b7b8405e9 100644
--- a/bsp/gd32/arm/gd32205r-start/project.uvprojx
+++ b/bsp/gd32/arm/gd32205r-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32207i-eval/project.ewp b/bsp/gd32/arm/gd32207i-eval/project.ewp
index 1fbfff0e7d7..7420926346f 100644
--- a/bsp/gd32/arm/gd32207i-eval/project.ewp
+++ b/bsp/gd32/arm/gd32207i-eval/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32207i-eval/project.uvproj b/bsp/gd32/arm/gd32207i-eval/project.uvproj
index bede91dbe92..c42f132e72b 100644
--- a/bsp/gd32/arm/gd32207i-eval/project.uvproj
+++ b/bsp/gd32/arm/gd32207i-eval/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32207i-eval/project.uvprojx b/bsp/gd32/arm/gd32207i-eval/project.uvprojx
index b4cb73b045e..e473780cddc 100644
--- a/bsp/gd32/arm/gd32207i-eval/project.uvprojx
+++ b/bsp/gd32/arm/gd32207i-eval/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32303c-start/project.ewp b/bsp/gd32/arm/gd32303c-start/project.ewp
index db39b2d9795..22f39057252 100644
--- a/bsp/gd32/arm/gd32303c-start/project.ewp
+++ b/bsp/gd32/arm/gd32303c-start/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32303c-start/project.uvproj b/bsp/gd32/arm/gd32303c-start/project.uvproj
index fef03e271f9..ccac00429e0 100644
--- a/bsp/gd32/arm/gd32303c-start/project.uvproj
+++ b/bsp/gd32/arm/gd32303c-start/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32303c-start/project.uvprojx b/bsp/gd32/arm/gd32303c-start/project.uvprojx
index d7b1a1b6b34..65e9c03ae5a 100644
--- a/bsp/gd32/arm/gd32303c-start/project.uvprojx
+++ b/bsp/gd32/arm/gd32303c-start/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32303e-eval/project.ewp b/bsp/gd32/arm/gd32303e-eval/project.ewp
index 31412725f7e..6b5e92f4117 100644
--- a/bsp/gd32/arm/gd32303e-eval/project.ewp
+++ b/bsp/gd32/arm/gd32303e-eval/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32303e-eval/project.uvproj b/bsp/gd32/arm/gd32303e-eval/project.uvproj
index 3b8c5fb4299..de25cc74618 100644
--- a/bsp/gd32/arm/gd32303e-eval/project.uvproj
+++ b/bsp/gd32/arm/gd32303e-eval/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32303e-eval/project.uvprojx b/bsp/gd32/arm/gd32303e-eval/project.uvprojx
index f9663a8fc48..58634d41f2b 100644
--- a/bsp/gd32/arm/gd32303e-eval/project.uvprojx
+++ b/bsp/gd32/arm/gd32303e-eval/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32305r-start/project.ewp b/bsp/gd32/arm/gd32305r-start/project.ewp
index 83d035a6d08..a86704604ac 100644
--- a/bsp/gd32/arm/gd32305r-start/project.ewp
+++ b/bsp/gd32/arm/gd32305r-start/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32305r-start/project.uvproj b/bsp/gd32/arm/gd32305r-start/project.uvproj
index 1f6eae713e8..b8d8efa6f59 100644
--- a/bsp/gd32/arm/gd32305r-start/project.uvproj
+++ b/bsp/gd32/arm/gd32305r-start/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32305r-start/project.uvprojx b/bsp/gd32/arm/gd32305r-start/project.uvprojx
index 08e1a0ad786..a3c0ff864ad 100644
--- a/bsp/gd32/arm/gd32305r-start/project.uvprojx
+++ b/bsp/gd32/arm/gd32305r-start/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32307e-start/project.ewp b/bsp/gd32/arm/gd32307e-start/project.ewp
index f2d83dff77a..64b85d5aaeb 100644
--- a/bsp/gd32/arm/gd32307e-start/project.ewp
+++ b/bsp/gd32/arm/gd32307e-start/project.ewp
@@ -2000,6 +2000,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32307e-start/project.uvproj b/bsp/gd32/arm/gd32307e-start/project.uvproj
index 1cb61c626d1..fbf506b22c5 100644
--- a/bsp/gd32/arm/gd32307e-start/project.uvproj
+++ b/bsp/gd32/arm/gd32307e-start/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32307e-start/project.uvprojx b/bsp/gd32/arm/gd32307e-start/project.uvprojx
index d760043058e..8c12cf9fe8d 100644
--- a/bsp/gd32/arm/gd32307e-start/project.uvprojx
+++ b/bsp/gd32/arm/gd32307e-start/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32407v-lckfb/project.ewp b/bsp/gd32/arm/gd32407v-lckfb/project.ewp
index fa29f6db364..882eefbafc5 100644
--- a/bsp/gd32/arm/gd32407v-lckfb/project.ewp
+++ b/bsp/gd32/arm/gd32407v-lckfb/project.ewp
@@ -2011,6 +2011,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32407v-lckfb/project.uvproj b/bsp/gd32/arm/gd32407v-lckfb/project.uvproj
index 06551351bc0..aaf64e82960 100644
--- a/bsp/gd32/arm/gd32407v-lckfb/project.uvproj
+++ b/bsp/gd32/arm/gd32407v-lckfb/project.uvproj
@@ -579,6 +579,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx b/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx
index 619c202cc43..6fae9ed9b66 100644
--- a/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx
+++ b/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx
@@ -544,6 +544,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32407v-start/project.ewp b/bsp/gd32/arm/gd32407v-start/project.ewp
index 55ba9a078aa..a9a281084b9 100644
--- a/bsp/gd32/arm/gd32407v-start/project.ewp
+++ b/bsp/gd32/arm/gd32407v-start/project.ewp
@@ -2009,6 +2009,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32407v-start/project.uvproj b/bsp/gd32/arm/gd32407v-start/project.uvproj
index b77f3790b44..6584c25cbed 100644
--- a/bsp/gd32/arm/gd32407v-start/project.uvproj
+++ b/bsp/gd32/arm/gd32407v-start/project.uvproj
@@ -579,6 +579,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32407v-start/project.uvprojx b/bsp/gd32/arm/gd32407v-start/project.uvprojx
index a1cdc9f04d7..68242775d1a 100644
--- a/bsp/gd32/arm/gd32407v-start/project.uvprojx
+++ b/bsp/gd32/arm/gd32407v-start/project.uvprojx
@@ -543,6 +543,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32450z-eval/project.ewp b/bsp/gd32/arm/gd32450z-eval/project.ewp
index 7c478c22e18..f15047fea18 100644
--- a/bsp/gd32/arm/gd32450z-eval/project.ewp
+++ b/bsp/gd32/arm/gd32450z-eval/project.ewp
@@ -173,7 +173,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
GD32F450
__RTTHREAD__
USE_STDPERIPH_DRIVER
@@ -1145,7 +1144,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
GD32F450
__RTTHREAD__
USE_STDPERIPH_DRIVER
@@ -2008,6 +2006,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32450z-eval/project.uvproj b/bsp/gd32/arm/gd32450z-eval/project.uvproj
index e79fd593ab7..58ee4991df1 100644
--- a/bsp/gd32/arm/gd32450z-eval/project.uvproj
+++ b/bsp/gd32/arm/gd32450z-eval/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32450z-eval/project.uvprojx b/bsp/gd32/arm/gd32450z-eval/project.uvprojx
index 12f729f5360..7e9447d6292 100644
--- a/bsp/gd32/arm/gd32450z-eval/project.uvprojx
+++ b/bsp/gd32/arm/gd32450z-eval/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.ewp b/bsp/gd32/arm/gd32470z-lckfb/project.ewp
index 97e405f77f1..a8c8ec3bcce 100644
--- a/bsp/gd32/arm/gd32470z-lckfb/project.ewp
+++ b/bsp/gd32/arm/gd32470z-lckfb/project.ewp
@@ -173,7 +173,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
GD32F470
__RTTHREAD__
USE_STDPERIPH_DRIVER
@@ -1145,7 +1144,6 @@
RT_USING_LIBC
_DLIB_ADD_EXTRA_SYMBOLS=0
_DLIB_FILE_DESCRIPTOR
- _DLIB_THREAD_SUPPORT
GD32F470
__RTTHREAD__
USE_STDPERIPH_DRIVER
@@ -2008,6 +2006,9 @@
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvproj b/bsp/gd32/arm/gd32470z-lckfb/project.uvproj
index 155b0e22a4e..d743b1d0ad1 100644
--- a/bsp/gd32/arm/gd32470z-lckfb/project.uvproj
+++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvproj
@@ -522,6 +522,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx b/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx
index aa9874df061..f90e584c925 100644
--- a/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx
+++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx
@@ -485,6 +485,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h
index 65c3dbf81e3..49853ad6f07 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -170,7 +170,7 @@ typedef struct _usb_class_core
uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */
uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */
- uint8_t (*ctlx_out) (usb_dev *udev);
+ uint8_t (*ctlx_out) (usb_dev *udev);
uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */
uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */
@@ -295,9 +295,9 @@ typedef struct _usb_core_driver
__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs)
{
uint32_t reg_data = usb_regs->gr->GINTEN;
-
+
reg_data &= usb_regs->gr->GINTF;
-
+
return reg_data;
}
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h
index c187e8693f7..ef47066a494 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -132,7 +132,7 @@ __STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev)
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
-
+
return value & DAEPINT_IEPITB;
}
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h
index 53c5183eefa..b6e54f08fbd 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h
index ff65e2bd9cb..cb06f0b3d44 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h
index ae93df81852..be75a1ef2fe 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h
index eb79e15d275..6ec3ec07f5f 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h
index 99a606dad72..0944614771c 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c
index ba9ee199b25..2d99cc78f1e 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -41,15 +41,15 @@ OF SUCH DAMAGE.
static void usb_core_reset (usb_core_regs *usb_regs);
/*!
- \brief configure USB core basic
+ \brief configure USB core basic
\param[in] usb_basic: pointer to USB capabilities
\param[in] usb_regs: USB core registers
\param[in] usb_core: USB core
\param[out] none
\retval operation status
*/
-usb_status usb_basic_init (usb_core_basic *usb_basic,
- usb_core_regs *usb_regs,
+usb_status usb_basic_init (usb_core_basic *usb_basic,
+ usb_core_regs *usb_regs,
usb_core_enum usb_core)
{
/* configure USB default transfer mode as FIFO mode */
@@ -142,7 +142,7 @@ usb_status usb_basic_init (usb_core_basic *usb_basic,
}
/*!
- \brief initializes the USB controller registers and
+ \brief initializes the USB controller registers and
prepares the core device mode or host mode operation
\param[in] usb_basic: pointer to USB capabilities
\param[in] usb_regs: pointer to USB core registers
@@ -222,9 +222,9 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
\param[out] none
\retval operation status
*/
-usb_status usb_txfifo_write (usb_core_regs *usb_regs,
- uint8_t *src_buf,
- uint8_t fifo_num,
+usb_status usb_txfifo_write (usb_core_regs *usb_regs,
+ uint8_t *src_buf,
+ uint8_t fifo_num,
uint16_t byte_count)
{
uint32_t word_count = (byte_count + 3U) / 4U;
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c
index 11bfab7e582..f7059516d18 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -49,7 +49,7 @@ static const uint8_t EP0_MAXLEN[4] = {
#ifdef USB_FS_CORE
/* USB endpoint Tx FIFO size */
-static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] =
+static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] =
{
(uint16_t)TX0_FIFO_FS_SIZE,
(uint16_t)TX1_FIFO_FS_SIZE,
@@ -61,7 +61,7 @@ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] =
#ifdef USB_HS_CORE
-uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] =
+uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] =
{
(uint16_t)TX0_FIFO_HS_SIZE,
(uint16_t)TX1_FIFO_HS_SIZE,
@@ -215,7 +215,7 @@ usb_status usb_devint_enable (usb_core_driver *udev)
usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc)
{
__IO uint32_t *reg_addr = NULL;
-
+
uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
/* get the endpoint number */
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c
index ab82a5ff035..a3e8d213070 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -61,7 +61,7 @@ usb_status usb_host_init (usb_core_driver *udev)
/* initialize host configuration register */
if (USB_ULPI_PHY == udev->bp.phy_itf) {
- usb_phyclock_config (udev, HCTL_30_60MHZ);
+ usb_phyclock_config (udev, HCTL_30_60MHZ);
} else {
usb_phyclock_config (udev, HCTL_48MHZ);
}
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c
index f22e79507e4..794102a67e3 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c
index b4358ea9bcf..9a161e8f655 100644
--- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c
+++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c
@@ -10,27 +10,27 @@
/*
Copyright (c) 2022, GigaDevice Semiconductor Inc.
- Redistribution and use in source and binary forms, with or without modification,
+ Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
- 1. Redistributions of source code must retain the above copyright notice, this
+ 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
specific prior written permission.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -40,7 +40,7 @@ OF SUCH DAMAGE.
#pragma O0
#elif defined (__GNUC__) /*!< GNU compiler */
#pragma GCC optimize ("O0")
-#elif defined (__TASKING__) /*!< TASKING compiler */
+#elif defined (__TASKING__) /*!< TASKING compiler */
#pragma optimize=0
#endif /* __CC_ARM */
@@ -137,8 +137,8 @@ uint32_t usbh_isr (usb_core_driver *udev)
\param[out] none
\retval none
*/
-static inline void usb_pp_halt (usb_core_driver *udev,
- uint8_t pp_num,
+static inline void usb_pp_halt (usb_core_driver *udev,
+ uint8_t pp_num,
uint32_t pp_int,
usb_pipe_staus pp_status)
{
@@ -460,7 +460,7 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num)
pp->urb_state = URB_DONE;
if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) {
- pp->data_toggle_out ^= 1U;
+ pp->data_toggle_out ^= 1U;
}
break;
@@ -530,7 +530,7 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev)
/* manage multiple transfer packet */
udev->host.pipe[pp_num].xfer_buf += count;
udev->host.pipe[pp_num].xfer_count += count;
-
+
xfer_count = udev->host.pipe[pp_num].xfer_count;
udev->host.backup_xfercount[pp_num] = xfer_count;
diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c
index 5503f3c51ac..9bad48c034d 100644
--- a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c
+++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c
@@ -362,15 +362,15 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
* @param dev, pin
* @retval None
*/
-static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
{
- rt_int8_t value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
const struct pin_index *index = RT_NULL;
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = gpio_input_bit_get(index->gpio_periph, index->pin);
diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c
index 56d4f0ffe22..5daf2421cdc 100644
--- a/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c
+++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
- * Date Author Notes
- * 2023-06-05 zengjianwei first version
+ * Date Author Notes
+ * 2023-06-05 zengjianwei first version
*/
#include
diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c
index d7d408ac1dc..813c0b6a4ad 100644
--- a/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c
+++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c
@@ -19,7 +19,7 @@
#define LOG_TAG "drv.sdio"
#include "drv_log.h"
-#define SDIO_DMA_USE_IPC 0//1:ʹipcͬ
+#define SDIO_DMA_USE_IPC 0//1:使用ipc做同步
/* card status of R1 definitions */
#define SD_R1_OUT_OF_RANGE BIT(31) /* command's argument was out of the allowed range */
diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c
index b89813a926c..1fdaf3a715f 100644
--- a/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c
+++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c
@@ -34,7 +34,7 @@ static int rt_hw_spi_flash_init(void)
static struct gd32_spi_cs spi_cs;
spi_cs.GPIOx = GD25Q_SPI_CS_GPIOX;
spi_cs.GPIO_Pin = GD25Q_SPI_CS_GPIOX_PIN_X;
-
+
rcu_periph_clock_enable(GD25Q_SPI_CS_GPIOX_CLK);
#if defined SOC_SERIES_GD32F4xx
gpio_mode_set(spi_cs.GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, spi_cs.GPIO_Pin);
diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c
index b159661d11b..8d3df301d42 100644
--- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c
+++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c
@@ -248,15 +248,15 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
* @param dev, pin
* @retval None
*/
-static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
{
- rt_int8_t value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
const struct pin_index *index = RT_NULL;
index = get_pin(pin);
if (index == RT_NULL)
{
- return value;
+ return -RT_EINVAL;
}
value = gpio_input_bit_get(index->gpio_periph, index->pin);
diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.ewp b/bsp/hc32/ev_hc32f448_lqfp80/project.ewp
index cc954d45f22..731b4c16f5a 100644
--- a/bsp/hc32/ev_hc32f448_lqfp80/project.ewp
+++ b/bsp/hc32/ev_hc32f448_lqfp80/project.ewp
@@ -1985,10 +1985,10 @@
Applications
- $PROJ_DIR$\applications\xtal32_fcm.c
+ $PROJ_DIR$\applications\main.c
- $PROJ_DIR$\applications\main.c
+ $PROJ_DIR$\applications\xtal32_fcm.c
@@ -2047,6 +2047,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx
index 5c29eb30e62..468e2b9b847 100644
--- a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx
+++ b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx
@@ -493,6 +493,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp
index 848445c20d1..ab4e14eb479 100644
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp
@@ -2049,6 +2049,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx
index 8d7ac58443b..b16a88e6f1f 100644
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx
@@ -493,6 +493,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp
index 3c24caf09d6..a7aca336fb4 100644
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp
@@ -1987,10 +1987,10 @@
Applications
- $PROJ_DIR$\applications\main.c
+ $PROJ_DIR$\applications\xtal32_fcm.c
- $PROJ_DIR$\applications\xtal32_fcm.c
+ $PROJ_DIR$\applications\main.c
@@ -2049,6 +2049,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx
index 30c1ebb4132..ecdf0a4ff0a 100644
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx
@@ -493,6 +493,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c
index 29c2f57e479..6758436c0d3 100644
--- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c
+++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c
@@ -283,7 +283,7 @@ static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t v
}
}
-static rt_int8_t hc32_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_ssize_t hc32_pin_read(struct rt_device *device, rt_base_t pin)
{
uint8_t gpio_port;
uint16_t gpio_pin;
@@ -302,6 +302,10 @@ static rt_int8_t hc32_pin_read(struct rt_device *device, rt_base_t pin)
value = PIN_HIGH;
}
}
+ else
+ {
+ return -RT_EINVAL;
+ }
return value;
}
diff --git a/bsp/hc32l136/drivers/drv_gpio.c b/bsp/hc32l136/drivers/drv_gpio.c
index b76673da011..3407c0b98a1 100644
--- a/bsp/hc32l136/drivers/drv_gpio.c
+++ b/bsp/hc32l136/drivers/drv_gpio.c
@@ -145,11 +145,11 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin)
{
uint8_t gpio_port;
uint16_t gpio_pin;
- rt_int8_t value = PIN_LOW;
+ rt_ssize_t value = PIN_LOW;
if (pin < PIN_MAX_NUM)
{
@@ -164,6 +164,10 @@ static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
value = PIN_HIGH;
}
}
+ else
+ {
+ value = -RT_EINVAL;
+ }
return value;
}
diff --git a/bsp/hc32l136/drivers/drv_usart.c b/bsp/hc32l136/drivers/drv_usart.c
index d5904a63d6c..0e5967dad09 100644
--- a/bsp/hc32l136/drivers/drv_usart.c
+++ b/bsp/hc32l136/drivers/drv_usart.c
@@ -270,7 +270,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial,
stcBaud.u32Baud = cfg->baud_rate;
u16Scnt = Uart_CalScnt(uart->config->idx, &stcBaud);
Uart_SetBaud(uart->config->idx, u16Scnt);
-
+
Uart_ClrStatus(uart->config->idx, UartTC);
Uart_ClrStatus(uart->config->idx, UartRC);
Uart_DisableIrq(uart->config->idx, UartTxIrq);
@@ -315,7 +315,7 @@ static int hc32_putc(struct rt_serial_device *serial, char c)
RT_ASSERT(RT_NULL != serial);
uart = rt_container_of(serial, struct hc32_uart, serial);
-
+
if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
{
if (Uart_GetStatus(uart->config->idx, UartTC) == FALSE)
diff --git a/bsp/hc32l136/drivers/drv_usart.h b/bsp/hc32l136/drivers/drv_usart.h
index a948bde5d34..ca542de27a8 100644
--- a/bsp/hc32l136/drivers/drv_usart.h
+++ b/bsp/hc32l136/drivers/drv_usart.h
@@ -7,7 +7,7 @@
* Date Author Notes
* 2021-08-19 pjq first version
*/
-
+
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
diff --git a/bsp/hc32l136/project.ewp b/bsp/hc32l136/project.ewp
index 33143a4d89d..2e9c27cbd33 100644
--- a/bsp/hc32l136/project.ewp
+++ b/bsp/hc32l136/project.ewp
@@ -2046,6 +2046,9 @@
$PROJ_DIR$\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/hc32l136/project.uvprojx b/bsp/hc32l136/project.uvprojx
index e71f8ce8ab0..a0d61aba4d0 100644
--- a/bsp/hc32l136/project.uvprojx
+++ b/bsp/hc32l136/project.uvprojx
@@ -486,6 +486,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hc32l196/drivers/drv_gpio.c b/bsp/hc32l196/drivers/drv_gpio.c
index b35b13ebea7..ab007a5868e 100644
--- a/bsp/hc32l196/drivers/drv_gpio.c
+++ b/bsp/hc32l196/drivers/drv_gpio.c
@@ -103,14 +103,14 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
}
}
-static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin)
{
en_gpio_port_t gpio_port;
en_gpio_pin_t gpio_pin;
if (pin >= PIN_MAX_NUM)
{
- return PIN_LOW;
+ return -RT_EINVAL;
}
gpio_port = GPIO_PORT(pin);
diff --git a/bsp/hc32l196/project.uvprojx b/bsp/hc32l196/project.uvprojx
index 12374cae697..935fd51ede5 100644
--- a/bsp/hc32l196/project.uvprojx
+++ b/bsp/hc32l196/project.uvprojx
@@ -478,6 +478,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hk32/hk32f030c8-mini/project.ewp b/bsp/hk32/hk32f030c8-mini/project.ewp
index 0c21e7abba0..1309324c597 100644
--- a/bsp/hk32/hk32f030c8-mini/project.ewp
+++ b/bsp/hk32/hk32f030c8-mini/project.ewp
@@ -2165,6 +2165,9 @@
$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c
+
+ $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c
+
$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c
diff --git a/bsp/hk32/hk32f030c8-mini/project.uvproj b/bsp/hk32/hk32f030c8-mini/project.uvproj
index e4d6eba2625..7fb1ea13a75 100644
--- a/bsp/hk32/hk32f030c8-mini/project.uvproj
+++ b/bsp/hk32/hk32f030c8-mini/project.uvproj
@@ -565,6 +565,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hk32/hk32f030c8-mini/project.uvprojx b/bsp/hk32/hk32f030c8-mini/project.uvprojx
index 1191fed6025..d3a508303d0 100644
--- a/bsp/hk32/hk32f030c8-mini/project.uvprojx
+++ b/bsp/hk32/hk32f030c8-mini/project.uvprojx
@@ -543,6 +543,25 @@
+
+
+ condvar.c
+ 1
+ ..\..\..\components\drivers\ipc\condvar.c
+
+
+
+
+
+ __RT_IPC_SOURCE__
+
+
+
+
+
+
+
+
dataqueue.c
diff --git a/bsp/hk32/libraries/rt_drivers/drv_gpio.c b/bsp/hk32/libraries/rt_drivers/drv_gpio.c
index f5a7de8fd68..bc59b76aa4f 100644
--- a/bsp/hk32/libraries/rt_drivers/drv_gpio.c
+++ b/bsp/hk32/libraries/rt_drivers/drv_gpio.c
@@ -120,6 +120,11 @@ static rt_int8_t hk32_pin_read(rt_device_t dev, rt_base_t pin)
gpio_pin = PIN_HKPIN(pin);
value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
}
+ else
+ {
+ return -RT_ENOSYS;
+ }
+
return value;
}
diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c
index 887d3a59130..6877fa607af 100644
--- a/bsp/hpmicro/libraries/drivers/drv_gpio.c
+++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c
@@ -217,13 +217,13 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
}
-static rt_int8_t hpm_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_ssize_t hpm_pin_read(rt_device_t dev, rt_base_t pin)
{
/* TODO: Check the validity of the pin value */
uint32_t gpio_idx = pin >> 5;
uint32_t pin_idx = pin & 0x1FU;
- return (int) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx);
+ return (rt_ssize_t) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx);
}
static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
@@ -310,13 +310,15 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u
return RT_EOK;
}
-const static struct rt_pin_ops hpm_pin_ops = {
- .pin_mode = hpm_pin_mode,
- .pin_write = hpm_pin_write,
- .pin_read = hpm_pin_read,
- .pin_attach_irq = hpm_pin_attach_irq,
- .pin_detach_irq = hpm_pin_detach_irq,
- .pin_irq_enable = hpm_pin_irq_enable};
+const static struct rt_pin_ops hpm_pin_ops =
+{
+ .pin_mode = hpm_pin_mode,
+ .pin_write = hpm_pin_write,
+ .pin_read = hpm_pin_read,
+ .pin_attach_irq = hpm_pin_attach_irq,
+ .pin_detach_irq = hpm_pin_detach_irq,
+ .pin_irq_enable = hpm_pin_irq_enable
+};
int rt_hw_pin_init(void)
{
diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.h b/bsp/hpmicro/libraries/drivers/drv_uart.h
index 4c4a67db821..b316d47ea40 100644
--- a/bsp/hpmicro/libraries/drivers/drv_uart.h
+++ b/bsp/hpmicro/libraries/drivers/drv_uart.h
@@ -11,4 +11,4 @@ int rt_hw_uart_init(void);
-#endif /* DRV_UART_H */
\ No newline at end of file
+#endif /* DRV_UART_H */
diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c
index 5cf2274d0f6..63540a886d5 100644
--- a/bsp/hpmicro/libraries/drivers/drv_wdt.c
+++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c
@@ -246,4 +246,4 @@ int rt_hw_wdt_init(void)
}
INIT_BOARD_EXPORT(rt_hw_wdt_init);
-#endif /* RT_USING_WDT */
\ No newline at end of file
+#endif /* RT_USING_WDT */
diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.h b/bsp/hpmicro/libraries/drivers/drv_wdt.h
index 4c69255af0f..100ffc27dd8 100644
--- a/bsp/hpmicro/libraries/drivers/drv_wdt.h
+++ b/bsp/hpmicro/libraries/drivers/drv_wdt.h
@@ -11,4 +11,4 @@
int rt_hw_wdt_init(void);
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/ht32/ht32f12366/.config b/bsp/ht32/ht32f12366/.config
new file mode 100644
index 00000000000..033557c8562
--- /dev/null
+++ b/bsp/ht32/ht32f12366/.config
@@ -0,0 +1,1093 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="usart0"
+CONFIG_RT_VER_NUM=0x50100
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# CONFIG_RT_USING_CACHE is not set
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M3=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_SOFT_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_BITOPS is not set
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_FAMILY_HT32=y
+CONFIG_SOC_SERIES_HT32F1=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HT32F12366=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_USART0=y
+# CONFIG_BSP_USING_USART1 is not set
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/ht32/ht32f12366/Kconfig b/bsp/ht32/ht32f12366/Kconfig
new file mode 100644
index 00000000000..7a400db91f4
--- /dev/null
+++ b/bsp/ht32/ht32f12366/Kconfig
@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
+
diff --git a/bsp/ht32/ht32f12366/README.md b/bsp/ht32/ht32f12366/README.md
new file mode 100644
index 00000000000..04de7527d74
--- /dev/null
+++ b/bsp/ht32/ht32f12366/README.md
@@ -0,0 +1,107 @@
+# HT32F12366 BSP 说明
+
+## 简介
+
+ESK32-30105是合泰基于HT32F12366芯片并针对Cortex®-M3入门而设计的评估板。本文档是为ESK32-30105开发板提供的BSP(板级支持包)说明。
+
+主要内容如下:
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP,将 RT-Thread 运行在开发板上。
+
+## 开发板介绍
+
+ESK32-30105使用32位ARM® Cortex®-M3高性能、低功耗单片机HT32F12366,针对Cortex®-M3入门而设计。开发板外观如下图所示:
+
+![board.png](figures/board.png)
+
+该开发板常用 **板载资源** 如下:
+
+- MCU:HT32F12366,主频 96MHz,256KB FLASH ,128KB SRAM
+- 常用外设
+ - LED:2个,(绿色,PE0、PD15)
+- 常用接口:USB 转串口 、USB SLAVE
+- 调试接口:板载的 e-Link32 Lite SWD 下载
+
+开发板更多详细信息请参考合泰官网的相关文档 [ESK32-30105](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30105)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下:
+
+| **板载外设** | **支持情况** | **备注** |
+| :--- | :---: | :--- |
+| USB 转串口 | 支持 | 使用 USART0 |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO | 支持 | PA0, PA1...PE15 ---> PIN: 0, 1...79 |
+| USART | 支持 | USART0/1 |
+| UART | 支持 | UART0/1 |
+| SPI | 支持 | SPI0/1 |
+| I2C | 支持 | 硬件 I2C0/1 |
+| ADC | 暂不支持 | |
+| WDT | 暂不支持 | |
+
+## 使用说明
+
+使用说明分为如下两个章节:
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明,遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上,看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多片上资源,实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。
+
+#### 编译下载
+
+双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
+
+> 注:工程默认配置使用CMSIS-DAP下载方式,在通过 e-Link32 Lite 连接开发板的基础上,点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后,系统会自动运行,观察开发板上 LED 的运行效果,LED1和LED2交替闪烁。
+
+连接开发板对应串口到 PC(也可以通过e-Link32 Lite的模拟串口将开发板连接到PC), 在终端工具里调整好串口配置(115200-8-1-N)并打开相应的串口,复位设备后,可以看到 RT-Thread 的输出信息:
+
+> 注:由于RT-Thread的finsh控制台使用的是命令行的输入形式,推荐使用串口调试工具如:Tabby terminal 或者 Tera Term。
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.1.0 build Apr 10 2024 14:39:43
+ 2006 - 2024 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 USART0 的功能,如果需使用更多的片上资源,需要利用 ENV 工具对BSP 进行配置,步骤如下:
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程,配置好之后保存退出。
+
+3. 输入`scons --target=mdk5` 命令重新生成工程。
+
+## 注意事项
+
+开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载,如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。
+
+## 联系人信息
+
+维护人:
+
+- [QT-one](https://github.com/QT-one)
\ No newline at end of file
diff --git a/bsp/ht32/ht32f12366/SConscript b/bsp/ht32/ht32f12366/SConscript
new file mode 100644
index 00000000000..682f94215ca
--- /dev/null
+++ b/bsp/ht32/ht32f12366/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os #包含os库
+Import('RTT_ROOT') #导入RTT_ROOT对象(RTT_ROOT代表的是RT-Thread源码包)
+from building import * #把building模块的所有内容都导入到当前模块中
+
+cwd = GetCurrentDir() #获取当前路径,并将该路径信息保存到变量cwd中
+objs = [] #创建一个list型变量objs
+list = os.listdir(cwd) #得到当前目录下的所有子目录,并保存到变量list中
+
+for d in list: #for循环用d记录循环的次数,直到寻遍所有路径
+ path = os.path.join(cwd, d) #根据d获取到不同的路径
+ if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件
+ objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中
+
+Return('objs') #将objs返回出去
diff --git a/bsp/ht32/ht32f12366/SConstruct b/bsp/ht32/ht32f12366/SConstruct
new file mode 100644
index 00000000000..5fcd0e3860a
--- /dev/null
+++ b/bsp/ht32/ht32f12366/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ht32_library = 'HT32_STD_1xxxx_FWLib'
+rtconfig.BSP_LIBRARY_TYPE = ht32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/ht32/ht32f12366/applications/SConscript b/bsp/ht32/ht32f12366/applications/SConscript
new file mode 100644
index 00000000000..9023be657ab
--- /dev/null
+++ b/bsp/ht32/ht32f12366/applications/SConscript
@@ -0,0 +1,21 @@
+#导入其他模块的变量
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#导入使用到的模块
+from building import *
+
+#获取当前目录的路径
+cwd = GetCurrentDir()
+
+#创建一个列表,用于保存需要使用到的C文件路径
+src = Glob('*c')
+
+#创建一个列表,用于保存需要包含的H文件路径
+path = [cwd]
+
+#创建一个组别
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+#返回创建好的组别
+Return('group')
\ No newline at end of file
diff --git a/bsp/ht32/ht32f12366/applications/main.c b/bsp/ht32/ht32f12366/applications/main.c
new file mode 100644
index 00000000000..6df261c71be
--- /dev/null
+++ b/bsp/ht32/ht32f12366/applications/main.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#include
+#include
+#include "board.h"
+
+/* defined the led2 pin: pd15 */
+#define LED1_PIN GET_PIN(D, 15)
+/* defined the led3 pin: pe0 */
+#define LED2_PIN GET_PIN(E, 0)
+
+int main(void)
+{
+ rt_uint32_t speed = 200;
+ /* set led1 pin mode to output */
+ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+ /* set led2 pin mode to output */
+ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+ while (1)
+ {
+ rt_pin_write(LED1_PIN, PIN_LOW);
+ rt_pin_write(LED2_PIN, PIN_HIGH);
+ rt_thread_mdelay(speed);
+ rt_pin_write(LED1_PIN, PIN_HIGH);
+ rt_pin_write(LED2_PIN, PIN_LOW);
+ rt_thread_mdelay(speed);
+ }
+}
diff --git a/bsp/ht32/ht32f12366/board/Kconfig b/bsp/ht32/ht32f12366/board/Kconfig
new file mode 100644
index 00000000000..3ee604b7be1
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/Kconfig
@@ -0,0 +1,77 @@
+menu "Hardware Drivers Config"
+
+config SOC_HT32F12366
+ bool
+ select SOC_SERIES_HT32F1
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default n
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default n
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_USART0
+ bool "Enable USART0"
+ default n
+
+ config BSP_USING_USART1
+ bool "Enable USART1"
+ default n
+
+ config BSP_USING_UART0
+ bool "Enable UART0"
+ default n
+
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI Bus"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI0
+ bool "Enable SPI0 Bus"
+ default n
+
+ config BSP_USING_SPI1
+ bool "Enable SPI1 Bus"
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C
+ bool "Enable I2C Bus"
+ default n
+ select RT_USING_I2C
+ if BSP_USING_I2C
+ config BSP_USING_I2C0
+ bool "Enable I2C0 Bus"
+ default n
+
+ config BSP_USING_I2C1
+ bool "Enable I2C1 Bus"
+ default n
+ endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/ht32/ht32f12366/board/SConscript b/bsp/ht32/ht32f12366/board/SConscript
new file mode 100644
index 00000000000..ba173ea9682
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/SConscript
@@ -0,0 +1,27 @@
+
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+src = Glob('src/*.c')
+
+startup_path_prefix = SDK_LIB
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s']
+
+path = [cwd]
+path = [cwd + '/inc']
+
+CPPDEFINES = ['USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
\ No newline at end of file
diff --git a/bsp/ht32/ht32f12366/board/inc/board.h b/bsp/ht32/ht32f12366/board/inc/board.h
new file mode 100644
index 00000000000..91d5c2d0a53
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/inc/board.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+#include "ht32.h"
+#include "ht32_msp.h"
+
+#ifdef BSP_USING_GPIO
+ #include "drv_gpio.h"
+#endif
+
+#ifdef BSP_USING_UART
+ #include "drv_usart.h"
+#endif
+
+#ifdef BSP_USING_SPI
+ #include "drv_spi.h"
+#endif
+
+#ifdef BSP_USING_I2C
+ #include "drv_i2c.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* whether use board external SRAM memory */
+#define HT32_EXT_SRAM 0
+#define HT32_EXT_SRAM_BEGIN 0x68000000
+#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024)
+
+/* internal sram memory size */
+#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE)
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+#define HEAP_END HT32_SRAM_END
+
+void rt_hw_board_clock_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/ht32/ht32f12366/board/inc/ht32_msp.h b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h
new file mode 100644
index 00000000000..8d05995146f
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#ifndef __HT32_MSP_H__
+#define __HT32_MSP_H__
+
+#include
+#include "ht32.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* UART gpio */
+#ifdef BSP_USING_UART
+#ifdef BSP_USING_USART0
+
+ #define HTCFG_USART0_IPN USART0
+
+ #define _HTCFG_USART0_TX_GPIOX A
+ #define _HTCFG_USART0_TX_GPION 8
+ #define _HTCFG_USART0_RX_GPIOX A
+ #define _HTCFG_USART0_RX_GPION 10
+
+ #define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX)
+ #define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX)
+ #define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX)
+ #define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION)
+
+ #define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX)
+ #define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX)
+ #define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX)
+ #define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION)
+
+#endif
+#ifdef BSP_USING_USART1
+
+ #define HTCFG_USART1_IPN USART1
+
+ #define _HTCFG_USART1_TX_GPIOX A
+ #define _HTCFG_USART1_TX_GPION 4
+ #define _HTCFG_USART1_RX_GPIOX A
+ #define _HTCFG_USART1_RX_GPION 5
+
+ #define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX)
+ #define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX)
+ #define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX)
+ #define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION)
+
+ #define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX)
+ #define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX)
+ #define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX)
+ #define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION)
+
+#endif
+#ifdef BSP_USING_UART0
+
+ #define HTCFG_UART0_IPN UART0
+
+ #define _HTCFG_UART0_TX_GPIOX C
+ #define _HTCFG_UART0_TX_GPION 9
+ #define _HTCFG_UART0_RX_GPIOX C
+ #define _HTCFG_UART0_RX_GPION 10
+
+ #define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX)
+ #define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX)
+ #define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX)
+ #define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION)
+
+ #define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX)
+ #define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX)
+ #define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX)
+ #define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION)
+
+#endif
+#ifdef BSP_USING_UART1
+
+ #define HTCFG_UART1_IPN UART1
+
+ #define _HTCFG_UART1_TX_GPIOX C
+ #define _HTCFG_UART1_TX_GPION 2
+ #define _HTCFG_UART1_RX_GPIOX C
+ #define _HTCFG_UART1_RX_GPION 3
+
+ #define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX)
+ #define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX)
+ #define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX)
+ #define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION)
+
+ #define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX)
+ #define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX)
+ #define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX)
+ #define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION)
+
+#endif
+#endif
+
+/* SPI gpio */
+#ifdef BSP_USING_SPI
+#ifdef BSP_USING_SPI0
+
+ #define HTCFG_SPI0_IPN SPI0
+
+ #define _HTCFG_SPI0_SCK_GPIOX B
+ #define _HTCFG_SPI0_SCK_GPION 3
+
+ #define _HTCFG_SPI0_MISO_GPIOX B
+ #define _HTCFG_SPI0_MISO_GPION 5
+
+ #define _HTCFG_SPI0_MOSI_GPIOX B
+ #define _HTCFG_SPI0_MOSI_GPION 4
+
+ #define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX)
+ #define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX)
+ #define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION)
+
+ #define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX)
+ #define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX)
+ #define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION)
+
+ #define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX)
+ #define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX)
+ #define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION)
+
+#endif
+#ifdef BSP_USING_SPI1
+
+ #define HTCFG_SPI1_IPN SPI1
+
+ #define _HTCFG_SPI1_SCK_GPIOX B
+ #define _HTCFG_SPI1_SCK_GPION 7
+
+ #define _HTCFG_SPI1_MISO_GPIOX B
+ #define _HTCFG_SPI1_MISO_GPION 9
+
+ #define _HTCFG_SPI1_MOSI_GPIOX B
+ #define _HTCFG_SPI1_MOSI_GPION 8
+
+ #define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX)
+ #define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX)
+ #define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION)
+
+ #define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX)
+ #define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX)
+ #define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION)
+
+ #define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX)
+ #define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX)
+ #define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION)
+
+#endif
+#endif
+
+/* I2C gpio */
+#ifdef BSP_USING_I2C
+#ifdef BSP_USING_I2C0
+
+ #define HTCFG_I2C0_IPN I2C0
+
+ #define _HTCFG_I2C0_SCL_GPIOX B
+ #define _HTCFG_I2C0_SCL_GPION 12
+
+ #define _HTCFG_I2C0_SDA_GPIOX B
+ #define _HTCFG_I2C0_SDA_GPION 13
+
+ #define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX)
+ #define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX)
+ #define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION)
+
+ #define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX)
+ #define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX)
+ #define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION)
+
+#endif
+#ifdef BSP_USING_I2C1
+
+ #define HTCFG_I2C1_IPN I2C1
+
+ #define _HTCFG_I2C1_SCL_GPIOX A
+ #define _HTCFG_I2C1_SCL_GPION 0
+
+ #define _HTCFG_I2C1_SDA_GPIOX A
+ #define _HTCFG_I2C1_SDA_GPION 1
+
+ #define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX)
+ #define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX)
+ #define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION)
+
+ #define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX)
+ #define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX)
+ #define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION)
+
+#endif
+#endif
+
+void ht32_usart_gpio_init(void *instance);
+void ht32_spi_gpio_init(void *instance);
+void ht32_i2c_gpio_init(void *instance);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HT32_MSP_H__ */
diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h
new file mode 100644
index 00000000000..432b323d7a4
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h
@@ -0,0 +1,453 @@
+/*********************************************************************************************************//**
+ * @file IP/Example/ht32f1xxxx_01_usbdconf.h
+ * @version $Rev:: 1090 $
+ * @date $Date:: 2018-01-29 #$
+ * @brief The configuration file of USB Device Driver.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ * other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ * other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ * the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * Copyright (C) Holtek Semiconductor Inc. All rights reserved
+ ************************************************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32F1XXXX_01_USBDCONF_H
+#define __HT32F1XXXX_01_USBDCONF_H
+
+// Enter Low Power mode when Suspended
+#define USBDCORE_ENABLE_LOW_POWER (0)
+//
+
+#if (USBDCORE_ENABLE_LOW_POWER == 1)
+ #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
+#else
+ #define USBDCore_LowPower(...)
+#endif
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* USB Interrupt Enable */
+/*----------------------------------------------------------------------------------------------------------*/
+// USB Interrupt Setting (UIER)
+// USB Global Interrupt Enable (UGIE) (Default)
+// Start Of Frame Interrupt Enable (SOFIE)
+// USB Reset Interrupt Enable (URSTIE) (Default)
+// Resume Interrupt Enable (RSMIE) (Default)
+// Suspend Interrupt Enable (SUSPIE) (Default)
+// Expected Start of Frame Interrupt Enable (ESOFE)
+// Control Endpoint Interrupt Enable (EP0IE) (Default)
+// Endpoint1 Interrupt Enable (EP1IE)
+// Endpoint2 Interrupt Enable (EP2IE)
+// Endpoint3 Interrupt Enable (EP3IE)
+// Endpoint4 Interrupt Enable (EP4IE)
+// Endpoint5 Interrupt Enable (EP5IE)
+// Endpoint6 Interrupt Enable (EP6IE)
+// Endpoint7 Interrupt Enable (EP7IE)
+#define _UIER (0x011D)
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint0 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Control Endpoint0 Configuration
+// Endpoint Buffer Length (EPLEN)
+// <8=> 8 bytes
+// <16=> 16 bytes
+// <32=> 32 bytes
+// <64=> 64 bytes
+ /* Maximum: 64 Bytes */
+#define _EP0LEN (64)
+
+
+// Control Endpoint0 Interrupt Enable Settings (EP0IER)
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+// SETUP Token Packet Received Interrupt Enable (STRXIE)
+// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
+// SETUP Data Error Interrupt Enable (SDERIE)
+// Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
+#define _EP0_IER (0x212)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint1 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint1 Configuration
+#define _EP1_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP1_CFG_EPADR (1)
+
+// Endpoint Enable (EPEN)
+#define _EP1_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP1_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP1_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP1LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP1_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint2 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint2 Configuration
+#define _EP2_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP2_CFG_EPADR (2)
+
+// Endpoint Enable (EPEN)
+#define _EP2_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP2_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP2_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP2LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP2_IER (0x002)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint3 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint3 Configuration
+#define _EP3_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP3_CFG_EPADR (3)
+
+// Endpoint Enable (EPEN)
+#define _EP3_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP3_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP3_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP3LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP3_IER (0x10)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint4 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint4 Configuration
+#define _EP4_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP4_CFG_EPADR (4)
+
+// Endpoint Enable (EPEN)
+#define _EP4_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP4_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP4_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP4LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP4_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP4_IER (0x02)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint5 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint5 Configuration
+#define _EP5_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP5_CFG_EPADR (5)
+
+// Endpoint Enable (EPEN)
+#define _EP5_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP5_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP5_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP5LEN_TMP (8)
+
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP5_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP5_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint6 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint6 Configuration
+#define _EP6_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP6_CFG_EPADR (6)
+
+// Endpoint Enable (EPEN)
+#define _EP6_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP6_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP6_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP6LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP6_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP6_IER (0x02)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint7 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint7 Configuration
+#define _EP7_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP7_CFG_EPADR (7)
+
+// Endpoint Enable (EPEN)
+#define _EP7_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP7_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP7_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP7LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP7_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP7_IER (0x10)
+//
+//
+
+#endif
diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h
new file mode 100644
index 00000000000..1128790b115
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h
@@ -0,0 +1,490 @@
+/*********************************************************************************************************//**
+ * @file IP/Example/ht32f1xxxx_conf.h
+ * @version $Rev:: 2922 $
+ * @date $Date:: 2023-06-07 #$
+ * @brief Library configuration file.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ * other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ * other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ * the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * Copyright (C) Holtek Semiconductor Inc. All rights reserved
+ ************************************************************************************************************/
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32F1XXXX_CONF_H
+#define __HT32F1XXXX_CONF_H
+
+/* Exported constants --------------------------------------------------------------------------------------*/
+
+#define RETARGET_ITM 0
+#define RETARGET_USB 1
+#define RETARGET_SYSLOG 2
+#define RETARGET_COM1 10
+#define RETARGET_COM2 11
+#define RETARGET_USART0 12
+#define RETARGET_USART1 13
+#define RETARGET_UART0 14
+#define RETARGET_UART1 15
+
+
+/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */
+/*
+// Enable Retarget
+// Retarget Port
+// <0=> ITM
+// <1=> USB Virtual COM
+// <2=> Syslog
+// <10=> COM1
+// <11=> COM2
+// <12=> USART0
+// <13=> USART1
+// <14=> UART0
+// <15=> UART1
+// Enable Auto Return
+// Auto Return function adds "\r" before "\n" automatically when print message by Retarget.
+*/
+#define _RETARGET 1
+#define RETARGET_PORT 10
+#define _AUTO_RETURN 0
+
+#ifndef AUTO_RETURN
+#if (_AUTO_RETURN == 1)
+#define AUTO_RETURN
+#endif
+#endif
+
+/* Enable Interrupt Mode for UxART Retarget
+// Retarget COM/UxART Setting
+// UxART Baudrate
+// Enable Interrupt Mode for UxART Tx Retarget
+// Define UxARTn_IRQHandler By Retarget (ht32_serial.c)
+// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler.
+// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable.
+// Tx Buffer Length (in byte)
+//
+*/
+#define RETARGET_UxART_BAUDRATE 115200
+#define RETARGET_INT_MODE 0
+#define RETARGET_DEFINE_HANDLER 1
+#define RETARGET_INT_BUFFER_SIZE 64
+
+#if (_RETARGET == 1)
+#if (RETARGET_PORT == RETARGET_ITM)
+#elif (RETARGET_PORT == RETARGET_USB)
+ #define RETARGET_IS_USB
+// Retarget USB Virtual COM Setting
+// Communication (Interrupt IN)
+// <1=> Endpoint 1
+// <2=> Endpoint 2
+// <3=> Endpoint 3
+// <4=> Endpoint 4
+// <5=> Endpoint 5
+// <6=> Endpoint 6
+// <7=> Endpoint 7
+// Data Rx (Bulk OUT)
+// <1=> Endpoint 1
+// <2=> Endpoint 2
+// <3=> Endpoint 3
+// <4=> Endpoint 4
+// <5=> Endpoint 5
+// <6=> Endpoint 6
+// <7=> Endpoint 7
+// Data Tx (Bulk IN)
+// <1=> Endpoint 1
+// <2=> Endpoint 2
+// <3=> Endpoint 3
+// <4=> Endpoint 4
+// <5=> Endpoint 5
+// <6=> Endpoint 6
+// <7=> Endpoint 7
+// Communication Endpoint Buffer Length (in byte) <4-64:4>
+// Data Rx Endpoint Buffer Length (in byte) <4-64:4>
+// Data Tx Endpoint Buffer Length (in byte) <4-64:4>
+// Rx Buffer Length (in byte) <64-1024:4>
+// Tx Buffer Length (in byte) <1-63:1>
+// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
+// USB Tx Mode (BULK IN)
+// <0=> Block Mode (Wait until both USB and terminal software are ready)
+// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready)
+// Enable HSI Auto Trim By USB Function
+// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source).
+ #define RETARGET_CTRL_EPT (5)
+ #define RETARGET_RX_EPT (6)
+ #define RETARGET_TX_EPT (7)
+ #define RETARGET_CTRL_EPTLEN (8)
+ #define RETARGET_RX_EPTLEN (64)
+ #define RETARGET_TX_EPTLEN (64)
+ #define RETARGET_BUFFER_SIZE (64)
+ #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
+ #define RETARGET_USB_MODE (0)
+ #define RETARGET_HSI_ATM (1)
+//
+#elif (RETARGET_PORT == RETARGET_COM1)
+ #define RETARGET_COM_PORT COM1
+ #define RETARGET_USART_PORT COM1_PORT
+ #define RETARGET_UART_IRQn COM1_IRQn
+ #define RETARGET_UART_IRQHandler COM1_IRQHandler
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_COM2)
+ #define RETARGET_COM_PORT COM2
+ #define RETARGET_USART_PORT COM2_PORT
+ #define RETARGET_UART_IRQn COM2_IRQn
+ #define RETARGET_UART_IRQHandler COM2_IRQHandler
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_USART0)
+ #define RETARGET_UxART_IPN USART0
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_USART1)
+ #define RETARGET_UxART_IPN USART1
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_UART0)
+ #define RETARGET_UxART_IPN UART0
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_UART1)
+ #define RETARGET_UxART_IPN UART1
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#endif
+ extern void RETARGET_Configuration(void);
+#else
+ #define RETARGET_Configuration(...)
+ #undef printf
+ #undef getchar
+ #define printf(...)
+ #define getchar() (0)
+#endif
+
+#if (RETARGET_DEFINE_HANDLER == 0)
+#undef RETARGET_UART_IRQHandler
+#endif
+
+/*
+// Enable HT32 Time Function
+// Provide "Time_GetTick()" and "Time_Dealy()" functions.
+
+// Timer Selection
+// <0=> BFTM0
+// <1=> BFTM1
+// <2=> SCTM0
+// <3=> SCTM1
+// <4=> SCTM2
+// <5=> SCTM3
+// <6=> PWM0
+// <7=> PWM1
+// <8=> PWM2
+// <9=> GPTM0
+// <10=> GPTM1
+// <11=> MCTM0
+
+// Timer Clock Setting
+//
+// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
+// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV)
+// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
+
+// -- Core Clock Setting (CK_AHB)
+// HTCFG_TIME_CLKSEL
+// 0 = Default Maximum (LIBCFG_MAX_SPEED)
+// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL)
+// <0=> Default Maximum (LIBCFG_MAX_SPEED)
+// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL)
+
+// -- Core Clock Manual Input (Hz)
+// HTCFG_TIME_CLK_MANUAL
+// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1)
+
+// -- APB Peripheral Clock Prescaler
+// HTCFG_TIME_PCLK_DIV
+// <0=> /1
+// <1=> /2
+// <2=> /4
+// <3=> /8
+
+// Time Tick (Hz, not applicable for BFTM) <1-1000000:100>
+// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM.
+*/
+#if (0) // Enable HT32 Time Function
+#define HTCFG_TIME_IPSEL (0)
+#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC)
+#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input)
+#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8)
+#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM
+#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM.
+/*
+
+ Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
+ HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV)
+ where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
+
+ Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time)
+ Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second
+ (Interrupt Time is not applicable for BFTM)
+
+ Example: 32-bit BFTM with 48 MHz Timer Clock
+ HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000
+ Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second)
+ BFTM do not use interrupt
+
+ Example: 16-bit GPTM with 1 ms tick
+ HTCFG_TIME_TICKHZ = 1000 (Hz)
+ HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick)
+ Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day)
+ Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second)
+*/
+#endif
+/*
+//
+*/
+
+/* !!! NOTICE !!!
+ * How to adjust the value of High Speed External oscillator (HSE)?
+ The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h".
+ If your board uses a different HSE speed, please add a new compiler preprocessor
+ C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE,
+ or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file (this file).
+*/
+/*
+// Enable User Define HSE Value
+// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h".
+// HSE Value (Hz)
+*/
+#if (0)
+#define HSE_VALUE 16000000
+#endif
+/*
+//
+*/
+
+/*
+// Enable CKOUT Function
+*/
+#define ENABLE_CKOUT 0
+
+
+/* The DEBUG definition to enter debug mode for library */
+/*
+// Library Debug Mode
+*/
+#define HT32_LIB_DEBUG 0
+
+
+/* Enable/disable the specific peripheral inclusion */
+
+// Library Inclusion Configuration
+/* ADC -----------------------------------------------------------------------------------------------------*/
+/*
+// ADC Library
+*/
+#define _ADC 1
+
+/* AES -----------------------------------------------------------------------------------------------------*/
+/*
+// AES Library
+*/
+#define _AES 1
+
+/* BFTM ----------------------------------------------------------------------------------------------------*/
+/*
+// BFTM Library
+*/
+#define _BFTM 1
+
+/* Clock Control -------------------------------------------------------------------------------------------*/
+/*
+// Clock Control Library
+*/
+#define _CKCU 1
+
+/* Comparator/OPA ------------------------------------------------------------------------------------------*/
+/*
+// Comparator/OPA Library
+*/
+#define _CMP_OPA 1
+
+/* Comparator ----------------------------------------------------------------------------------------------*/
+/*
+// Comparator Library
+*/
+#define _CMP 1
+
+/* CRC -----------------------------------------------------------------------------------------------------*/
+/*
+// CRC Library
+*/
+#define _CRC 1
+
+/* CSIF ----------------------------------------------------------------------------------------------------*/
+/*
+// CSIF Library
+*/
+#define _CSIF 1
+
+/* EBI -----------------------------------------------------------------------------------------------------*/
+/*
+// EBI Library
+*/
+#define _EBI 1
+
+/* EXTI ----------------------------------------------------------------------------------------------------*/
+/*
+// EXTI Library
+*/
+#define _EXTI 1
+
+/* Flash ---------------------------------------------------------------------------------------------------*/
+/*
+// Flash Library
+*/
+#define _FLASH 1
+
+/* GPIO ----------------------------------------------------------------------------------------------------*/
+/*
+// GPIO Library
+*/
+#define _GPIO 1
+
+/* GPTM ----------------------------------------------------------------------------------------------------*/
+/*
+// GPTM Library
+*/
+#define _GPTM 1
+
+/* I2C -----------------------------------------------------------------------------------------------------*/
+/*
+// I2C Library
+*/
+#define _I2C 1
+
+/* I2S -----------------------------------------------------------------------------------------------------*/
+/*
+// I2S Library
+*/
+#define _I2S 1
+
+/* MCTM ----------------------------------------------------------------------------------------------------*/
+/*
+// MCTM Library
+*/
+#define _MCTM 1
+
+/* PDMA ----------------------------------------------------------------------------------------------------*/
+/*
+// PDMA Library
+*/
+#define _PDMA 1
+
+/* PWM -----------------------------------------------------------------------------------------------------*/
+/*
+// PWM Library
+*/
+#define _PWM 1
+
+/* PWRCU ---------------------------------------------------------------------------------------------------*/
+/*
+// PWRCU Library
+*/
+#define _PWRCU 1
+
+/* RSTCU ---------------------------------------------------------------------------------------------------*/
+/*
+// RSTCU Library
+*/
+#define _RSTCU 1
+
+/* RTC -----------------------------------------------------------------------------------------------------*/
+/*
+// RTC Library
+*/
+#define _RTC 1
+
+/* SCI -----------------------------------------------------------------------------------------------------*/
+/*
+// SCI Library
+*/
+#define _SCI 1
+
+/* SCTM ----------------------------------------------------------------------------------------------------*/
+/*
+// SCTM Library
+*/
+#define _SCTM 1
+
+/* SDIO ----------------------------------------------------------------------------------------------------*/
+/*
+// SDIO Library
+*/
+#define _SDIO 1
+
+/* SPI -----------------------------------------------------------------------------------------------------*/
+/*
+// SPI Library
+*/
+#define _SPI 1
+
+/* USART ---------------------------------------------------------------------------------------------------*/
+/*
+// USART/UART Library
+*/
+#define _USART 1
+
+/* USBD ----------------------------------------------------------------------------------------------------*/
+/*
+// USB Library
+*/
+#define _USB 1
+
+/* WDT -----------------------------------------------------------------------------------------------------*/
+/*
+// WDT Library
+*/
+#define _WDT 1
+
+/* Misc ----------------------------------------------------------------------------------------------------*/
+/*
+// Misc Library
+*/
+#define _MISC 1
+
+/* Serial --------------------------------------------------------------------------------------------------*/
+/*
+// Serial Library
+*/
+#define _SERIAL 1
+
+/* Software Random Number ----------------------------------------------------------------------------------*/
+/*
+// Software Random Number Library
+*/
+#define _SWRAND 1
+
+
+//
+
+#endif
diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.icf b/bsp/ht32/ht32f12366/board/linker_scripts/link.icf
new file mode 100644
index 00000000000..65c2bfc8b7c
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__ = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, last block CSTACK};
\ No newline at end of file
diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.lds b/bsp/ht32/ht32f12366/board/linker_scripts/link.lds
new file mode 100644
index 00000000000..27269dd77ea
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.lds
@@ -0,0 +1,156 @@
+/*
+ * linker script for AT32 with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
+ RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+
+ PROVIDE(__ctors_start__ = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE(__ctors_end__ = .);
+
+ . = ALIGN(4);
+
+ _etext = .;
+ } > ROM = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > ROM
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+ .stack :
+ {
+ . = ALIGN(4);
+ _sstack = .;
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >RAM
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > RAM
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.sct b/bsp/ht32/ht32f12366/board/linker_scripts/link.sct
new file mode 100644
index 00000000000..16cced4f77f
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x0003FC00 { ; load region size_region
+ ER_IROM1 0x00000000 0x0003FC00 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/ht32/ht32f12366/board/src/board.c b/bsp/ht32/ht32f12366/board/src/board.c
new file mode 100644
index 00000000000..e0160468e94
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/src/board.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#include "board.h"
+
+/* This feature will initialize the HT32 chip clock */
+void rt_hw_board_clock_init(void)
+{
+
+}
diff --git a/bsp/ht32/ht32f12366/board/src/ht32_msp.c b/bsp/ht32/ht32f12366/board/src/ht32_msp.c
new file mode 100644
index 00000000000..4ef7b61b543
--- /dev/null
+++ b/bsp/ht32/ht32f12366/board/src/ht32_msp.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#include "ht32_msp.h"
+
+/* GPIO configuration for UART */
+#ifdef BSP_USING_UART
+void ht32_usart_gpio_init(void *instance)
+{
+ CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
+ HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance;
+#ifdef BSP_USING_USART0
+ if(HT_USART0 == usart_x)
+ {
+ CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+ /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+ GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT,HTCFG_USART0_RX_GPIO_PIN,GPIO_PR_UP);
+ /* Config AFIO mode as UxART function */
+ AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID,HTCFG_USART0_TX_GPIO_PIN,AFIO_FUN_USART_UART);
+ AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID,HTCFG_USART0_RX_GPIO_PIN,AFIO_FUN_USART_UART);
+ }
+#endif
+#ifdef BSP_USING_USART1
+ if(HT_USART1 == usart_x)
+ {
+ CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+ /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+ GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT,HTCFG_USART1_RX_GPIO_PIN,GPIO_PR_UP);
+ /* Config AFIO mode as UxART function */
+ AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID,HTCFG_USART1_TX_GPIO_PIN,AFIO_FUN_USART_UART);
+ AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID,HTCFG_USART1_RX_GPIO_PIN,AFIO_FUN_USART_UART);
+ }
+#endif
+#ifdef BSP_USING_UART0
+ if(HT_UART0 == usart_x)
+ {
+ CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+ /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+ GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT,HTCFG_UART0_RX_GPIO_PIN,GPIO_PR_UP);
+ /* Config AFIO mode as UxART function */
+ AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID,HTCFG_UART0_TX_GPIO_PIN,AFIO_FUN_USART_UART);
+ AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID,HTCFG_UART0_RX_GPIO_PIN,AFIO_FUN_USART_UART);
+ }
+#endif
+#ifdef BSP_USING_UART1
+ if(HT_UART1 == usart_x)
+ {
+ CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+ /* Turn on UxART Rx internal pull up resistor to prevent unknow state */
+ GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT,HTCFG_UART1_RX_GPIO_PIN,GPIO_PR_UP);
+ /* Config AFIO mode as UxART function */
+ AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID,HTCFG_UART1_TX_GPIO_PIN,AFIO_FUN_USART_UART);
+ AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID,HTCFG_UART1_RX_GPIO_PIN,AFIO_FUN_USART_UART);
+ }
+#endif
+}
+#endif
+
+/* GPIO configuration for SPI */
+#ifdef BSP_USING_SPI
+void ht32_spi_gpio_init(void *instance)
+{
+ CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
+ HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance;
+#ifdef BSP_USING_SPI0
+ if(HT_SPI0 == spi_x)
+ {
+ CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+
+ AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI);
+ AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI);
+ AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI);
+ }
+#endif
+#ifdef BSP_USING_SPI1
+ if(HT_SPI1 == spi_x)
+ {
+ CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+
+ AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI);
+ AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI);
+ AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI);
+ }
+#endif
+}
+#endif
+
+/* GPIO configuration for I2C */
+#ifdef BSP_USING_I2C
+void ht32_i2c_gpio_init(void *instance)
+{
+ CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}};
+ HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance;
+#ifdef BSP_USING_I2C0
+ if(HT_I2C0 == i2c_x)
+ {
+ CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+ /* Configure GPIO to I2C mode */
+ AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID,HTCFG_I2C0_SCL_GPIO_PIN,AFIO_FUN_I2C);
+ AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID,HTCFG_I2C0_SDA_GPIO_PIN,AFIO_FUN_I2C);
+ }
+#endif
+#ifdef BSP_USING_I2C1
+ if(HT_I2C1 == i2c_x)
+ {
+ CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1;
+ CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1;
+ CKCU_PeripClockConfig(CKCUClock,ENABLE);
+ /* Configure GPIO to I2C mode */
+ AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID,HTCFG_I2C1_SCL_GPIO_PIN,AFIO_FUN_I2C);
+ AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID,HTCFG_I2C1_SDA_GPIO_PIN,AFIO_FUN_I2C);
+ }
+#endif
+}
+#endif
diff --git a/bsp/ht32/ht32f12366/figures/board.png b/bsp/ht32/ht32f12366/figures/board.png
new file mode 100644
index 00000000000..850221d1afa
Binary files /dev/null and b/bsp/ht32/ht32f12366/figures/board.png differ
diff --git a/bsp/ht32/ht32f12366/project.uvoptx b/bsp/ht32/ht32f12366/project.uvoptx
new file mode 100644
index 00000000000..4c6655f9dd9
--- /dev/null
+++ b/bsp/ht32/ht32f12366/project.uvoptx
@@ -0,0 +1,179 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\keil\List\
+
+
+ 1
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+
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+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM))
+
+
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+
+
+
+ 0
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+
+
+
+
+
+
+
+
+ Source Group 1
+ 0
+ 0
+ 0
+ 0
+
+
+
diff --git a/bsp/ht32/ht32f12366/project.uvprojx b/bsp/ht32/ht32f12366/project.uvprojx
new file mode 100644
index 00000000000..733d03c6803
--- /dev/null
+++ b/bsp/ht32/ht32f12366/project.uvprojx
@@ -0,0 +1,1366 @@
+
+
+ 2.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060422::V5.06 update 4 (build 422)::ARMCC
+
+
+ HT32F12366
+ Holtek
+ Holtek.HT32_DFP.1.0.19
+ http://mcu.holtek.com.tw/pack
+ IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM))
+ 0
+ $$Device:HT32F12366$ARM\INC\Holtek\HT32F1xxxx\ht32f1xxxx_01.h
+
+
+
+
+
+
+
+
+
+ $$Device:HT32F12366$SVD\HT32F12365_66.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
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+ .\build\keil\Obj\
+ rt-thread
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+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
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+ 16
+
+
+
+
+ 1
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+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
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+ "Cortex-M3"
+
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+ 0
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+
+
+ __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366, __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, __RTTHREAD__
+
+ ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\ht32_drivers;..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Include;applications;..\..\..\libcpu\arm\cortex-m3;..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\inc;.;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;board\inc;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\ipc;..\libraries\HT32_STD_1xxxx_FWLib\library\CMSIS\Include
+
+
+
+ 1
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+
+
+
+
+
+ 0
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+ 0x00000000
+ 0x20000000
+
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+
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+
+
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+
+
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+
+
+
+
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+
+
+ syscall_mem.c
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+
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+
+
+
+
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+ 1
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+
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+
+
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+
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+
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+
+
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+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
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+
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+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ kstdio.c
+ 1
+ ..\..\..\src\klibc\kstdio.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ kstring.c
+ 1
+ ..\..\..\src\klibc\kstring.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ memheap.c
+ 1
+ ..\..\..\src\memheap.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ scheduler_comm.c
+ 1
+ ..\..\..\src\scheduler_comm.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ scheduler_up.c
+ 1
+ ..\..\..\src\scheduler_up.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ libcpu
+
+
+ atomic_arm.c
+ 1
+ ..\..\..\libcpu\arm\common\atomic_arm.c
+
+
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+
+
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+
+
+ Libraries
+
+
+ ht32f1xxxx_wdt.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_wdt.c
+
+
+
+
+ ht32f1xxxx_sci.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sci.c
+
+
+
+
+ ht32f1xxxx_rstcu.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rstcu.c
+
+
+
+
+ ht32f1xxxx_usbd.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usbd.c
+
+
+
+
+ ht32f1xxxx_tm.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_tm.c
+
+
+
+
+ ht32f1xxxx_ckcu.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ckcu.c
+
+
+
+
+ ht32f1xxxx_usart.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usart.c
+
+
+
+
+ ht32f1xxxx_aes.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_aes.c
+
+
+
+
+ ht32f1xxxx_flash.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_flash.c
+
+
+
+
+ ht32f1xxxx_gpio.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_gpio.c
+
+
+
+
+ ht32_cm3_misc.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32_cm3_misc.c
+
+
+
+
+ ht32f1xxxx_crc.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_crc.c
+
+
+
+
+ ht32f1xxxx_sdio.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c
+
+
+
+
+ ht32f1xxxx_ebi.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ebi.c
+
+
+
+
+ ht32f1xxxx_cmp.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c
+
+
+
+
+ ht32f1xxxx_i2c.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c
+
+
+
+
+ ht32f1xxxx_adc.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c
+
+
+
+
+ ht32f1xxxx_pwrcu.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c
+
+
+
+
+ ht32f1xxxx_pdma.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c
+
+
+
+
+ system_ht32f1xxxx_02.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c
+
+
+
+
+ ht32f1xxxx_mctm.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_mctm.c
+
+
+
+
+ ht32f1xxxx_spi.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c
+
+
+
+
+ ht32f1xxxx_bftm.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_bftm.c
+
+
+
+
+ ht32f1xxxx_i2s.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c
+
+
+
+
+ ht32f1xxxx_exti.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_exti.c
+
+
+
+
+ ht32f1xxxx_rtc.c
+ 1
+ ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rtc.c
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/ht32/ht32f12366/rtconfig.h b/bsp/ht32/ht32f12366/rtconfig.h
new file mode 100644
index 00000000000..42fd7c23e09
--- /dev/null
+++ b/bsp/ht32/ht32f12366/rtconfig.h
@@ -0,0 +1,273 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "usart0"
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
+#define RT_USING_SPI
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Memory protection */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+
+/* Kendryte SDK */
+
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_FAMILY_HT32
+#define SOC_SERIES_HT32F1
+
+/* Hardware Drivers Config */
+
+#define SOC_HT32F12366
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_USART0
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/ht32/ht32f12366/rtconfig.py b/bsp/ht32/ht32f12366/rtconfig.py
new file mode 100644
index 00000000000..1c3077b6cf4
--- /dev/null
+++ b/bsp/ht32/ht32f12366/rtconfig.py
@@ -0,0 +1,152 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+# EXEC_PATH = r'D:\keil5\keil_v532\UV4'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M3 '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M3'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M3'
+ AFLAGS += ' --fpu None'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
+
diff --git a/bsp/ht32/ht32f12366/template.uvoptx b/bsp/ht32/ht32f12366/template.uvoptx
new file mode 100644
index 00000000000..4c6655f9dd9
--- /dev/null
+++ b/bsp/ht32/ht32f12366/template.uvoptx
@@ -0,0 +1,179 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\keil\List\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 2
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
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+ 0
+ 0
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ Source Group 1
+ 0
+ 0
+ 0
+ 0
+
+
+
diff --git a/bsp/ht32/ht32f12366/template.uvprojx b/bsp/ht32/ht32f12366/template.uvprojx
new file mode 100644
index 00000000000..9b24487b535
--- /dev/null
+++ b/bsp/ht32/ht32f12366/template.uvprojx
@@ -0,0 +1,392 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060422::V5.06 update 4 (build 422)::ARMCC
+
+
+ HT32F12366
+ Holtek
+ Holtek.HT32_DFP.1.0.19
+ http://mcu.holtek.com.tw/pack
+ IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM))
+ 0
+ $$Device:HT32F12366$ARM\INC\Holtek\HT32F1xxxx\ht32f1xxxx_01.h
+
+
+
+
+
+
+
+
+
+ $$Device:HT32F12366$SVD\HT32F12365_66.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\keil\Obj\
+ rt-thread
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\build\keil\List\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
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+ 0
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+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
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+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 0
+ 0
+ 0
+ 0
+ 3
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+ 0x0
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+ 0x0
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+ 0x0
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+ 0x0
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+
+ 0
+ 0x20000000
+ 0x20000
+
+
+ 1
+ 0x0
+ 0x3fc00
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x3fc00
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x20000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+ USE_HT32_CHIP=2
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+ .\board\linker_scripts\link.sct
+
+
+
+
+
+
+
+
+
+
+ Source Group 1
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/ht32/ht32f52352/.config b/bsp/ht32/ht32f52352/.config
new file mode 100644
index 00000000000..b89bfb8deb1
--- /dev/null
+++ b/bsp/ht32/ht32f52352/.config
@@ -0,0 +1,1092 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="usart1"
+CONFIG_RT_VER_NUM=0x50100
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_RT_USING_HW_ATOMIC is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M0=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_SOFT_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_BITOPS is not set
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_FAMILY_HT32=y
+CONFIG_SOC_SERIES_HT32F5=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HT32F52352=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_USART0 is not set
+CONFIG_BSP_USING_USART1=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/ht32/ht32f52352/Kconfig b/bsp/ht32/ht32f52352/Kconfig
new file mode 100644
index 00000000000..79b160b8567
--- /dev/null
+++ b/bsp/ht32/ht32f52352/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/ht32/ht32f52352/README.md b/bsp/ht32/ht32f52352/README.md
new file mode 100644
index 00000000000..10644a76a4a
--- /dev/null
+++ b/bsp/ht32/ht32f52352/README.md
@@ -0,0 +1,108 @@
+# HT32F52352 BSP 说明
+
+## 简介
+
+ESK32-30501是合泰基于HT32F52352芯片并针对Cortex®-M0+入门而设计的评估板。本文档是为ESK32-30501开发板提供的BSP(板级支持包)说明。
+
+主要内容如下:
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP,将 RT-Thread 运行在开发板上。
+
+## 开发板介绍
+
+ESK32-30501使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F52352,针对Cortex®-M0+入门而设计。开发板外观如下图所示:
+
+![board.png](figures/board.png)
+
+该开发板常用 **板载资源** 如下:
+
+- MCU:HT32F52352,主频 48MHz,128KB FLASH ,16KB SRAM
+- 常用外设
+ - LED:2个,(绿色,PC14、PC15)
+- 常用接口:USB 转串口 、USB SLAVE
+- 调试接口:板载的 e-Link32 Lite SWD 下载
+
+开发板更多详细信息请参考合泰官网的相关文档[ESK32-30501](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30501)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下:
+
+| **板载外设** | **支持情况** | **备注** |
+| :--- | :---: | :--- |
+| USB 转串口 | 支持 | 使用 USART1 |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO | 支持 | PA0, PA1...PD3 ---> PIN: 0, 1...51 |
+| USART | 支持 | USART0/1 |
+| UART | 支持 | UART0/1 |
+| SPI | 支持 | SPI0/1 |
+| I2C | 支持 | 硬件 I2C0/1 |
+| ADC | 暂不支持 | |
+| WDT | 暂不支持 | |
+
+## 使用说明
+
+使用说明分为如下两个章节:
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明,遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上,看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多片上资源,实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。
+
+#### 编译下载
+
+双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
+
+> 注:工程默认配置使用CMSIS-DAP下载方式,在通过 e-Link32 Lite 连接开发板的基础上,点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后,系统会自动运行,观察开发板上 LED 的运行效果,LED1和LED2交替闪烁。
+
+连接开发板对应串口到 PC(也可以通过e-Link32 Lite的模拟串口将开发板连接到PC), 在终端工具里调整好串口配置(115200-8-1-N)并打开相应的串口,复位设备后,可以看到 RT-Thread 的输出信息:
+
+> 注:由于RT-Thread的finsh控制台使用的是命令行的输入形式,推荐使用串口调试工具如:Tabby terminal 或者 Tera Term。
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.1.0 build Apr 10 2024 14:39:43
+ 2006 - 2024 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 USART1 的功能,如果需使用更多的片上资源,需要利用 ENV 工具对BSP 进行配置,步骤如下:
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程,配置好之后保存退出。
+
+3. 输入`scons --target=mdk5` 命令重新生成工程。
+
+## 注意事项
+
+开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载,如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。
+
+## 联系人信息
+
+维护人:
+
+- [QT-one](https://github.com/QT-one)
\ No newline at end of file
diff --git a/bsp/ht32/ht32f52352/SConscript b/bsp/ht32/ht32f52352/SConscript
new file mode 100644
index 00000000000..682f94215ca
--- /dev/null
+++ b/bsp/ht32/ht32f52352/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os #包含os库
+Import('RTT_ROOT') #导入RTT_ROOT对象(RTT_ROOT代表的是RT-Thread源码包)
+from building import * #把building模块的所有内容都导入到当前模块中
+
+cwd = GetCurrentDir() #获取当前路径,并将该路径信息保存到变量cwd中
+objs = [] #创建一个list型变量objs
+list = os.listdir(cwd) #得到当前目录下的所有子目录,并保存到变量list中
+
+for d in list: #for循环用d记录循环的次数,直到寻遍所有路径
+ path = os.path.join(cwd, d) #根据d获取到不同的路径
+ if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件
+ objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中
+
+Return('objs') #将objs返回出去
diff --git a/bsp/ht32/ht32f52352/SConstruct b/bsp/ht32/ht32f52352/SConstruct
new file mode 100644
index 00000000000..9f16ec63d24
--- /dev/null
+++ b/bsp/ht32/ht32f52352/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ht32_library = 'HT32_STD_5xxxx_FWLib'
+rtconfig.BSP_LIBRARY_TYPE = ht32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/ht32/ht32f52352/applications/SConscript b/bsp/ht32/ht32f52352/applications/SConscript
new file mode 100644
index 00000000000..9023be657ab
--- /dev/null
+++ b/bsp/ht32/ht32f52352/applications/SConscript
@@ -0,0 +1,21 @@
+#导入其他模块的变量
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#导入使用到的模块
+from building import *
+
+#获取当前目录的路径
+cwd = GetCurrentDir()
+
+#创建一个列表,用于保存需要使用到的C文件路径
+src = Glob('*c')
+
+#创建一个列表,用于保存需要包含的H文件路径
+path = [cwd]
+
+#创建一个组别
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+#返回创建好的组别
+Return('group')
\ No newline at end of file
diff --git a/bsp/ht32/ht32f52352/applications/main.c b/bsp/ht32/ht32f52352/applications/main.c
new file mode 100644
index 00000000000..3bcf7a1215c
--- /dev/null
+++ b/bsp/ht32/ht32f52352/applications/main.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#include
+#include
+#include "board.h"
+
+/* defined the led2 pin: pc14 */
+#define LED1_PIN GET_PIN(C, 14)
+/* defined the led3 pin: pc15 */
+#define LED2_PIN GET_PIN(C, 15)
+
+int main(void)
+{
+ rt_uint32_t speed = 200;
+ /* set led1 pin mode to output */
+ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+ /* set led2 pin mode to output */
+ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+ while (1)
+ {
+ rt_pin_write(LED1_PIN, PIN_LOW);
+ rt_pin_write(LED2_PIN, PIN_HIGH);
+ rt_thread_mdelay(speed);
+ rt_pin_write(LED1_PIN, PIN_HIGH);
+ rt_pin_write(LED2_PIN, PIN_LOW);
+ rt_thread_mdelay(speed);
+ }
+}
diff --git a/bsp/ht32/ht32f52352/board/Kconfig b/bsp/ht32/ht32f52352/board/Kconfig
new file mode 100644
index 00000000000..b12d8e56263
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/Kconfig
@@ -0,0 +1,77 @@
+menu "Hardware Drivers Config"
+
+config SOC_HT32F52352
+ bool
+ select SOC_SERIES_HT32F5
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default n
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default n
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_USART0
+ bool "Enable USART0"
+ default n
+
+ config BSP_USING_USART1
+ bool "Enable USART1"
+ default n
+
+ config BSP_USING_UART0
+ bool "Enable UART0"
+ default n
+
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI Bus"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI0
+ bool "Enable SPI0 Bus"
+ default n
+
+ config BSP_USING_SPI1
+ bool "Enable SPI1 Bus"
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C
+ bool "Enable I2C Bus"
+ default n
+ select RT_USING_I2C
+ if BSP_USING_I2C
+ config BSP_USING_I2C0
+ bool "Enable I2C0 Bus"
+ default n
+
+ config BSP_USING_I2C1
+ bool "Enable I2C1 Bus"
+ default n
+ endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/ht32/ht32f52352/board/SConscript b/bsp/ht32/ht32f52352/board/SConscript
new file mode 100644
index 00000000000..79eab7eced6
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/SConscript
@@ -0,0 +1,27 @@
+
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+src = Glob('src/*.c')
+
+startup_path_prefix = SDK_LIB
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s']
+
+path = [cwd]
+path = [cwd + '/inc']
+
+CPPDEFINES = ['USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
\ No newline at end of file
diff --git a/bsp/ht32/ht32f52352/board/inc/board.h b/bsp/ht32/ht32f52352/board/inc/board.h
new file mode 100644
index 00000000000..91d5c2d0a53
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/inc/board.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+#include "ht32.h"
+#include "ht32_msp.h"
+
+#ifdef BSP_USING_GPIO
+ #include "drv_gpio.h"
+#endif
+
+#ifdef BSP_USING_UART
+ #include "drv_usart.h"
+#endif
+
+#ifdef BSP_USING_SPI
+ #include "drv_spi.h"
+#endif
+
+#ifdef BSP_USING_I2C
+ #include "drv_i2c.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* whether use board external SRAM memory */
+#define HT32_EXT_SRAM 0
+#define HT32_EXT_SRAM_BEGIN 0x68000000
+#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024)
+
+/* internal sram memory size */
+#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE)
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+#define HEAP_END HT32_SRAM_END
+
+void rt_hw_board_clock_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/ht32/ht32f52352/board/inc/ht32_msp.h b/bsp/ht32/ht32f52352/board/inc/ht32_msp.h
new file mode 100644
index 00000000000..066add8d568
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/inc/ht32_msp.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-08 QT-one first version
+ */
+
+#ifndef __HT32_MSP_H__
+#define __HT32_MSP_H__
+
+#include
+#include "ht32.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* UART gpio */
+#ifdef BSP_USING_UART
+#ifdef BSP_USING_USART0
+#define HTCFG_USART0_IPN USART0
+
+#define _HTCFG_USART0_TX_GPIOX A
+#define _HTCFG_USART0_TX_GPION 2
+#define _HTCFG_USART0_RX_GPIOX A
+#define _HTCFG_USART0_RX_GPION 3
+
+#define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX)
+#define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX)
+#define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX)
+#define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION)
+
+#define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX)
+#define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX)
+#define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX)
+#define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION)
+
+#endif
+#ifdef BSP_USING_USART1
+
+#define HTCFG_USART1_IPN USART1
+
+#define _HTCFG_USART1_TX_GPIOX A
+#define _HTCFG_USART1_TX_GPION 4
+#define _HTCFG_USART1_RX_GPIOX A
+#define _HTCFG_USART1_RX_GPION 5
+
+#define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX)
+#define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX)
+#define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX)
+#define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION)
+
+#define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX)
+#define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX)
+#define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX)
+#define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION)
+
+#endif
+#ifdef BSP_USING_UART0
+
+#define HTCFG_UART0_IPN UART0
+
+#define _HTCFG_UART0_TX_GPIOX B
+#define _HTCFG_UART0_TX_GPION 2
+#define _HTCFG_UART0_RX_GPIOX B
+#define _HTCFG_UART0_RX_GPION 3
+
+#define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX)
+#define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX)
+#define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX)
+#define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION)
+
+#define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX)
+#define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX)
+#define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX)
+#define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION)
+
+#endif
+#ifdef BSP_USING_UART1
+
+#define HTCFG_UART1_IPN UART1
+
+#define _HTCFG_UART1_TX_GPIOX B
+#define _HTCFG_UART1_TX_GPION 4
+#define _HTCFG_UART1_RX_GPIOX B
+#define _HTCFG_UART1_RX_GPION 5
+
+#define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX)
+#define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX)
+#define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX)
+#define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION)
+
+#define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX)
+#define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX)
+#define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX)
+#define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION)
+
+#endif
+#endif
+
+/* SPI gpio */
+#ifdef BSP_USING_SPI
+#ifdef BSP_USING_SPI0
+
+#define HTCFG_SPI0_IPN SPI0
+
+#define _HTCFG_SPI0_SCK_GPIOX C
+#define _HTCFG_SPI0_SCK_GPION 0
+
+#define _HTCFG_SPI0_MISO_GPIOX A
+#define _HTCFG_SPI0_MISO_GPION 11
+
+#define _HTCFG_SPI0_MOSI_GPIOX A
+#define _HTCFG_SPI0_MOSI_GPION 9
+
+#define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX)
+#define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX)
+#define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION)
+
+#define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX)
+#define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX)
+#define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION)
+
+#define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX)
+#define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX)
+#define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION)
+
+#endif
+#ifdef BSP_USING_SPI1
+
+#define HTCFG_SPI1_IPN SPI1
+
+#define _HTCFG_SPI1_SCK_GPIOX A
+#define _HTCFG_SPI1_SCK_GPION 15
+
+#define _HTCFG_SPI1_MISO_GPIOX B
+#define _HTCFG_SPI1_MISO_GPION 1
+
+#define _HTCFG_SPI1_MOSI_GPIOX B
+#define _HTCFG_SPI1_MOSI_GPION 0
+
+#define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX)
+#define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX)
+#define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION)
+
+#define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX)
+#define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX)
+#define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION)
+
+#define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX)
+#define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX)
+#define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION)
+
+#endif
+#endif
+
+/* I2C gpio */
+#ifdef BSP_USING_I2C
+#ifdef BSP_USING_I2C0
+
+#define HTCFG_I2C0_IPN I2C0
+
+#define _HTCFG_I2C0_SCL_GPIOX C
+#define _HTCFG_I2C0_SCL_GPION 12
+
+#define _HTCFG_I2C0_SDA_GPIOX C
+#define _HTCFG_I2C0_SDA_GPION 13
+
+#define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX)
+#define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX)
+#define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION)
+
+#define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX)
+#define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX)
+#define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION)
+
+#endif
+#ifdef BSP_USING_I2C1
+
+#define HTCFG_I2C1_IPN I2C1
+
+#define _HTCFG_I2C1_SCL_GPIOX A
+#define _HTCFG_I2C1_SCL_GPION 0
+
+#define _HTCFG_I2C1_SDA_GPIOX A
+#define _HTCFG_I2C1_SDA_GPION 1
+
+#define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX)
+#define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX)
+#define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION)
+
+#define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX)
+#define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX)
+#define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION)
+
+#endif
+#endif
+
+void ht32_usart_gpio_init(void *instance);
+void ht32_spi_gpio_init(void *instance);
+void ht32_i2c_gpio_init(void *instance);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HT32_MSP_H__ */
diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h
new file mode 100644
index 00000000000..a512579519a
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h
@@ -0,0 +1,453 @@
+/*********************************************************************************************************//**
+ * @file IP/Example/ht32f5xxxx_01_usbdconf.h
+ * @version $Rev:: 2390 $
+ * @date $Date:: 2017-12-21 #$
+ * @brief The configuration file of USB Device Driver.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ * other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ * other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ * the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * Copyright (C) Holtek Semiconductor Inc. All rights reserved
+ ************************************************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32F5XXXX_01_USBDCONF_H
+#define __HT32F5XXXX_01_USBDCONF_H
+
+// Enter Low Power mode when Suspended
+#define USBDCORE_ENABLE_LOW_POWER (0)
+//
+
+#if (USBDCORE_ENABLE_LOW_POWER == 1)
+ #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
+#else
+ #define USBDCore_LowPower(...)
+#endif
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* USB Interrupt Enable */
+/*----------------------------------------------------------------------------------------------------------*/
+// USB Interrupt Setting (UIER)
+// USB Global Interrupt Enable (UGIE) (Default)
+// Start Of Frame Interrupt Enable (SOFIE)
+// USB Reset Interrupt Enable (URSTIE) (Default)
+// Resume Interrupt Enable (RSMIE) (Default)
+// Suspend Interrupt Enable (SUSPIE) (Default)
+// Expected Start of Frame Interrupt Enable (ESOFE)
+// Control Endpoint Interrupt Enable (EP0IE) (Default)
+// Endpoint1 Interrupt Enable (EP1IE)
+// Endpoint2 Interrupt Enable (EP2IE)
+// Endpoint3 Interrupt Enable (EP3IE)
+// Endpoint4 Interrupt Enable (EP4IE)
+// Endpoint5 Interrupt Enable (EP5IE)
+// Endpoint6 Interrupt Enable (EP6IE)
+// Endpoint7 Interrupt Enable (EP7IE)
+#define _UIER (0x011D)
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint0 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Control Endpoint0 Configuration
+// Endpoint Buffer Length (EPLEN)
+// <8=> 8 bytes
+// <16=> 16 bytes
+// <32=> 32 bytes
+// <64=> 64 bytes
+ /* Maximum: 64 Bytes */
+#define _EP0LEN (64)
+
+
+// Control Endpoint0 Interrupt Enable Settings (EP0IER)
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+// SETUP Token Packet Received Interrupt Enable (STRXIE)
+// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
+// SETUP Data Error Interrupt Enable (SDERIE)
+// Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
+#define _EP0_IER (0x212)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint1 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint1 Configuration
+#define _EP1_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP1_CFG_EPADR (1)
+
+// Endpoint Enable (EPEN)
+#define _EP1_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP1_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP1_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP1LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP1_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint2 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint2 Configuration
+#define _EP2_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP2_CFG_EPADR (2)
+
+// Endpoint Enable (EPEN)
+#define _EP2_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP2_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP2_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP2LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP2_IER (0x002)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint3 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint3 Configuration
+#define _EP3_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP3_CFG_EPADR (3)
+
+// Endpoint Enable (EPEN)
+#define _EP3_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP3_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP3_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP3LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP3_IER (0x10)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint4 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint4 Configuration
+#define _EP4_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP4_CFG_EPADR (4)
+
+// Endpoint Enable (EPEN)
+#define _EP4_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP4_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP4_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP4LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP4_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP4_IER (0x02)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint5 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint5 Configuration
+#define _EP5_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP5_CFG_EPADR (5)
+
+// Endpoint Enable (EPEN)
+#define _EP5_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP5_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP5_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP5LEN_TMP (8)
+
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP5_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP5_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint6 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint6 Configuration
+#define _EP6_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP6_CFG_EPADR (6)
+
+// Endpoint Enable (EPEN)
+#define _EP6_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP6_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP6_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP6LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP6_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP6_IER (0x02)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint7 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint7 Configuration
+#define _EP7_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+#define _EP7_CFG_EPADR (7)
+
+// Endpoint Enable (EPEN)
+#define _EP7_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP7_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP7_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP7LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP7_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP7_IER (0x10)
+//
+//
+
+#endif
diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h
new file mode 100644
index 00000000000..272e8cd127b
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h
@@ -0,0 +1,569 @@
+/*********************************************************************************************************//**
+ * @file IP/Example/ht32f5xxxx_02_usbdconf.h
+ * @version $Rev:: 5656 $
+ * @date $Date:: 2021-11-24 #$
+ * @brief The configuration file of USB Device Driver.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ * other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ * other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ * the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * Copyright (C) Holtek Semiconductor Inc. All rights reserved
+ ************************************************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32F5XXXX_02_USBDCONF_H
+#define __HT32F5XXXX_02_USBDCONF_H
+
+// Enter Low Power mode when Suspended
+#define USBDCORE_ENABLE_LOW_POWER (0)
+//
+
+#if (USBDCORE_ENABLE_LOW_POWER == 1)
+ #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE)
+#else
+ #define USBDCore_LowPower(...)
+#endif
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* USB Interrupt Enable */
+/*----------------------------------------------------------------------------------------------------------*/
+// USB Interrupt Setting (UIER)
+// USB Global Interrupt Enable (UGIE) (Default)
+// Start Of Frame Interrupt Enable (SOFIE)
+// USB Reset Interrupt Enable (URSTIE) (Default)
+// Resume Interrupt Enable (RSMIE) (Default)
+// Suspend Interrupt Enable (SUSPIE) (Default)
+// Expected Start of Frame Interrupt Enable (ESOFE)
+// Control Endpoint Interrupt Enable (EP0IE) (Default)
+// Endpoint1 Interrupt Enable (EP1IE)
+// Endpoint2 Interrupt Enable (EP2IE)
+// Endpoint3 Interrupt Enable (EP3IE)
+// Endpoint4 Interrupt Enable (EP4IE)
+// Endpoint5 Interrupt Enable (EP5IE)
+// Endpoint6 Interrupt Enable (EP6IE)
+// Endpoint7 Interrupt Enable (EP7IE)
+// Endpoint8 Interrupt Enable (EP8IE)
+// Endpoint9 Interrupt Enable (EP9IE)
+#define _UIER (0x011D)
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint0 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Control Endpoint0 Configuration
+// Endpoint Buffer Length (EPLEN)
+// <8=> 8 bytes
+// <16=> 16 bytes
+// <32=> 32 bytes
+// <64=> 64 bytes
+ /* Maximum: 64 Bytes */
+#define _EP0LEN (64)
+
+
+// Control Endpoint0 Interrupt Enable Settings (EP0IER)
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+// SETUP Token Packet Received Interrupt Enable (STRXIE)
+// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default)
+// SETUP Data Error Interrupt Enable (SDERIE)
+// Zero Length Data Packet Received Interrupt Enable (ZLRXIE)
+#define _EP0_IER (0x212)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint1 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint1 Configuration
+#define _EP1_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP1_CFG_EPADR (1)
+
+// Endpoint Enable (EPEN)
+#define _EP1_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP1_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP1_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP1LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP1_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint2 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint2 Configuration
+#define _EP2_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP2_CFG_EPADR (2)
+
+// Endpoint Enable (EPEN)
+#define _EP2_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP2_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP2_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP2LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP2_IER (0x002)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint3 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint3 Configuration
+#define _EP3_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP3_CFG_EPADR (3)
+
+// Endpoint Enable (EPEN)
+#define _EP3_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP3_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP3_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP3LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP3_IER (0x10)
+//
+//
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint4 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint4 Configuration
+#define _EP4_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP4_CFG_EPADR (4)
+
+// Endpoint Enable (EPEN)
+#define _EP4_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP4_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP4_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP4LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP4_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP4_IER (0x02)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint5 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint5 Configuration
+#define _EP5_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP5_CFG_EPADR (5)
+
+// Endpoint Enable (EPEN)
+#define _EP5_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP5_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP5_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP5LEN_TMP (8)
+
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP5_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP5_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint6 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint6 Configuration
+#define _EP6_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP6_CFG_EPADR (6)
+
+// Endpoint Enable (EPEN)
+#define _EP6_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP6_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP6_CFG_EPDIR (0)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP6LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP6_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP6_IER (0x02)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint7 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint7 Configuration
+#define _EP7_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP7_CFG_EPADR (7)
+
+// Endpoint Enable (EPEN)
+#define _EP7_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <1=> Isochronous
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP7_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP7_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4>
+ /* Maximum: 1000 Bytes */
+#define _EP7LEN_TMP (8)
+
+// Single/Double Buffer Selection (SDBS)
+// <0=> Single Buffer
+// <1=> Double Buffer
+#define _EP7_CFG_SDBS (0)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP7_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint8 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint8 Configuration
+#define _EP8_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP8_CFG_EPADR (8)
+
+// Endpoint Enable (EPEN)
+#define _EP8_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP8_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP8_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP8LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP8_IER (0x10)
+//
+//
+
+
+/*----------------------------------------------------------------------------------------------------------*/
+/* Endpoint9 Configuration Setting */
+/*----------------------------------------------------------------------------------------------------------*/
+// Endpoint9 Configuration
+#define _EP9_ENABLE (0)
+
+// Endpoint Address (EPADR)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+#define _EP9_CFG_EPADR (9)
+
+// Endpoint Enable (EPEN)
+#define _EP9_CFG_EPEN_TMP (1)
+
+// Endpoint Transfer Type
+// <2=> Bulk
+// <3=> Interrupt
+#define _EP9_TYPR (3)
+
+// Endpoint Direction (EPDIR)
+// <1=> IN
+// <0=> OUT
+#define _EP9_CFG_EPDIR (1)
+
+// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4>
+ /* Maximum: 64 Bytes */
+#define _EP9LEN_TMP (8)
+
+// Endpoint Interrupt Enable Settings (EPIER)
+// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1>
+// OUT Token Packet Received Interrupt Enable (OTRXIE)
+// OUT Data Packet Received Interrupt Enable (ODRXIE)
+// OUT Data Buffer Overrun Interrupt Enable (ODOVIE)
+// IN Token Packet Received Interrupt Enable (ITRXIE)
+// IN Data Packet Transmitted Interrupt Enable (IDTXIE)
+// NAK Transmitted Interrupt Enable (NAKIE)
+// STALL Transmitted Interrupt Enable (STLIE)
+// USB Error Interrupt Enable (UERIE)
+#define _EP9_IER (0x10)
+//
+//
+
+#endif
diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h
new file mode 100644
index 00000000000..c78b9bb75d7
--- /dev/null
+++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h
@@ -0,0 +1,556 @@
+/*********************************************************************************************************//**
+ * @file IP/Example/ht32f5xxxx_conf.h
+ * @version $Rev:: 7109 $
+ * @date $Date:: 2023-08-10 #$
+ * @brief Library configuration file.
+ *************************************************************************************************************
+ * @attention
+ *
+ * Firmware Disclaimer Information
+ *
+ * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
+ * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
+ * other intellectual property laws.
+ *
+ * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
+ * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
+ * other than HOLTEK and the customer.
+ *
+ * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
+ * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
+ * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
+ * the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
+ *
+ * Copyright (C) Holtek Semiconductor Inc. All rights reserved
+ ************************************************************************************************************/
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+
+/* Define to prevent recursive inclusion -------------------------------------------------------------------*/
+#ifndef __HT32F5XXXX_CONF_H
+#define __HT32F5XXXX_CONF_H
+
+/* Exported constants --------------------------------------------------------------------------------------*/
+
+#define RETARGET_USB 1
+#define RETARGET_SYSLOG 2
+#define RETARGET_COM1 10
+#define RETARGET_COM2 11
+#define RETARGET_USART0 12
+#define RETARGET_USART1 13
+#define RETARGET_UART0 14
+#define RETARGET_UART1 15
+#define RETARGET_UART2 16
+#define RETARGET_UART3 17
+
+
+/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */
+/*
+// Enable Retarget
+// Retarget Port
+// <1=> USB Virtual COM
+// <2=> Syslog
+// <10=> COM1
+// <11=> COM2
+// <12=> USART0
+// <13=> USART1
+// <14=> UART0
+// <15=> UART1
+// <16=> UART2
+// <17=> UART3
+// Enable Auto Return
+// Auto Return function adds "\r" before "\n" automatically when print message by Retarget.
+*/
+#define _RETARGET 1
+#define RETARGET_PORT 10
+#define _AUTO_RETURN 0
+
+#ifndef AUTO_RETURN
+#if (_AUTO_RETURN == 1)
+#define AUTO_RETURN
+#endif
+#endif
+
+/* Enable Interrupt Mode for UxART Retarget
+// Retarget COM/UxART Setting
+// UxART Baudrate
+// Enable Interrupt Mode for UxART Tx Retarget
+// Define UxARTn_IRQHandler By Retarget (ht32_serial.c)
+// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler.
+// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable.
+// Tx Buffer Length (in byte)
+//
+*/
+#define RETARGET_UxART_BAUDRATE 115200
+#define RETARGET_INT_MODE 0
+#define RETARGET_DEFINE_HANDLER 1
+#define RETARGET_INT_BUFFER_SIZE 64
+
+#if (_RETARGET == 1)
+#if (RETARGET_PORT == RETARGET_USB)
+ #define RETARGET_IS_USB
+// Retarget USB Virtual COM Setting
+// Communication (Interrupt IN)
+// <1=> Endpoint 1
+// <2=> Endpoint 2
+// <3=> Endpoint 3
+// <4=> Endpoint 4
+// <5=> Endpoint 5
+// <6=> Endpoint 6
+// <7=> Endpoint 7
+// Data Rx (Bulk OUT)
+// <1=> Endpoint 1
+// <2=> Endpoint 2
+// <3=> Endpoint 3
+// <4=> Endpoint 4
+// <5=> Endpoint 5
+// <6=> Endpoint 6
+// <7=> Endpoint 7
+// Data Tx (Bulk IN)
+// <1=> Endpoint 1
+// <2=> Endpoint 2
+// <3=> Endpoint 3
+// <4=> Endpoint 4
+// <5=> Endpoint 5
+// <6=> Endpoint 6
+// <7=> Endpoint 7
+// Communication Endpoint Buffer Length (in byte) <4-64:4>
+// Data Rx Endpoint Buffer Length (in byte) <4-64:4>
+// Data Tx Endpoint Buffer Length (in byte) <4-64:4>
+// Rx Buffer Length (in byte) <64-1024:4>
+// Tx Buffer Length (in byte) <1-63:1>
+// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
+// USB Tx Mode (BULK IN)
+// <0=> Block Mode (Wait until both USB and terminal software are ready)
+// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready)
+// Enable HSI Auto Trim By USB Function
+// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source).
+ #define RETARGET_CTRL_EPT (5)
+ #define RETARGET_RX_EPT (6)
+ #define RETARGET_TX_EPT (7)
+ #define RETARGET_CTRL_EPTLEN (8)
+ #define RETARGET_RX_EPTLEN (64)
+ #define RETARGET_TX_EPTLEN (64)
+ #define RETARGET_BUFFER_SIZE (64)
+ #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1.
+ #define RETARGET_USB_MODE (0)
+ #define RETARGET_HSI_ATM (1)
+//
+#elif (RETARGET_PORT == RETARGET_COM1)
+ #define RETARGET_COM_PORT COM1
+ #define RETARGET_USART_PORT COM1_PORT
+ #define RETARGET_UART_IRQn COM1_IRQn
+ #define RETARGET_UART_IRQHandler COM1_IRQHandler
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_COM2)
+ #define RETARGET_COM_PORT COM2
+ #define RETARGET_USART_PORT COM2_PORT
+ #define RETARGET_UART_IRQn COM2_IRQn
+ #define RETARGET_UART_IRQHandler COM2_IRQHandler
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_USART0)
+ #define RETARGET_UxART_IPN USART0
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_USART1)
+ #define RETARGET_UxART_IPN USART1
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_UART0)
+ #define RETARGET_UxART_IPN UART0
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_UART1)
+ #define RETARGET_UxART_IPN UART1
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_UART2)
+ #define RETARGET_UxART_IPN UART2
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#elif (RETARGET_PORT == RETARGET_UART3)
+ #define RETARGET_UxART_IPN UART3
+ #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN)
+ #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn)
+ #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler)
+ #define RETARGET_IS_UART
+#endif
+ extern void RETARGET_Configuration(void);
+#else
+ #define RETARGET_Configuration(...)
+ #undef printf
+ #undef getchar
+ #define printf(...)
+ #define getchar() (0)
+#endif
+
+#if (RETARGET_DEFINE_HANDLER == 0)
+#undef RETARGET_UART_IRQHandler
+#endif
+
+/*
+// Enable HT32 Time Function
+// Provide "Time_GetTick()" and "Time_Dealy()" functions.
+
+// Timer Selection
+// <0=> BFTM0
+// <1=> BFTM1
+// <2=> SCTM0
+// <3=> SCTM1
+// <4=> SCTM2
+// <5=> SCTM3
+// <6=> PWM0
+// <7=> PWM1
+// <8=> PWM2
+// <9=> GPTM0
+// <10=> GPTM1
+// <11=> MCTM0
+
+// Timer Clock Setting
+//
+// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
+// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV)
+// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
+
+// -- Core Clock Setting (CK_AHB)
+// HTCFG_TIME_CLKSEL
+// 0 = Default Maximum (LIBCFG_MAX_SPEED)
+// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL)
+// <0=> Default Maximum (LIBCFG_MAX_SPEED)
+// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL)
+
+// -- Core Clock Manual Input (Hz)
+// HTCFG_TIME_CLK_MANUAL
+// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1)
+
+// -- APB Peripheral Clock Prescaler
+// HTCFG_TIME_PCLK_DIV
+// <0=> /1
+// <1=> /2
+// <2=> /4
+// <3=> /8
+
+// Time Tick (Hz, not applicable for BFTM) <1-1000000:100>
+// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM.
+*/
+#if (0) // Enable HT32 Time Function
+#define HTCFG_TIME_IPSEL (0)
+#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC)
+#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input)
+#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8)
+#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM
+#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM.
+/*
+
+ Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler)
+ HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV)
+ where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL)
+
+ Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time)
+ Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second
+ (Interrupt Time is not applicable for BFTM)
+
+ Example: 32-bit BFTM with 48 MHz Timer Clock
+ HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000
+ Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second)
+ BFTM do not use interrupt
+
+ Example: 16-bit GPTM with 1 ms tick
+ HTCFG_TIME_TICKHZ = 1000 (Hz)
+ HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick)
+ Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day)
+ Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second)
+*/
+#endif
+/*
+//
+*/
+
+/* !!! NOTICE !!!
+ * How to adjust the value of High Speed External oscillator (HSE)?
+ The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h".
+ If your board uses a different HSE speed, please add a new compiler preprocessor
+ C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE,
+ or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file (this file).
+*/
+/*
+// Enable User Define HSE Value
+// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h".
+// HSE Value (Hz)
+*/
+#if (0)
+#define HSE_VALUE 16000000
+#endif
+/*
+//
+*/
+
+/*
+// Enable CKOUT Function
+*/
+#define ENABLE_CKOUT 0
+
+/*
+// Enable Get CK_ADC of "CKCU_GetClocksFrequency()"
+// Enable ADC0_Freq and ADC1_Freq of the "CKCU_GetClocksFrequency()" function. It required the division calculation (by C Library) and increased the code size.
+*/
+#define HT32_LIB_ENABLE_GET_CK_ADC 0
+
+/* The DEBUG definition to enter debug mode for library */
+/*
+// Library Debug Mode
+*/
+#define HT32_LIB_DEBUG 0
+
+
+/* Enable/disable the specific peripheral inclusion */
+
+// Library Inclusion Configuration
+/* ADC -----------------------------------------------------------------------------------------------------*/
+/*
+// ADC Library
+*/
+#define _ADC 1
+
+/* AES -----------------------------------------------------------------------------------------------------*/
+/*
+// AES Library
+*/
+#define _AES 1
+
+/* BFTM ----------------------------------------------------------------------------------------------------*/
+/*
+// BFTM Library
+*/
+#define _BFTM 1
+
+/* CAN -----------------------------------------------------------------------------------------------------*/
+/*
+// CAN Library
+*/
+#define _CAN 1
+
+/* Clock Control -------------------------------------------------------------------------------------------*/
+/*
+// Clock Control Library
+*/
+#define _CKCU 1
+
+/* Comparator ----------------------------------------------------------------------------------------------*/
+/*
+// Comparator Library
+*/
+#define _CMP 1
+
+/* CRC -----------------------------------------------------------------------------------------------------*/
+/*
+// CRC Library
+*/
+#define _CRC 1
+
+/* DAC -----------------------------------------------------------------------------------------------------*/
+/*
+// DAC Library
+*/
+#define _DAC 1
+
+/* DAC Dual 16-bit -----------------------------------------------------------------------------------------*/
+/*
+// DAC_Dual16 Library
+*/
+#define _DAC_DUAL16 1
+
+/* DIV -----------------------------------------------------------------------------------------------------*/
+/*
+// DIV Library
+*/
+#define _DIV 1
+
+/* EBI -----------------------------------------------------------------------------------------------------*/
+/*
+// EBI Library
+*/
+#define _EBI 1
+
+/* EXTI ----------------------------------------------------------------------------------------------------*/
+/*
+// EXTI Library
+*/
+#define _EXTI 1
+
+/* Flash ---------------------------------------------------------------------------------------------------*/
+/*
+// Flash Library
+*/
+#define _FLASH 1
+
+/* GPIO ----------------------------------------------------------------------------------------------------*/
+/*
+// GPIO Library
+*/
+#define _GPIO 1
+
+/* GPTM ----------------------------------------------------------------------------------------------------*/
+/*
+// GPTM Library
+*/
+#define _GPTM 1
+
+/* I2C -----------------------------------------------------------------------------------------------------*/
+/*
+// I2C Library
+*/
+#define _I2C 1
+
+/* I2S -----------------------------------------------------------------------------------------------------*/
+/*
+// I2S Library
+*/
+#define _I2S 1
+
+/* LCD -----------------------------------------------------------------------------------------------------*/
+/*
+// LCD Library
+*/
+#define _LCD 1
+
+/* LEDC ----------------------------------------------------------------------------------------------------*/
+/*
+// LEDC Library
+*/
+#define _LEDC 1
+
+/* MCTM ----------------------------------------------------------------------------------------------------*/
+/*
+// MCTM Library
+*/
+#define _MCTM 1
+
+/* MIDI ----------------------------------------------------------------------------------------------------*/
+/*
+// MIDI Library
+*/
+#define _MIDI 1
+
+/* OPA -----------------------------------------------------------------------------------------------------*/
+/*
+// OPA
+*/
+#define _OPA 1
+
+/* PDMA ----------------------------------------------------------------------------------------------------*/
+/*
+// PDMA Library
+*/
+#define _PDMA 1
+
+/* PWM -----------------------------------------------------------------------------------------------------*/
+/*
+// PWM Library
+*/
+#define _PWM 1
+
+/* PWRCU ---------------------------------------------------------------------------------------------------*/
+/*
+// PWRCU Library
+*/
+#define _PWRCU 1
+
+/* RSTCU ---------------------------------------------------------------------------------------------------*/
+/*
+// RSTCU Library
+*/
+#define _RSTCU 1
+
+/* RTC -----------------------------------------------------------------------------------------------------*/
+/*
+// RTC Library
+*/
+#define _RTC 1
+
+/* SCI -----------------------------------------------------------------------------------------------------*/
+/*
+// SCI Library
+*/
+#define _SCI 1
+
+/* SCTM ----------------------------------------------------------------------------------------------------*/
+/*
+// SCTM Library
+*/
+#define _SCTM 1
+
+/* SLED ----------------------------------------------------------------------------------------------------*/
+/*
+// SLED Library
+*/
+#define _SLED 1
+
+/* SPI -----------------------------------------------------------------------------------------------------*/
+/*
+// SPI Library
+*/
+#define _SPI 1
+
+/* TKEY ----------------------------------------------------------------------------------------------------*/
+/*
+// TKEY Library
+*/
+#define _TKEY 1
+
+/* USART ---------------------------------------------------------------------------------------------------*/
+/*
+// USART/UART Library
+*/
+#define _USART 1
+
+/* USBD ----------------------------------------------------------------------------------------------------*/
+/*
+// USB Library
+*/
+#define _USB 1
+
+/* WDT -----------------------------------------------------------------------------------------------------*/
+/*
+// WDT Library
+*/
+#define _WDT 1
+
+/* Misc ----------------------------------------------------------------------------------------------------*/
+/*
+// Misc Library
+*/
+#define _MISC 1
+
+/* Serial --------------------------------------------------------------------------------------------------*/
+/*
+//