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ppu.cpp
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ppu.cpp
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/* FCE Ultra - NES/Famicom Emulator
*
* Copyright notice for this file:
* Copyright (C) 1998 BERO
* Copyright (C) 2003 Xodnizel
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "types.h"
#include "x6502.h"
#include "fceu.h"
#include "ppu.h"
#include "nsf.h"
#include "sound.h"
#include "file.h"
#include "utils/endian.h"
#include "utils/memory.h"
#include "cart.h"
#include "palette.h"
#include "state.h"
#include "video.h"
#include "input.h"
#include "driver.h"
#include "debug.h"
#include <cstring>
#include <cstdio>
#include <cstdlib>
#define VBlankON (PPU[0] & 0x80) //Generate VBlank NMI
#define Sprite16 (PPU[0] & 0x20) //Sprites 8x16/8x8
#define BGAdrHI (PPU[0] & 0x10) //BG pattern adr $0000/$1000
#define SpAdrHI (PPU[0] & 0x08) //Sprite pattern adr $0000/$1000
#define INC32 (PPU[0] & 0x04) //auto increment 1/32
#define SpriteON (PPU[1] & 0x10) //Show Sprite
#define ScreenON (PPU[1] & 0x08) //Show screen
#define PPUON (PPU[1] & 0x18) //PPU should operate
#define GRAYSCALE (PPU[1] & 0x01) //Grayscale (AND palette entries with 0x30)
#define SpriteLeft8 (PPU[1] & 0x04)
#define BGLeft8 (PPU[1] & 0x02)
#define PPU_status (PPU[2])
#define READPALNOGS(ofs) (PALRAM[(ofs)])
#define READPAL(ofs) (PALRAM[(ofs)] & (GRAYSCALE ? 0x30 : 0xFF))
#define READUPAL(ofs) (UPALRAM[(ofs)] & (GRAYSCALE ? 0x30 : 0xFF))
static void FetchSpriteData(void);
static void RefreshLine(int lastpixel);
static void RefreshSprites(void);
static void CopySprites(uint8 *target);
static void Fixit1(void);
static uint32 ppulut1[256];
static uint32 ppulut2[256];
static uint32 ppulut3[128];
static bool new_ppu_reset = false;
int test = 0;
template<typename T, int BITS>
struct BITREVLUT {
T* lut;
BITREVLUT() {
int bits = BITS;
int n = 1 << BITS;
lut = new T[n];
int m = 1;
int a = n >> 1;
int j = 2;
lut[0] = 0;
lut[1] = a;
while (--bits) {
m <<= 1;
a >>= 1;
for (int i = 0; i < m; i++)
lut[j++] = lut[i] + a;
}
}
T operator[](int index) {
return lut[index];
}
};
BITREVLUT<uint8, 8> bitrevlut;
struct PPUSTATUS {
int32 sl;
int32 cycle, end_cycle;
};
struct SPRITE_READ {
int32 num;
int32 count;
int32 fetch;
int32 found;
int32 found_pos[8];
int32 ret;
int32 last;
int32 mode;
void reset() {
num = count = fetch = found = ret = last = mode = 0;
found_pos[0] = found_pos[1] = found_pos[2] = found_pos[3] = 0;
found_pos[4] = found_pos[5] = found_pos[6] = found_pos[7] = 0;
}
void start_scanline() {
num = 1;
found = 0;
fetch = 1;
count = 0;
last = 64;
mode = 0;
found_pos[0] = found_pos[1] = found_pos[2] = found_pos[3] = 0;
found_pos[4] = found_pos[5] = found_pos[6] = found_pos[7] = 0;
}
};
//doesn't need to be savestated as it is just a reflection of the current position in the ppu loop
PPUPHASE ppuphase;
//this needs to be savestated since a game may be trying to read from this across vblanks
SPRITE_READ spr_read;
//definitely needs to be savestated
uint8 idleSynch = 1;
//uses the internal counters concept at http:https://nesdev.icequake.net/PPU%20addressing.txt
struct PPUREGS {
//normal clocked regs. as the game can interfere with these at any time, they need to be savestated
uint32 fv; //3
uint32 v; //1
uint32 h; //1
uint32 vt; //5
uint32 ht; //5
//temp unlatched regs (need savestating, can be written to at any time)
uint32 _fv, _v, _h, _vt, _ht;
//other regs that need savestating
uint32 fh; //3 (horz scroll)
uint32 s; //1 ($2000 bit 4: "Background pattern table address (0: $0000; 1: $1000)")
//other regs that don't need saving
uint32 par; //8 (sort of a hack, just stored in here, but not managed by this system)
//cached state data. these are always reset at the beginning of a frame and don't need saving
//but just to be safe, we're gonna save it
PPUSTATUS status;
void reset() {
fv = v = h = vt = ht = 0;
fh = par = s = 0;
_fv = _v = _h = _vt = _ht = 0;
status.cycle = 0;
status.end_cycle = 341;
status.sl = 241;
}
void install_latches() {
fv = _fv;
v = _v;
h = _h;
vt = _vt;
ht = _ht;
}
void install_h_latches() {
ht = _ht;
h = _h;
}
void clear_latches() {
_fv = _v = _h = _vt = _ht = 0;
fh = 0;
}
void increment_hsc() {
//The first one, the horizontal scroll counter, consists of 6 bits, and is
//made up by daisy-chaining the HT counter to the H counter. The HT counter is
//then clocked every 8 pixel dot clocks (or every 8/3 CPU clock cycles).
ht++;
h += (ht >> 5);
ht &= 31;
h &= 1;
}
void increment_vs() {
fv++;
int fv_overflow = (fv >> 3);
vt += fv_overflow;
vt &= 31; //fixed tecmo super bowl
if (vt == 30 && fv_overflow == 1) { //caution here (only do it at the exact instant of overflow) fixes p'radikus conflict
v++;
vt = 0;
}
fv &= 7;
v &= 1;
}
uint32 get_ntread() {
return 0x2000 | (v << 0xB) | (h << 0xA) | (vt << 5) | ht;
}
uint32 get_2007access() {
return ((fv & 3) << 0xC) | (v << 0xB) | (h << 0xA) | (vt << 5) | ht;
}
//The PPU has an internal 4-position, 2-bit shifter, which it uses for
//obtaining the 2-bit palette select data during an attribute table byte
//fetch. To represent how this data is shifted in the diagram, letters a..c
//are used in the diagram to represent the right-shift position amount to
//apply to the data read from the attribute data (a is always 0). This is why
//you only see bits 0 and 1 used off the read attribute data in the diagram.
uint32 get_atread() {
return 0x2000 | (v << 0xB) | (h << 0xA) | 0x3C0 | ((vt & 0x1C) << 1) | ((ht & 0x1C) >> 2);
}
//address line 3 relates to the pattern table fetch occuring (the PPU always makes them in pairs).
uint32 get_ptread() {
return (s << 0xC) | (par << 0x4) | fv;
}
void increment2007(bool rendering, bool by32) {
if (rendering)
{
//don't do this:
//if (by32) increment_vs();
//else increment_hsc();
//do this instead:
increment_vs(); //yes, even if we're moving by 32
return;
}
//If the VRAM address increment bit (2000.2) is clear (inc. amt. = 1), all the
//scroll counters are daisy-chained (in the order of HT, VT, H, V, FV) so that
//the carry out of each counter controls the next counter's clock rate. The
//result is that all 5 counters function as a single 15-bit one. Any access to
//2007 clocks the HT counter here.
//
//If the VRAM address increment bit is set (inc. amt. = 32), the only
//difference is that the HT counter is no longer being clocked, and the VT
//counter is now being clocked by access to 2007.
if (by32) {
vt++;
} else {
ht++;
vt += (ht >> 5) & 1;
}
h += (vt >> 5);
v += (h >> 1);
fv += (v >> 1);
ht &= 31;
vt &= 31;
h &= 1;
v &= 1;
fv &= 7;
}
void debug_log()
{
FCEU_printf("ppur: fv(%d), v(%d), h(%d), vt(%d), ht(%d)\n",fv,v,h,vt,ht);
FCEU_printf(" _fv(%d), _v(%d), _h(%d), _vt(%d), _ht(%d)\n",_fv,_v,_h,_vt,_ht);
FCEU_printf(" fh(%d), s(%d), par(%d)\n",fh,s,par);
FCEU_printf(" .status cycle(%d), end_cycle(%d), sl(%d)\n",status.cycle,status.end_cycle,status.sl);
}
} ppur;
int newppu_get_scanline() { return ppur.status.sl; }
int newppu_get_dot() { return ppur.status.cycle; }
void newppu_hacky_emergency_reset()
{
if(ppur.status.end_cycle == 0)
ppur.reset();
}
static void makeppulut(void) {
int x;
int y;
int cc, xo, pixel;
for (x = 0; x < 256; x++) {
ppulut1[x] = 0;
for (y = 0; y < 8; y++)
ppulut1[x] |= ((x >> (7 - y)) & 1) << (y * 4);
ppulut2[x] = ppulut1[x] << 1;
}
for (cc = 0; cc < 16; cc++) {
for (xo = 0; xo < 8; xo++) {
ppulut3[xo | (cc << 3)] = 0;
for (pixel = 0; pixel < 8; pixel++) {
int shiftr;
shiftr = (pixel + xo) / 8;
shiftr *= 2;
ppulut3[xo | (cc << 3)] |= ((cc >> shiftr) & 3) << (2 + pixel * 4);
}
}
}
}
static int ppudead = 1;
static int kook = 0;
int fceuindbg = 0;
//mbg 6/23/08
//make the no-bg fill color configurable
//0xFF shall indicate to use palette[0]
uint8 gNoBGFillColor = 0xFF;
int MMC5Hack = 0;
uint32 MMC5HackVROMMask = 0;
uint8 *MMC5HackExNTARAMPtr = 0;
uint8 *MMC5HackVROMPTR = 0;
uint8 MMC5HackCHRMode = 0;
uint8 MMC5HackSPMode = 0;
uint8 MMC50x5130 = 0;
uint8 MMC5HackSPScroll = 0;
uint8 MMC5HackSPPage = 0;
int PEC586Hack = 0;
int QTAIHack = 0;
uint8 QTAINTRAM[2048];
uint8 qtaintramreg;
uint8 VRAMBuffer = 0, PPUGenLatch = 0;
uint8 *vnapage[4];
uint8 PPUNTARAM = 0;
uint8 PPUCHRRAM = 0;
//Color deemphasis emulation. Joy...
static uint8 deemp = 0;
static int deempcnt[8];
void (*GameHBIRQHook)(void), (*GameHBIRQHook2)(void);
void (*PPU_hook)(uint32 A);
uint8 vtoggle = 0;
uint8 XOffset = 0;
uint8 SpriteDMA = 0; // $4014 / Writing $xx copies 256 bytes by reading from $xx00-$xxFF and writing to $2004 (OAM data)
uint32 TempAddr = 0, RefreshAddr = 0, DummyRead = 0, NTRefreshAddr = 0;
static int maxsprites = 8;
//scanline is equal to the current visible scanline we're on.
int scanline;
int g_rasterpos;
static uint32 scanlines_per_frame;
uint8 PPU[4];
uint8 PPUSPL;
uint8 NTARAM[0x800], PALRAM[0x20], SPRAM[0x100], SPRBUF[0x100];
uint8 UPALRAM[0x03];//for 0x4/0x8/0xC addresses in palette, the ones in
//0x20 are 0 to not break fceu rendering.
#define MMC5SPRVRAMADR(V) &MMC5SPRVPage[(V) >> 10][(V)]
#define VRAMADR(V) &VPage[(V) >> 10][(V)]
uint8* MMC5BGVRAMADR(uint32 A);
uint8 READPAL_MOTHEROFALL(uint32 A)
{
if(!(A & 3)) {
if(!(A & 0xC))
return READPAL(0x00);
else
return READUPAL(((A & 0xC) >> 2) - 1);
}
else
return READPAL(A & 0x1F);
}
//this duplicates logic which is embedded in the ppu rendering code
//which figures out where to get CHR data from depending on various hack modes
//mostly involving mmc5.
//this might be incomplete.
uint8* FCEUPPU_GetCHR(uint32 vadr, uint32 refreshaddr) {
if (MMC5Hack) {
if (MMC5HackCHRMode == 1) {
uint8 *C = MMC5HackVROMPTR;
C += (((MMC5HackExNTARAMPtr[refreshaddr & 0x3ff]) & 0x3f & MMC5HackVROMMask) << 12) + (vadr & 0xfff);
C += (MMC50x5130 & 0x3) << 18; //11-jun-2009 for kuja_killer
return C;
} else {
return MMC5BGVRAMADR(vadr);
}
} else return VRAMADR(vadr);
}
//likewise for ATTR
int FCEUPPU_GetAttr(int ntnum, int xt, int yt) {
int attraddr = 0x3C0 + ((yt >> 2) << 3) + (xt >> 2);
int temp = (((yt & 2) << 1) + (xt & 2));
int refreshaddr = xt + yt * 32;
if (MMC5Hack && MMC5HackCHRMode == 1)
return (MMC5HackExNTARAMPtr[refreshaddr & 0x3ff] & 0xC0) >> 6;
else
return (vnapage[ntnum][attraddr] & (3 << temp)) >> temp;
}
//new ppu-----
inline void FFCEUX_PPUWrite_Default(uint32 A, uint8 V) {
uint32 tmp = A;
if (PPU_hook) PPU_hook(A);
if (tmp < 0x2000) {
if (PPUCHRRAM & (1 << (tmp >> 10)))
VPage[tmp >> 10][tmp] = V;
} else if (tmp < 0x3F00) {
if (QTAIHack && (qtaintramreg & 1)) {
QTAINTRAM[((((tmp & 0xF00) >> 10) >> ((qtaintramreg >> 1)) & 1) << 10) | (tmp & 0x3FF)] = V;
} else {
if (PPUNTARAM & (1 << ((tmp & 0xF00) >> 10)))
vnapage[((tmp & 0xF00) >> 10)][tmp & 0x3FF] = V;
}
} else {
if (!(tmp & 3)) {
if (!(tmp & 0xC)) {
PALRAM[0x00] = PALRAM[0x04] = PALRAM[0x08] = PALRAM[0x0C] = V & 0x3F;
PALRAM[0x10] = PALRAM[0x14] = PALRAM[0x18] = PALRAM[0x1C] = V & 0x3F;
}
else
UPALRAM[((tmp & 0xC) >> 2) - 1] = V & 0x3F;
} else
PALRAM[tmp & 0x1F] = V & 0x3F;
}
}
volatile int rendercount, vromreadcount, undefinedvromcount, LogAddress = -1;
unsigned char *cdloggervdata = NULL;
unsigned int cdloggerVideoDataSize = 0;
int GetCHRAddress(int A)
{
if (cdloggerVideoDataSize)
{
int result = -1;
if ( (A >= 0) && (A < 0x2000) )
{
result = &VPage[A >> 10][A] - CHRptr[0];
}
if ((result >= 0) && (result < (int)cdloggerVideoDataSize))
{
return result;
}
}
else
{
if ( (A >= 0) && (A < 0x2000) ) return A;
}
return -1;
}
int GetCHROffset(uint8 *ptr) {
int result = ptr - CHRptr[0];
if (cdloggerVideoDataSize) {
if ((result >= 0) && (result < (int)cdloggerVideoDataSize))
return result;
} else {
if ((result >= 0) && (result < 0x2000))
return result;
}
return -1;
}
#define RENDER_LOG(tmp) { \
if (debug_loggingCD) \
{ \
int addr = GetCHRAddress(tmp); \
if (addr != -1) \
{ \
if (!(cdloggervdata[addr] & 1)) \
{ \
cdloggervdata[addr] |= 1; \
if(cdloggerVideoDataSize) { \
if (!(cdloggervdata[addr] & 2)) undefinedvromcount--; \
rendercount++; \
} \
} \
} \
} \
}
#define RENDER_LOGP(tmp) { \
if (debug_loggingCD) \
{ \
int addr = GetCHROffset(tmp); \
if (addr != -1) \
{ \
if (!(cdloggervdata[addr] & 1)) \
{ \
cdloggervdata[addr] |= 1; \
if(cdloggerVideoDataSize) { \
if (!(cdloggervdata[addr] & 2)) undefinedvromcount--; \
rendercount++; \
} \
} \
} \
} \
}
uint8 FASTCALL FFCEUX_PPURead_Default(uint32 A) {
uint32 tmp = A;
if (PPU_hook) PPU_hook(A);
if (tmp < 0x2000) {
return VPage[tmp >> 10][tmp];
} else if (tmp < 0x3F00) {
return vnapage[(tmp >> 10) & 0x3][tmp & 0x3FF];
} else {
uint8 ret;
if (!(tmp & 3)) {
if (!(tmp & 0xC))
ret = READPAL(0x00);
else
ret = READUPAL(((tmp & 0xC) >> 2) - 1);
} else
ret = READPAL(tmp & 0x1F);
return ret;
}
}
uint8 (FASTCALL *FFCEUX_PPURead)(uint32 A) = 0;
void (*FFCEUX_PPUWrite)(uint32 A, uint8 V) = 0;
#define CALL_PPUREAD(A) (FFCEUX_PPURead(A))
#define CALL_PPUWRITE(A, V) (FFCEUX_PPUWrite ? FFCEUX_PPUWrite(A, V) : FFCEUX_PPUWrite_Default(A, V))
//whether to use the new ppu
int newppu = 0;
void ppu_getScroll(int &xpos, int &ypos) {
if (newppu) {
ypos = ppur._vt * 8 + ppur._fv + ppur._v * 256;
xpos = ppur._ht * 8 + ppur.fh + ppur._h * 256;
} else {
xpos = ((RefreshAddr & 0x400) >> 2) | ((RefreshAddr & 0x1F) << 3) | XOffset;
ypos = ((RefreshAddr & 0x3E0) >> 2) | ((RefreshAddr & 0x7000) >> 12);
if (RefreshAddr & 0x800) ypos += 240;
}
}
//---------------
static DECLFR(A2002) {
if (newppu) {
//once we thought we clear latches here, but that caused midframe glitches.
//i think we should only reset the state machine for 2005/2006
//ppur.clear_latches();
}
uint8 ret;
FCEUPPU_LineUpdate();
ret = PPU_status;
ret |= PPUGenLatch & 0x1F;
#ifdef FCEUDEF_DEBUGGER
if (!fceuindbg)
#endif
{
vtoggle = 0;
PPU_status &= 0x7F;
PPUGenLatch = ret;
}
return ret;
}
static DECLFR(A2004) {
if (newppu) {
if ((ppur.status.sl < 241) && PPUON) {
// from cycles 0 to 63, the
// 32 byte OAM buffer gets init
// to 0xFF
if (ppur.status.cycle < 64)
return spr_read.ret = 0xFF;
else {
for (int i = spr_read.last;
i != ppur.status.cycle; ++i) {
if (i < 256) {
switch (spr_read.mode) {
case 0:
if (spr_read.count < 2)
spr_read.ret = (PPU[3] & 0xF8) + (spr_read.count << 2);
else
spr_read.ret = spr_read.count << 2;
spr_read.found_pos[spr_read.found] = spr_read.ret;
spr_read.ret = SPRAM[spr_read.ret];
if (i & 1) {
//odd cycle
//see if in range
if (!((ppur.status.sl - 1 - spr_read.ret) & ~(Sprite16 ? 0xF : 0x7))) {
++spr_read.found;
spr_read.fetch = 1;
spr_read.mode = 1;
} else {
if (++spr_read.count == 64) {
spr_read.mode = 4;
spr_read.count = 0;
} else if (spr_read.found == 8) {
spr_read.fetch = 0;
spr_read.mode = 2;
}
}
}
break;
case 1: //sprite is in range fetch next 3 bytes
if (i & 1) {
++spr_read.fetch;
if (spr_read.fetch == 4) {
spr_read.fetch = 1;
if (++spr_read.count == 64) {
spr_read.count = 0;
spr_read.mode = 4;
} else if (spr_read.found == 8) {
spr_read.fetch = 0;
spr_read.mode = 2;
} else
spr_read.mode = 0;
}
}
if (spr_read.count < 2)
spr_read.ret = (PPU[3] & 0xF8) + (spr_read.count << 2);
else
spr_read.ret = spr_read.count << 2;
spr_read.ret = SPRAM[spr_read.ret | spr_read.fetch];
break;
case 2: //8th sprite fetched
spr_read.ret = SPRAM[(spr_read.count << 2) | spr_read.fetch];
if (i & 1) {
if (!((ppur.status.sl - 1 - SPRAM[((spr_read.count << 2) | spr_read.fetch)]) & ~((Sprite16) ? 0xF : 0x7))) {
spr_read.fetch = 1;
spr_read.mode = 3;
} else {
if (++spr_read.count == 64) {
spr_read.count = 0;
spr_read.mode = 4;
}
spr_read.fetch =
(spr_read.fetch + 1) & 3;
}
}
spr_read.ret = spr_read.count;
break;
case 3: //9th sprite overflow detected
spr_read.ret = SPRAM[spr_read.count | spr_read.fetch];
if (i & 1) {
if (++spr_read.fetch == 4) {
spr_read.count = (spr_read.count + 1) & 63;
spr_read.mode = 4;
}
}
break;
case 4: //read OAM[n][0] until hblank
if (i & 1)
spr_read.count = (spr_read.count + 1) & 63;
spr_read.fetch = 0;
spr_read.ret = SPRAM[spr_read.count << 2];
break;
}
} else if (i < 320) {
spr_read.ret = (i & 0x38) >> 3;
if (spr_read.found < (spr_read.ret + 1)) {
if (spr_read.num) {
spr_read.ret = SPRAM[252];
spr_read.num = 0;
} else
spr_read.ret = 0xFF;
} else if ((i & 7) < 4) {
spr_read.ret =
SPRAM[spr_read.found_pos[spr_read.ret] | spr_read.fetch++];
if (spr_read.fetch == 4)
spr_read.fetch = 0;
} else
spr_read.ret = SPRAM[spr_read.found_pos [spr_read.ret | 3]];
} else {
if (!spr_read.found)
spr_read.ret = SPRAM[252];
else
spr_read.ret = SPRAM[spr_read.found_pos[0]];
break;
}
}
spr_read.last = ppur.status.cycle;
return spr_read.ret;
}
} else
return SPRAM[PPU[3]];
} else {
FCEUPPU_LineUpdate();
return PPUGenLatch;
}
}
static DECLFR(A200x) { /* Not correct for $2004 reads. */
FCEUPPU_LineUpdate();
return PPUGenLatch;
}
static DECLFR(A2007) {
uint8 ret;
uint32 tmp = RefreshAddr & 0x3FFF;
if (debug_loggingCD) {
if (!DummyRead && (LogAddress != -1)) {
if (!(cdloggervdata[LogAddress] & 2)) {
cdloggervdata[LogAddress] |= 2;
if ((!(cdloggervdata[LogAddress] & 1)) && cdloggerVideoDataSize) undefinedvromcount--;
vromreadcount++;
}
} else
DummyRead = 0;
}
if (newppu) {
ret = VRAMBuffer;
RefreshAddr = ppur.get_2007access() & 0x3FFF;
if ((RefreshAddr & 0x3F00) == 0x3F00) {
//if it is in the palette range bypass the
//delayed read, and what gets filled in the temp
//buffer is the address - 0x1000, also
//if grayscale is set then the return is AND with 0x30
//to get a gray color reading
if (!(tmp & 3)) {
if (!(tmp & 0xC))
ret = READPAL(0x00);
else
ret = READUPAL(((tmp & 0xC) >> 2) - 1);
} else
ret = READPAL(tmp & 0x1F);
VRAMBuffer = CALL_PPUREAD(RefreshAddr - 0x1000);
} else {
if (debug_loggingCD && (RefreshAddr < 0x2000))
LogAddress = GetCHRAddress(RefreshAddr);
VRAMBuffer = CALL_PPUREAD(RefreshAddr);
}
ppur.increment2007(ppur.status.sl >= 0 && ppur.status.sl < 241 && PPUON, INC32 != 0);
RefreshAddr = ppur.get_2007access();
return ret;
} else {
//OLDPPU
FCEUPPU_LineUpdate();
if (tmp >= 0x3F00) { // Palette RAM tied directly to the output data, without VRAM buffer
if (!(tmp & 3)) {
if (!(tmp & 0xC))
ret = READPAL(0x00);
else
ret = READUPAL(((tmp & 0xC) >> 2) - 1);
} else
ret = READPAL(tmp & 0x1F);
#ifdef FCEUDEF_DEBUGGER
if (!fceuindbg)
#endif
{
if ((tmp - 0x1000) < 0x2000)
VRAMBuffer = VPage[(tmp - 0x1000) >> 10][tmp - 0x1000];
else
VRAMBuffer = vnapage[((tmp - 0x1000) >> 10) & 0x3][(tmp - 0x1000) & 0x3FF];
if (PPU_hook) PPU_hook(tmp);
}
} else {
ret = VRAMBuffer;
#ifdef FCEUDEF_DEBUGGER
if (!fceuindbg)
#endif
{
if (PPU_hook) PPU_hook(tmp);
PPUGenLatch = VRAMBuffer;
if (tmp < 0x2000) {
if (debug_loggingCD)
LogAddress = GetCHRAddress(tmp);
if(MMC5Hack && newppu)
VRAMBuffer = *MMC5BGVRAMADR(tmp);
else
VRAMBuffer = VPage[tmp >> 10][tmp];
} else if (tmp < 0x3F00)
VRAMBuffer = vnapage[(tmp >> 10) & 0x3][tmp & 0x3FF];
}
}
#ifdef FCEUDEF_DEBUGGER
if (!fceuindbg)
#endif
{
if ((ScreenON || SpriteON) && (scanline < 240)) {
uint32 rad = RefreshAddr;
if ((rad & 0x7000) == 0x7000) {
rad ^= 0x7000;
if ((rad & 0x3E0) == 0x3A0)
rad ^= 0xBA0;
else if ((rad & 0x3E0) == 0x3e0)
rad ^= 0x3e0;
else
rad += 0x20;
} else
rad += 0x1000;
RefreshAddr = rad;
} else {
if (INC32)
RefreshAddr += 32;
else
RefreshAddr++;
}
if (PPU_hook) PPU_hook(RefreshAddr & 0x3fff);
}
return ret;
}
}
static DECLFW(B2000) {
FCEUPPU_LineUpdate();
PPUGenLatch = V;
if (!(PPU[0] & 0x80) && (V & 0x80) && (PPU_status & 0x80))
TriggerNMI2();
PPU[0] = V;
TempAddr &= 0xF3FF;
TempAddr |= (V & 3) << 10;
ppur._h = V & 1;
ppur._v = (V >> 1) & 1;
ppur.s = (V >> 4) & 1;
}
static DECLFW(B2001) {
FCEUPPU_LineUpdate();
if (paldeemphswap)
V = (V&0x9F)|((V&0x40)>>1)|((V&0x20)<<1);
PPUGenLatch = V;
PPU[1] = V;
if (V & 0xE0)
deemp = V >> 5;
}
static DECLFW(B2002) {
PPUGenLatch = V;
}
static DECLFW(B2003) {
PPUGenLatch = V;
PPU[3] = V;
PPUSPL = V & 0x7;
}
static DECLFW(B2004) {
PPUGenLatch = V;
if (newppu) {
//the attribute upper bits are not connected
//so AND them out on write, since reading them
//should return 0 in those bits.
if ((PPU[3] & 3) == 2)
V &= 0xE3;
SPRAM[PPU[3]] = V;
PPU[3] = (PPU[3] + 1) & 0xFF;
} else {
if (PPUSPL >= 8) {
if (PPU[3] >= 8)
SPRAM[PPU[3]] = V;
} else {
SPRAM[PPUSPL] = V;
}
PPU[3]++;
PPUSPL++;
}
}
static DECLFW(B2005) {
uint32 tmp = TempAddr;
FCEUPPU_LineUpdate();
PPUGenLatch = V;
if (!vtoggle) {
tmp &= 0xFFE0;
tmp |= V >> 3;
XOffset = V & 7;
ppur._ht = V >> 3;
ppur.fh = V & 7;
} else {
tmp &= 0x8C1F;
tmp |= ((V & ~0x7) << 2);
tmp |= (V & 7) << 12;
ppur._vt = V >> 3;
ppur._fv = V & 7;
}
TempAddr = tmp;
vtoggle ^= 1;
}
static DECLFW(B2006) {
FCEUPPU_LineUpdate();
PPUGenLatch = V;
if (!vtoggle) {
TempAddr &= 0x00FF;
TempAddr |= (V & 0x3f) << 8;
ppur._vt &= 0x07;
ppur._vt |= (V & 0x3) << 3;
ppur._h = (V >> 2) & 1;
ppur._v = (V >> 3) & 1;
ppur._fv = (V >> 4) & 3;
} else {
TempAddr &= 0xFF00;
TempAddr |= V;
RefreshAddr = TempAddr;
DummyRead = 1;
if (PPU_hook)
PPU_hook(RefreshAddr);
ppur._vt &= 0x18;
ppur._vt |= (V >> 5);
ppur._ht = V & 31;
ppur.install_latches();
}
vtoggle ^= 1;
}
static DECLFW(B2007) {
uint32 tmp = RefreshAddr & 0x3FFF;
if (debug_loggingCD) {
if(!cdloggerVideoDataSize && (tmp < 0x2000))
cdloggervdata[tmp] = 0;
}
if (newppu) {
PPUGenLatch = V;
RefreshAddr = ppur.get_2007access() & 0x3FFF;
CALL_PPUWRITE(RefreshAddr, V);
ppur.increment2007(ppur.status.sl >= 0 && ppur.status.sl < 241 && PPUON, INC32 != 0);
RefreshAddr = ppur.get_2007access();
} else {
PPUGenLatch = V;
if (tmp < 0x2000) {
if (PPUCHRRAM & (1 << (tmp >> 10)))
VPage[tmp >> 10][tmp] = V;
} else if (tmp < 0x3F00) {
if (QTAIHack && (qtaintramreg & 1)) {
QTAINTRAM[((((tmp & 0xF00) >> 10) >> ((qtaintramreg >> 1)) & 1) << 10) | (tmp & 0x3FF)] = V;
} else {
if (PPUNTARAM & (1 << ((tmp & 0xF00) >> 10)))
vnapage[((tmp & 0xF00) >> 10)][tmp & 0x3FF] = V;
}
} else {
if (!(tmp & 3)) {
if (!(tmp & 0xC))
PALRAM[0x00] = PALRAM[0x04] = PALRAM[0x08] = PALRAM[0x0C] = V & 0x3F;
else
UPALRAM[((tmp & 0xC) >> 2) - 1] = V & 0x3F;
} else
PALRAM[tmp & 0x1F] = V & 0x3F;
}
if (INC32)
RefreshAddr += 32;
else
RefreshAddr++;
if (PPU_hook)
PPU_hook(RefreshAddr & 0x3fff);