From 763146e04a8ccfdf844d5f3def8e710bc21301d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mos=C3=A8=20Giordano?= Date: Wed, 16 Feb 2022 20:28:13 +0000 Subject: [PATCH 1/5] [CPUID] Rework how current ISA is determined --- base/Base.jl | 6 +++--- base/cpuid.jl | 29 ++++++++++++++++++++++------- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/base/Base.jl b/base/Base.jl index f39b227d6f663..9ad0cdf7a6661 100644 --- a/base/Base.jl +++ b/base/Base.jl @@ -276,9 +276,6 @@ include("weakkeydict.jl") include("env.jl") -# BinaryPlatforms, used by Artifacts -include("binaryplatforms.jl") - # functions defined in Random function rand end function randn end @@ -336,6 +333,9 @@ using .Order include("sort.jl") using .Sort +# BinaryPlatforms, used by Artifacts. Needs `Sort`. +include("binaryplatforms.jl") + # Fast math include("fastmath.jl") using .FastMath diff --git a/base/cpuid.jl b/base/cpuid.jl index b1fb82cf86dae..fe927179ffe60 100644 --- a/base/cpuid.jl +++ b/base/cpuid.jl @@ -56,9 +56,9 @@ const ISAs_by_family = Dict( "aarch64" => [ # Implicit in all sets, because always required: fp, asimd "armv8.0-a" => ISA(Set{UInt32}()), - "armv8.1-a" => ISA(Set((JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))), - "armv8.2-a+crypto" => ISA(Set((JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))), - "armv8.4-a+crypto+sve" => ISA(Set((JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_fp16fml, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_dotprod, JL_AArch64_sve))), + "armv8.1-a" => ISA(Set((JL_AArch64_v8_1a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))), + "armv8.2-a+crypto" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))), + "armv8.4-a+crypto+sve" => ISA(Set((JL_AArch64_v8_4a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_fp16fml, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_dotprod, JL_AArch64_sve))), ], "powerpc64le" => [ # We have no way to test powerpc64le features yet, so we're only going to declare the lowest ISA: @@ -88,14 +88,29 @@ function normalize_arch(arch::String) return arch end +const ALL_FEATURES = let + get_features(prefix::String) = + getfield.(Ref(@__MODULE__), filter(n -> startswith(String(n), prefix), (names(@__MODULE__; all=true)))) + Dict( + "i686" => get_features("JL_X86"), + "x86_64" => get_features("JL_X86"), + "armv6l" => get_features("JL_AArch32"), + "armv7l" => get_features("JL_AArch32"), + "aarch64" => get_features("JL_AArch64"), + "powerpc64le" => UInt32[], + ) +end + +# Use `@eval` to statically determine the list of features for the current architecture. +@eval function cpu_isa() + return ISA(Set{UInt32}(feat for feat in $(ALL_FEATURES[normalize_arch(String(Sys.ARCH))]) if test_cpu_feature(feat))) +end + """ cpu_isa() Return the [`ISA`](@ref) (instruction set architecture) of the current CPU. """ -function cpu_isa() - all_features = last(last(get(ISAs_by_family, normalize_arch(String(Sys.ARCH)), "" => [ISA(Set{UInt32}())]))).features - return ISA(Set{UInt32}(feat for feat in all_features if test_cpu_feature(feat))) -end +cpu_isa end # module CPUID From 8abda40e18bfc3cb3d0a8432a9826ebdd1e8d655 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mos=C3=A8=20Giordano?= Date: Wed, 16 Feb 2022 00:36:45 +0000 Subject: [PATCH 2/5] [CPUID] Add ISA entry for A64FX --- base/binaryplatforms.jl | 2 +- base/cpuid.jl | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/base/binaryplatforms.jl b/base/binaryplatforms.jl index efc58dc6c6b7a..ff9f98312ce0d 100644 --- a/base/binaryplatforms.jl +++ b/base/binaryplatforms.jl @@ -608,7 +608,7 @@ const arch_march_isa_mapping = let "armv8_0" => get_set("aarch64", "armv8.0-a"), "armv8_1" => get_set("aarch64", "armv8.1-a"), "armv8_2_crypto" => get_set("aarch64", "armv8.2-a+crypto"), - "armv8_4_crypto_sve" => get_set("aarch64", "armv8.4-a+crypto+sve"), + "a64fx" => get_set("aarch64", "a64fx"), ], "powerpc64le" => [ "power8" => get_set("powerpc64le", "power8"), diff --git a/base/cpuid.jl b/base/cpuid.jl index fe927179ffe60..ce13f4c8b3efa 100644 --- a/base/cpuid.jl +++ b/base/cpuid.jl @@ -58,6 +58,7 @@ const ISAs_by_family = Dict( "armv8.0-a" => ISA(Set{UInt32}()), "armv8.1-a" => ISA(Set((JL_AArch64_v8_1a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))), "armv8.2-a+crypto" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))), + "a64fx" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fullfp16, JL_AArch64_sve))), "armv8.4-a+crypto+sve" => ISA(Set((JL_AArch64_v8_4a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_fp16fml, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_dotprod, JL_AArch64_sve))), ], "powerpc64le" => [ From 2b44fcc32544d34261205163468928996914f7ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mos=C3=A8=20Giordano?= Date: Wed, 16 Feb 2022 20:31:54 +0000 Subject: [PATCH 3/5] [CPUID] Add ISA entry for Apple Silicon M1 --- base/binaryplatforms.jl | 1 + base/cpuid.jl | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/base/binaryplatforms.jl b/base/binaryplatforms.jl index ff9f98312ce0d..61e1af796999d 100644 --- a/base/binaryplatforms.jl +++ b/base/binaryplatforms.jl @@ -609,6 +609,7 @@ const arch_march_isa_mapping = let "armv8_1" => get_set("aarch64", "armv8.1-a"), "armv8_2_crypto" => get_set("aarch64", "armv8.2-a+crypto"), "a64fx" => get_set("aarch64", "a64fx"), + "apple_m1" => get_set("aarch64", "apple_m1"), ], "powerpc64le" => [ "power8" => get_set("powerpc64le", "power8"), diff --git a/base/cpuid.jl b/base/cpuid.jl index ce13f4c8b3efa..8f323e3607431 100644 --- a/base/cpuid.jl +++ b/base/cpuid.jl @@ -59,7 +59,7 @@ const ISAs_by_family = Dict( "armv8.1-a" => ISA(Set((JL_AArch64_v8_1a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))), "armv8.2-a+crypto" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))), "a64fx" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fullfp16, JL_AArch64_sve))), - "armv8.4-a+crypto+sve" => ISA(Set((JL_AArch64_v8_4a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_fp16fml, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_dotprod, JL_AArch64_sve))), + "apple_m1" => ISA(Set((JL_AArch64_v8_5a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_sha3, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fp16fml, JL_AArch64_fullfp16, JL_AArch64_dotprod, JL_AArch64_rcpc, JL_AArch64_altnzcv))), ], "powerpc64le" => [ # We have no way to test powerpc64le features yet, so we're only going to declare the lowest ISA: From 22eb7a9973ada72159503ee566f42bbb7597d887 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mos=C3=A8=20Giordano?= Date: Wed, 16 Feb 2022 23:09:16 +0000 Subject: [PATCH 4/5] [CPUID] Simplify collection of full set of features for architecture --- base/cpuid.jl | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/base/cpuid.jl b/base/cpuid.jl index 8f323e3607431..6883c465f28fe 100644 --- a/base/cpuid.jl +++ b/base/cpuid.jl @@ -89,22 +89,20 @@ function normalize_arch(arch::String) return arch end -const ALL_FEATURES = let - get_features(prefix::String) = - getfield.(Ref(@__MODULE__), filter(n -> startswith(String(n), prefix), (names(@__MODULE__; all=true)))) - Dict( - "i686" => get_features("JL_X86"), - "x86_64" => get_features("JL_X86"), - "armv6l" => get_features("JL_AArch32"), - "armv7l" => get_features("JL_AArch32"), - "aarch64" => get_features("JL_AArch64"), - "powerpc64le" => UInt32[], - ) -end +let + # Collect all relevant features for the current architecture, if any. + FEATURES = UInt32[] + arch = normalize_arch(String(Sys.ARCH)) + if arch in keys(ISAs_by_family) + for isa in ISAs_by_family[arch] + unique!(append!(FEATURES, last(isa).features)) + end + end -# Use `@eval` to statically determine the list of features for the current architecture. -@eval function cpu_isa() - return ISA(Set{UInt32}(feat for feat in $(ALL_FEATURES[normalize_arch(String(Sys.ARCH))]) if test_cpu_feature(feat))) + # Use `@eval` to inline the list of features. + @eval function cpu_isa() + return ISA(Set{UInt32}(feat for feat in $(FEATURES) if test_cpu_feature(feat))) + end end """ From c5e2d4f3ea63472bb29fe6624b38a2c27846879b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mos=C3=A8=20Giordano?= Date: Sat, 19 Feb 2022 17:14:28 +0000 Subject: [PATCH 5/5] [CPUID] Remove AES from A64FX ISA, not all chips appear to have it --- base/cpuid.jl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/base/cpuid.jl b/base/cpuid.jl index 6883c465f28fe..48930d8064ba9 100644 --- a/base/cpuid.jl +++ b/base/cpuid.jl @@ -58,7 +58,7 @@ const ISAs_by_family = Dict( "armv8.0-a" => ISA(Set{UInt32}()), "armv8.1-a" => ISA(Set((JL_AArch64_v8_1a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))), "armv8.2-a+crypto" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))), - "a64fx" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fullfp16, JL_AArch64_sve))), + "a64fx" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_sha2, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fullfp16, JL_AArch64_sve))), "apple_m1" => ISA(Set((JL_AArch64_v8_5a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_sha3, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fp16fml, JL_AArch64_fullfp16, JL_AArch64_dotprod, JL_AArch64_rcpc, JL_AArch64_altnzcv))), ], "powerpc64le" => [