-
-
Notifications
You must be signed in to change notification settings - Fork 5.4k
/
processor_arm.cpp
1873 lines (1769 loc) · 65 KB
/
processor_arm.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// This file is a part of Julia. License is MIT: https://julialang.org/license
// ARM (AArch32/AArch64) specific processor detection and dispatch
#include <sys/stat.h>
#include <sys/utsname.h>
#include <fcntl.h>
#include <set>
#include <fstream>
#include <algorithm>
// This nesting is required to allow compilation on musl
#define USE_DYN_GETAUXVAL
#if defined(_OS_LINUX_) && defined(_CPU_AARCH64_)
# undef USE_DYN_GETAUXVAL
# include <sys/auxv.h>
#elif defined(__GLIBC_PREREQ)
# if __GLIBC_PREREQ(2, 16)
# undef USE_DYN_GETAUXVAL
# include <sys/auxv.h>
# endif
#endif
namespace ARM {
enum class CPU : uint32_t {
generic = 0,
// Architecture targets
armv7_a,
armv7_m,
armv7e_m,
armv7_r,
armv8_a,
armv8_m_base,
armv8_m_main,
armv8_r,
armv8_1_a,
armv8_2_a,
armv8_3_a,
armv8_4_a,
armv8_5_a,
armv8_6_a,
// ARM
// armv6l
arm_mpcore,
arm_1136jf_s,
arm_1156t2f_s,
arm_1176jzf_s,
arm_cortex_m0,
arm_cortex_m1,
// armv7ml
arm_cortex_m3,
arm_cortex_m4,
arm_cortex_m7,
// armv7l
arm_cortex_a5,
arm_cortex_a7,
arm_cortex_a8,
arm_cortex_a9,
arm_cortex_a12,
arm_cortex_a15,
arm_cortex_a17,
arm_cortex_r4,
arm_cortex_r5,
arm_cortex_r7,
arm_cortex_r8,
// armv8ml
arm_cortex_m23,
arm_cortex_m33,
// armv8l
arm_cortex_a32,
arm_cortex_r52,
// aarch64
arm_cortex_a34,
arm_cortex_a35,
arm_cortex_a53,
arm_cortex_a55,
arm_cortex_a57,
arm_cortex_a65,
arm_cortex_a65ae,
arm_cortex_a72,
arm_cortex_a73,
arm_cortex_a75,
arm_cortex_a76,
arm_cortex_a76ae,
arm_cortex_a77,
arm_cortex_a78,
arm_cortex_x1,
arm_neoverse_e1,
arm_neoverse_n1,
arm_neoverse_v1,
arm_neoverse_n2,
// Cavium
// aarch64
cavium_thunderx,
cavium_thunderx88,
cavium_thunderx88p1,
cavium_thunderx81,
cavium_thunderx83,
cavium_thunderx2t99,
cavium_thunderx2t99p1,
cavium_octeontx2,
cavium_octeontx2t98,
cavium_octeontx2t96,
cavium_octeontx2f95,
cavium_octeontx2f95n,
cavium_octeontx2f95mm,
// Fujitsu
// aarch64
fujitsu_a64fx,
// HiSilicon
// aarch64
hisilicon_tsv110,
// Huaxingtong
// aarch64
hxt_phecda,
// NVIDIA
// aarch64
nvidia_denver1,
nvidia_denver2,
nvidia_carmel,
// AppliedMicro
// aarch64
apm_xgene1,
apm_xgene2,
apm_xgene3,
// Qualcomm
// armv7l
qualcomm_scorpion,
qualcomm_krait,
// aarch64
qualcomm_kyro,
qualcomm_falkor,
qualcomm_saphira,
// Samsung
// aarch64
samsung_exynos_m1,
samsung_exynos_m2,
samsung_exynos_m3,
samsung_exynos_m4,
samsung_exynos_m5,
// Apple
// armv7l
apple_swift,
// aarch64
apple_a7, // cyclone
apple_a8, // typhoon
apple_a9, // twister
apple_a10, // hurricane
apple_a11,
apple_a12,
apple_a13,
apple_s4,
apple_s5,
// Marvell
// armv7l
marvell_pj4,
// aarch64
marvell_thunderx3t110,
// Intel
// armv7l
intel_3735d,
};
#ifdef _CPU_AARCH64_
static constexpr size_t feature_sz = 3;
static constexpr FeatureName feature_names[] = {
#define JL_FEATURE_DEF(name, bit, llvmver) {#name, bit, llvmver},
#define JL_FEATURE_DEF_NAME(name, bit, llvmver, str) {str, bit, llvmver},
#include "features_aarch64.h"
#undef JL_FEATURE_DEF
#undef JL_FEATURE_DEF_NAME
};
static constexpr uint32_t nfeature_names = sizeof(feature_names) / sizeof(FeatureName);
template<typename... Args>
static inline constexpr FeatureList<feature_sz> get_feature_masks(Args... args)
{
return ::get_feature_masks<feature_sz>(args...);
}
#define JL_FEATURE_DEF_NAME(name, bit, llvmver, str) JL_FEATURE_DEF(name, bit, llvmver)
static constexpr auto feature_masks = get_feature_masks(
#define JL_FEATURE_DEF(name, bit, llvmver) bit,
#include "features_aarch64.h"
#undef JL_FEATURE_DEF
-1);
static const auto real_feature_masks =
feature_masks & FeatureList<feature_sz>{{(uint32_t)-1, (uint32_t)-1, 0}};
namespace Feature {
enum : uint32_t {
#define JL_FEATURE_DEF(name, bit, llvmver) name = bit,
#include "features_aarch64.h"
#undef JL_FEATURE_DEF
};
#undef JL_FEATURE_DEF_NAME
// This does not cover all dependencies (e.g. the ones that depends on arm versions)
static constexpr FeatureDep deps[] = {
{rcpc_immo, rcpc},
{sha3, sha2},
// {sha512, sha3},
{ccdp, ccpp},
{sve, fullfp16},
{fp16fml, fullfp16},
{altnzcv, fmi},
{sve2, sve},
{sve2_aes, sve2},
{sve2_aes, aes},
{sve2_bitperm, sve2},
{sve2_sha3, sve2},
{sve2_sha3, sha3},
{sve2_sm4, sve2},
{sve2_sm4, sm4},
{f32mm, sve},
{f64mm, sve},
};
constexpr auto generic = get_feature_masks();
constexpr auto armv8a_crc = get_feature_masks(crc);
constexpr auto armv8a_crc_crypto = armv8a_crc | get_feature_masks(aes, sha2);
constexpr auto armv8_1a = armv8a_crc | get_feature_masks(v8_1a, lse, rdm); // lor
constexpr auto armv8_1a_crypto = armv8_1a | get_feature_masks(aes, sha2);
constexpr auto armv8_2a = armv8_1a | get_feature_masks(v8_2a, ccpp);
constexpr auto armv8_2a_crypto = armv8_2a | get_feature_masks(aes, sha2);
constexpr auto armv8_3a = armv8_2a | get_feature_masks(v8_3a, jsconv, complxnum, rcpc);
constexpr auto armv8_3a_crypto = armv8_3a | get_feature_masks(aes, sha2);
constexpr auto armv8_4a = armv8_3a | get_feature_masks(v8_4a, dit, rcpc_immo, fmi);
constexpr auto armv8_4a_crypto = armv8_4a | get_feature_masks(aes, sha2);
constexpr auto armv8_5a = armv8_4a | get_feature_masks(v8_5a, sb, ccdp, altnzcv, fptoint);
constexpr auto armv8_6a = armv8_5a | get_feature_masks(v8_6a, i8mm, bf16);
// For ARM cores, the features required can be found in the technical reference manual
// The relevant register values and the features they are related to are:
// ID_AA64ISAR0_EL1:
// .AES: aes, pmull
// .SHA1: sha1
// .SHA2: sha2, sha512
// .CRC32: crc
// .Atomic: les
// .RDM: rdm
// .SHA3: sha3
// .SM3: sm3 (sm4)
// .SM4: sm4
// .DP: dotprod
// .FHM: fp16fml
// .TS: fmi, altnzcz
// .RNDR: rand
// ID_AA64ISAR1_EL1
// .JSCVT: jsconv
// .FCMA: complxnum
// .LRCPC: rcpc, rcpc_immo
// .DPB: ccpp, ccdp
// .SB: sb
// .APA/.API: paca (pa)
// .GPA/.GPI: paga (pa)
// .FRINTTS: fptoint
// .I8MM: i8mm
// .BF16: bf16
// .DGH: dgh
// ID_AA64PFR0_EL1
// .FP: fullfp16
// .SVE: sve
// .DIT: dit
// .BT: bti
// ID_AA64PFR1_EL1
// .SSBS: ssbs
// .MTE: mte
// ID_AA64MMFR2_EL1.AT: uscat
// ID_AA64ZFR0_EL1
// .SVEVer: sve2
// .AES: sve2-aes, sve2-pmull
// .BitPerm: sve2-bitperm
// .SHA3: sve2-sha3
// .SM4: sve2-sm4
// .F32MM: f32mm
// .F64MM: f64mm
constexpr auto arm_cortex_a34 = armv8a_crc;
constexpr auto arm_cortex_a35 = armv8a_crc;
constexpr auto arm_cortex_a53 = armv8a_crc;
constexpr auto arm_cortex_a55 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs);
constexpr auto arm_cortex_a57 = armv8a_crc;
constexpr auto arm_cortex_a65 = armv8_2a | get_feature_masks(rcpc, fullfp16, ssbs);
constexpr auto arm_cortex_a72 = armv8a_crc;
constexpr auto arm_cortex_a73 = armv8a_crc;
constexpr auto arm_cortex_a75 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16);
constexpr auto arm_cortex_a76 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs);
constexpr auto arm_cortex_a77 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs);
constexpr auto arm_cortex_a78 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); // spe
constexpr auto arm_cortex_x1 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); // spe
constexpr auto arm_neoverse_e1 = armv8_2a | get_feature_masks(rcpc, fullfp16, ssbs);
constexpr auto arm_neoverse_n1 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs);
constexpr auto arm_neoverse_v1 = armv8_4a | get_feature_masks(sve, i8mm, bf16, fullfp16, ssbs, rand);
constexpr auto arm_neoverse_n2 = armv8_5a | get_feature_masks(sve, i8mm, bf16, fullfp16, sve2,
sve2_bitperm, rand, mte);
constexpr auto cavium_thunderx = armv8a_crc_crypto;
constexpr auto cavium_thunderx88 = armv8a_crc_crypto;
constexpr auto cavium_thunderx88p1 = armv8a_crc_crypto;
constexpr auto cavium_thunderx81 = armv8a_crc_crypto;
constexpr auto cavium_thunderx83 = armv8a_crc_crypto;
constexpr auto cavium_thunderx2t99 = armv8_1a_crypto;
constexpr auto cavium_thunderx2t99p1 = cavium_thunderx2t99;
constexpr auto cavium_octeontx2 = armv8_2a_crypto;
constexpr auto fujitsu_a64fx = armv8_2a | get_feature_masks(sha2, fullfp16, sve, complxnum);
constexpr auto hisilicon_tsv110 = armv8_2a_crypto | get_feature_masks(dotprod, fullfp16);
constexpr auto hxt_phecda = armv8a_crc_crypto;
constexpr auto marvell_thunderx3t110 = armv8_3a_crypto;
constexpr auto nvidia_denver1 = generic; // TODO? (crc, crypto)
constexpr auto nvidia_denver2 = armv8a_crc_crypto;
constexpr auto nvidia_carmel = armv8_2a_crypto | get_feature_masks(fullfp16);
constexpr auto apm_xgene1 = generic;
constexpr auto apm_xgene2 = generic; // TODO?
constexpr auto apm_xgene3 = generic; // TODO?
constexpr auto qualcomm_kyro = armv8a_crc_crypto;
constexpr auto qualcomm_falkor = armv8a_crc_crypto | get_feature_masks(rdm);
constexpr auto qualcomm_saphira = armv8_4a_crypto;
constexpr auto samsung_exynos_m1 = armv8a_crc_crypto;
constexpr auto samsung_exynos_m2 = armv8a_crc_crypto;
constexpr auto samsung_exynos_m3 = armv8a_crc_crypto;
constexpr auto samsung_exynos_m4 = armv8_2a_crypto | get_feature_masks(dotprod, fullfp16);
constexpr auto samsung_exynos_m5 = samsung_exynos_m4;
constexpr auto apple_a7 = armv8a_crc_crypto;
constexpr auto apple_a10 = armv8a_crc_crypto | get_feature_masks(rdm);
constexpr auto apple_a11 = armv8_2a_crypto | get_feature_masks(fullfp16);
constexpr auto apple_a12 = armv8_3a_crypto | get_feature_masks(fullfp16);
constexpr auto apple_a13 = armv8_4a_crypto | get_feature_masks(fp16fml, fullfp16, sha3);
constexpr auto apple_s4 = apple_a12;
constexpr auto apple_s5 = apple_a12;
}
static constexpr CPUSpec<CPU, feature_sz> cpus[] = {
{"generic", CPU::generic, CPU::generic, 0, Feature::generic},
{"armv8.1-a", CPU::armv8_1_a, CPU::generic, 0, Feature::armv8_1a},
{"armv8.2-a", CPU::armv8_2_a, CPU::generic, 0, Feature::armv8_2a},
{"armv8.3_a", CPU::armv8_3_a, CPU::generic, 0, Feature::armv8_3a},
{"armv8.4-a", CPU::armv8_4_a, CPU::generic, 0, Feature::armv8_4a},
{"armv8.5-a", CPU::armv8_5_a, CPU::generic, 0, Feature::armv8_5a},
{"armv8.6_a", CPU::armv8_6_a, CPU::generic, 0, Feature::armv8_6a},
{"cortex-a34", CPU::arm_cortex_a34, CPU::arm_cortex_a35, 110000, Feature::arm_cortex_a34},
{"cortex-a35", CPU::arm_cortex_a35, CPU::generic, 0, Feature::arm_cortex_a35},
{"cortex-a53", CPU::arm_cortex_a53, CPU::generic, 0, Feature::arm_cortex_a53},
{"cortex-a55", CPU::arm_cortex_a55, CPU::generic, 0, Feature::arm_cortex_a55},
{"cortex-a57", CPU::arm_cortex_a57, CPU::generic, 0, Feature::arm_cortex_a57},
{"cortex-a65", CPU::arm_cortex_a65, CPU::arm_cortex_a75, 100000, Feature::arm_cortex_a65},
{"cortex-a65ae", CPU::arm_cortex_a65ae, CPU::arm_cortex_a75, 100000, Feature::arm_cortex_a65},
{"cortex-a72", CPU::arm_cortex_a72, CPU::generic, 0, Feature::arm_cortex_a72},
{"cortex-a73", CPU::arm_cortex_a73, CPU::generic, 0, Feature::arm_cortex_a73},
{"cortex-a75", CPU::arm_cortex_a75, CPU::generic, 0, Feature::arm_cortex_a75},
{"cortex-a76", CPU::arm_cortex_a76, CPU::generic, 0, Feature::arm_cortex_a76},
{"cortex-a76ae", CPU::arm_cortex_a76ae, CPU::generic, 0, Feature::arm_cortex_a76},
{"cortex-a77", CPU::arm_cortex_a77, CPU::arm_cortex_a76, 110000, Feature::arm_cortex_a77},
{"cortex-a78", CPU::arm_cortex_a78, CPU::arm_cortex_a77, 110000, Feature::arm_cortex_a78},
{"cortex-x1", CPU::arm_cortex_x1, CPU::arm_cortex_a78, 110000, Feature::arm_cortex_x1},
{"neoverse-e1", CPU::arm_neoverse_e1, CPU::arm_cortex_a76, 100000, Feature::arm_neoverse_e1},
{"neoverse-n1", CPU::arm_neoverse_n1, CPU::arm_cortex_a76, 100000, Feature::arm_neoverse_n1},
{"neoverse-v1", CPU::arm_neoverse_v1, CPU::arm_neoverse_n1, UINT32_MAX, Feature::arm_neoverse_v1},
{"neoverse-n2", CPU::arm_neoverse_n2, CPU::arm_neoverse_n1, UINT32_MAX, Feature::arm_neoverse_n2},
{"thunderx", CPU::cavium_thunderx, CPU::generic, 0, Feature::cavium_thunderx},
{"thunderxt88", CPU::cavium_thunderx88, CPU::generic, 0, Feature::cavium_thunderx88},
{"thunderxt88p1", CPU::cavium_thunderx88p1, CPU::cavium_thunderx88, UINT32_MAX,
Feature::cavium_thunderx88p1},
{"thunderxt81", CPU::cavium_thunderx81, CPU::generic, 0, Feature::cavium_thunderx81},
{"thunderxt83", CPU::cavium_thunderx83, CPU::generic, 0, Feature::cavium_thunderx83},
{"thunderx2t99", CPU::cavium_thunderx2t99, CPU::generic, 0, Feature::cavium_thunderx2t99},
{"thunderx2t99p1", CPU::cavium_thunderx2t99p1, CPU::cavium_thunderx2t99, UINT32_MAX,
Feature::cavium_thunderx2t99p1},
{"octeontx2", CPU::cavium_octeontx2, CPU::arm_cortex_a57, UINT32_MAX,
Feature::cavium_octeontx2},
{"octeontx2t98", CPU::cavium_octeontx2t98, CPU::arm_cortex_a57, UINT32_MAX,
Feature::cavium_octeontx2},
{"octeontx2t96", CPU::cavium_octeontx2t96, CPU::arm_cortex_a57, UINT32_MAX,
Feature::cavium_octeontx2},
{"octeontx2f95", CPU::cavium_octeontx2f95, CPU::arm_cortex_a57, UINT32_MAX,
Feature::cavium_octeontx2},
{"octeontx2f95n", CPU::cavium_octeontx2f95n, CPU::arm_cortex_a57, UINT32_MAX,
Feature::cavium_octeontx2},
{"octeontx2f95mm", CPU::cavium_octeontx2f95mm, CPU::arm_cortex_a57, UINT32_MAX,
Feature::cavium_octeontx2},
{"a64fx", CPU::fujitsu_a64fx, CPU::generic, 110000, Feature::fujitsu_a64fx},
{"tsv110", CPU::hisilicon_tsv110, CPU::generic, 0, Feature::hisilicon_tsv110},
{"phecda", CPU::hxt_phecda, CPU::qualcomm_falkor, UINT32_MAX, Feature::hxt_phecda},
{"denver1", CPU::nvidia_denver1, CPU::generic, UINT32_MAX, Feature::nvidia_denver1},
{"denver2", CPU::nvidia_denver2, CPU::generic, UINT32_MAX, Feature::nvidia_denver2},
{"carmel", CPU::nvidia_carmel, CPU::generic, 110000, Feature::nvidia_carmel},
{"xgene1", CPU::apm_xgene1, CPU::generic, UINT32_MAX, Feature::apm_xgene1},
{"xgene2", CPU::apm_xgene2, CPU::generic, UINT32_MAX, Feature::apm_xgene2},
{"xgene3", CPU::apm_xgene3, CPU::generic, UINT32_MAX, Feature::apm_xgene3},
{"kyro", CPU::qualcomm_kyro, CPU::generic, 0, Feature::qualcomm_kyro},
{"falkor", CPU::qualcomm_falkor, CPU::generic, 0, Feature::qualcomm_falkor},
{"saphira", CPU::qualcomm_saphira, CPU::generic, 0, Feature::qualcomm_saphira},
{"exynos-m1", CPU::samsung_exynos_m1, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m1},
{"exynos-m2", CPU::samsung_exynos_m2, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m2},
{"exynos-m3", CPU::samsung_exynos_m3, CPU::generic, 0, Feature::samsung_exynos_m3},
{"exynos-m4", CPU::samsung_exynos_m4, CPU::generic, 0, Feature::samsung_exynos_m4},
{"exynos-m5", CPU::samsung_exynos_m5, CPU::samsung_exynos_m4, 110000,
Feature::samsung_exynos_m5},
{"apple-a7", CPU::apple_a7, CPU::generic, 100000, Feature::apple_a7},
{"apple-a8", CPU::apple_a8, CPU::generic, 100000, Feature::apple_a7},
{"apple-a9", CPU::apple_a9, CPU::generic, 100000, Feature::apple_a7},
{"apple-a10", CPU::apple_a10, CPU::generic, 100000, Feature::apple_a10},
{"apple-a11", CPU::apple_a11, CPU::generic, 100000, Feature::apple_a11},
{"apple-a12", CPU::apple_a12, CPU::generic, 100000, Feature::apple_a12},
{"apple-a13", CPU::apple_a13, CPU::generic, 100000, Feature::apple_a13},
{"apple-s4", CPU::apple_s4, CPU::generic, 100000, Feature::apple_s4},
{"apple-s5", CPU::apple_s5, CPU::generic, 100000, Feature::apple_s5},
{"thunderx3t110", CPU::marvell_thunderx3t110, CPU::cavium_thunderx2t99, 110000,
Feature::marvell_thunderx3t110},
};
#else
static constexpr size_t feature_sz = 3;
static constexpr FeatureName feature_names[] = {
#define JL_FEATURE_DEF(name, bit, llvmver) {#name, bit, llvmver},
#define JL_FEATURE_DEF_NAME(name, bit, llvmver, str) {str, bit, llvmver},
#include "features_aarch32.h"
#undef JL_FEATURE_DEF
#undef JL_FEATURE_DEF_NAME
};
static constexpr uint32_t nfeature_names = sizeof(feature_names) / sizeof(FeatureName);
template<typename... Args>
static inline constexpr FeatureList<feature_sz> get_feature_masks(Args... args)
{
return ::get_feature_masks<feature_sz>(args...);
}
#define JL_FEATURE_DEF_NAME(name, bit, llvmver, str) JL_FEATURE_DEF(name, bit, llvmver)
static constexpr auto feature_masks = get_feature_masks(
#define JL_FEATURE_DEF(name, bit, llvmver) bit,
#include "features_aarch32.h"
#undef JL_FEATURE_DEF
-1);
static const auto real_feature_masks =
feature_masks & FeatureList<feature_sz>{{(uint32_t)-1, (uint32_t)-1, 0}};
namespace Feature {
enum : uint32_t {
#define JL_FEATURE_DEF(name, bit, llvmver) name = bit,
#include "features_aarch32.h"
#undef JL_FEATURE_DEF
};
#undef JL_FEATURE_DEF_NAME
// This does not cover all dependencies (e.g. the ones that depends on arm versions)
static constexpr FeatureDep deps[] = {
{neon, vfp3},
{vfp4, vfp3},
{crypto, neon},
};
// These are the real base requirements of the specific architectures
constexpr auto _armv7m = get_feature_masks(v7, mclass, hwdiv);
constexpr auto _armv7a = get_feature_masks(v7, aclass);
constexpr auto _armv7r = get_feature_masks(v7, rclass);
constexpr auto _armv8m = get_feature_masks(v7, v8, mclass, hwdiv);
constexpr auto _armv8a = get_feature_masks(v7, v8, aclass, neon, vfp3, vfp4, d32,
hwdiv, hwdiv_arm);
constexpr auto _armv8r = get_feature_masks(v7, v8, rclass, neon, vfp3, vfp4, d32,
hwdiv, hwdiv_arm);
// Set `generic` to match the feature requirement of the `C` code.
// we'll require at least these when compiling the sysimg.
#if __ARM_ARCH >= 8
# if !defined(__ARM_ARCH_PROFILE)
constexpr auto generic = get_feature_masks(v7, v8, hwdiv);
# elif __ARM_ARCH_PROFILE == 'A'
constexpr auto generic = _armv8a;
# elif __ARM_ARCH_PROFILE == 'R'
constexpr auto generic = _armv8r;
# elif __ARM_ARCH_PROFILE == 'M'
constexpr auto generic = _armv8m;
# else
constexpr auto generic = get_feature_masks(v7, v8, hwdiv);
# endif
#elif __ARM_ARCH == 7
# if !defined(__ARM_ARCH_PROFILE)
constexpr auto generic = get_feature_masks(v7);
# elif __ARM_ARCH_PROFILE == 'A'
constexpr auto generic = _armv7a;
# elif __ARM_ARCH_PROFILE == 'R'
constexpr auto generic = _armv7r;
# elif __ARM_ARCH_PROFILE == 'M'
constexpr auto generic = _armv7m;
# else
constexpr auto generic = get_feature_masks(v7);
# endif
#else
constexpr auto generic = get_feature_masks();
#endif
// All feature sets below should use or be or'ed with one of these (or generic).
// This makes sure that, for example, the `generic` target on `armv7-a` binary is equivalent
// to the `armv7-a` target.
constexpr auto armv7m = generic | _armv7m;
constexpr auto armv7a = generic | _armv7a;
constexpr auto armv7r = generic | _armv7r;
constexpr auto armv8m = generic | _armv8m;
constexpr auto armv8a = generic | _armv8a;
constexpr auto armv8r = generic | _armv8r;
// armv7l
constexpr auto arm_cortex_a5 = armv7a;
constexpr auto arm_cortex_a7 = armv7a | get_feature_masks(vfp3, vfp4, neon);
constexpr auto arm_cortex_a8 = armv7a | get_feature_masks(d32, vfp3, neon);
constexpr auto arm_cortex_a9 = armv7a;
constexpr auto arm_cortex_a12 = armv7a | get_feature_masks(d32, vfp3, vfp4, neon);
constexpr auto arm_cortex_a15 = armv7a | get_feature_masks(d32, vfp3, vfp4, neon);
constexpr auto arm_cortex_a17 = armv7a | get_feature_masks(d32, vfp3, vfp4, neon);
constexpr auto arm_cortex_r4 = armv7r | get_feature_masks(vfp3, hwdiv);
constexpr auto arm_cortex_r5 = armv7r | get_feature_masks(vfp3, hwdiv, hwdiv_arm);
constexpr auto arm_cortex_r7 = armv7r | get_feature_masks(vfp3, hwdiv, hwdiv_arm);
constexpr auto arm_cortex_r8 = armv7r | get_feature_masks(vfp3, hwdiv, hwdiv_arm);
constexpr auto qualcomm_scorpion = armv7a | get_feature_masks(v7, aclass, vfp3, neon);
constexpr auto qualcomm_krait = armv7a | get_feature_masks(vfp3, vfp4, neon, hwdiv, hwdiv_arm);
constexpr auto apple_swift = armv7a | get_feature_masks(d32, vfp3, vfp4, neon, hwdiv, hwdiv_arm);
constexpr auto marvell_pj4 = armv7a | get_feature_masks(vfp3);
constexpr auto intel_3735d = armv7a | get_feature_masks(vfp3, neon);
// armv8ml
constexpr auto arm_cortex_m23 = armv8m; // unsupported
constexpr auto arm_cortex_m33 = armv8m | get_feature_masks(v8_m_main); // unsupported
// armv8l
constexpr auto armv8a_crc = armv8a | get_feature_masks(crc);
constexpr auto armv8_1a = armv8a_crc | get_feature_masks(v8_1a);
constexpr auto armv8_2a = armv8_1a | get_feature_masks(v8_2a);
constexpr auto armv8a_crc_crypto = armv8a_crc | get_feature_masks(crypto);
constexpr auto armv8_2a_crypto = armv8_2a | get_feature_masks(crypto);
constexpr auto armv8_3a = armv8_2a | get_feature_masks(v8_3a);
constexpr auto armv8_3a_crypto = armv8_3a | get_feature_masks(crypto);
constexpr auto armv8_4a = armv8_3a | get_feature_masks(v8_4a);
constexpr auto armv8_4a_crypto = armv8_4a | get_feature_masks(crypto);
constexpr auto armv8_5a = armv8_4a | get_feature_masks(v8_5a);
constexpr auto armv8_5a_crypto = armv8_5a | get_feature_masks(crypto);
constexpr auto armv8_6a = armv8_5a | get_feature_masks(v8_6a);
constexpr auto armv8_6a_crypto = armv8_6a | get_feature_masks(crypto);
constexpr auto arm_cortex_a32 = armv8a_crc;
constexpr auto arm_cortex_r52 = armv8a_crc;
constexpr auto arm_cortex_a35 = armv8a_crc;
constexpr auto arm_cortex_a53 = armv8a_crc;
constexpr auto arm_cortex_a55 = armv8_2a;
constexpr auto arm_cortex_a57 = armv8a_crc;
constexpr auto arm_cortex_a72 = armv8a_crc;
constexpr auto arm_cortex_a73 = armv8a_crc;
constexpr auto arm_cortex_a75 = armv8_2a;
constexpr auto arm_cortex_a76 = armv8_2a;
constexpr auto arm_cortex_a77 = armv8_2a;
constexpr auto arm_cortex_a78 = armv8_2a;
constexpr auto arm_cortex_x1 = armv8_2a;
constexpr auto arm_neoverse_n1 = armv8_2a;
constexpr auto arm_neoverse_v1 = armv8_4a;
constexpr auto arm_neoverse_n2 = armv8_5a;
constexpr auto nvidia_denver1 = armv8a; // TODO? (crc, crypto)
constexpr auto nvidia_denver2 = armv8a_crc_crypto;
constexpr auto apm_xgene1 = armv8a;
constexpr auto apm_xgene2 = armv8a; // TODO?
constexpr auto apm_xgene3 = armv8a; // TODO?
constexpr auto qualcomm_kyro = armv8a_crc_crypto;
constexpr auto qualcomm_falkor = armv8a_crc_crypto;
constexpr auto qualcomm_saphira = armv8_3a_crypto;
constexpr auto samsung_exynos_m1 = armv8a_crc_crypto;
constexpr auto samsung_exynos_m2 = armv8a_crc_crypto;
constexpr auto samsung_exynos_m3 = armv8a_crc_crypto;
constexpr auto samsung_exynos_m4 = armv8_2a_crypto;
constexpr auto samsung_exynos_m5 = samsung_exynos_m4;
constexpr auto apple_a7 = armv8a_crc_crypto;
}
static constexpr CPUSpec<CPU, feature_sz> cpus[] = {
{"generic", CPU::generic, CPU::generic, 0, Feature::generic},
// armv6
{"mpcore", CPU::arm_mpcore, CPU::generic, 0, Feature::generic},
{"arm1136jf-s", CPU::arm_1136jf_s, CPU::generic, 0, Feature::generic},
{"arm1156t2f-s", CPU::arm_1156t2f_s, CPU::generic, 0, Feature::generic},
{"arm1176jzf-s", CPU::arm_1176jzf_s, CPU::generic, 0, Feature::generic},
{"cortex-m0", CPU::arm_cortex_m0, CPU::generic, 0, Feature::generic},
{"cortex-m1", CPU::arm_cortex_m1, CPU::generic, 0, Feature::generic},
// armv7ml
{"armv7-m", CPU::armv7_m, CPU::generic, 0, Feature::armv7m},
{"armv7e-m", CPU::armv7e_m, CPU::generic, 0, Feature::armv7m},
{"cortex-m3", CPU::arm_cortex_m3, CPU::generic, 0, Feature::armv7m},
{"cortex-m4", CPU::arm_cortex_m4, CPU::generic, 0, Feature::armv7m},
{"cortex-m7", CPU::arm_cortex_m7, CPU::generic, 0, Feature::armv7m},
// armv7l
{"armv7-a", CPU::armv7_a, CPU::generic, 0, Feature::armv7a},
{"armv7-r", CPU::armv7_r, CPU::generic, 0, Feature::armv7r},
{"cortex-a5", CPU::arm_cortex_a5, CPU::generic, 0, Feature::arm_cortex_a5},
{"cortex-a7", CPU::arm_cortex_a7, CPU::generic, 0, Feature::arm_cortex_a7},
{"cortex-a8", CPU::arm_cortex_a8, CPU::generic, 0, Feature::arm_cortex_a8},
{"cortex-a9", CPU::arm_cortex_a9, CPU::generic, 0, Feature::arm_cortex_a9},
{"cortex-a12", CPU::arm_cortex_a12, CPU::generic, 0, Feature::arm_cortex_a12},
{"cortex-a15", CPU::arm_cortex_a15, CPU::generic, 0, Feature::arm_cortex_a15},
{"cortex-a17", CPU::arm_cortex_a17, CPU::generic, 0, Feature::arm_cortex_a17},
{"cortex-r4", CPU::arm_cortex_r4, CPU::generic, 0, Feature::arm_cortex_r4},
{"cortex-r5", CPU::arm_cortex_r5, CPU::generic, 0, Feature::arm_cortex_r5},
{"cortex-r7", CPU::arm_cortex_r7, CPU::generic, 0, Feature::arm_cortex_r7},
{"cortex-r8", CPU::arm_cortex_r8, CPU::generic, 0, Feature::arm_cortex_r8},
{"scorpion", CPU::qualcomm_scorpion, CPU::armv7_a, UINT32_MAX, Feature::qualcomm_scorpion},
{"krait", CPU::qualcomm_krait, CPU::generic, 0, Feature::qualcomm_krait},
{"swift", CPU::apple_swift, CPU::generic, 0, Feature::apple_swift},
{"pj4", CPU::marvell_pj4, CPU::armv7_a, UINT32_MAX, Feature::marvell_pj4},
{"3735d", CPU::intel_3735d, CPU::armv7_a, UINT32_MAX, Feature::intel_3735d},
// armv8ml
{"armv8-m.base", CPU::armv8_m_base, CPU::generic, 0, Feature::armv8m},
{"armv8-m.main", CPU::armv8_m_main, CPU::generic, 0, Feature::armv8m},
{"cortex-m23", CPU::arm_cortex_m23, CPU::armv8_m_base, 0, Feature::arm_cortex_m23},
{"cortex-m33", CPU::arm_cortex_m33, CPU::armv8_m_main, 0, Feature::arm_cortex_m33},
// armv8l
{"armv8-a", CPU::armv8_a, CPU::generic, 0, Feature::armv8a},
{"armv8-r", CPU::armv8_r, CPU::generic, 0, Feature::armv8r},
{"armv8.1-a", CPU::armv8_1_a, CPU::generic, 0, Feature::armv8_1a},
{"armv8.2-a", CPU::armv8_2_a, CPU::generic, 0, Feature::armv8_2a},
{"armv8.3-a", CPU::armv8_3_a, CPU::generic, 0, Feature::armv8_3a},
{"armv8.4-a", CPU::armv8_4_a, CPU::generic, 0, Feature::armv8_4a},
{"armv8.5-a", CPU::armv8_5_a, CPU::generic, 0, Feature::armv8_5a},
{"armv8.6_a", CPU::armv8_6_a, CPU::generic, 0, Feature::armv8_6a},
{"cortex-a32", CPU::arm_cortex_a32, CPU::generic, 0, Feature::arm_cortex_a32},
{"cortex-r52", CPU::arm_cortex_r52, CPU::generic, 0, Feature::arm_cortex_r52},
{"cortex-a35", CPU::arm_cortex_a35, CPU::generic, 0, Feature::arm_cortex_a35},
{"cortex-a53", CPU::arm_cortex_a53, CPU::generic, 0, Feature::arm_cortex_a53},
{"cortex-a55", CPU::arm_cortex_a55, CPU::generic, 0, Feature::arm_cortex_a55},
{"cortex-a57", CPU::arm_cortex_a57, CPU::generic, 0, Feature::arm_cortex_a57},
{"cortex-a72", CPU::arm_cortex_a72, CPU::generic, 0, Feature::arm_cortex_a72},
{"cortex-a73", CPU::arm_cortex_a73, CPU::generic, 0, Feature::arm_cortex_a73},
{"cortex-a75", CPU::arm_cortex_a75, CPU::generic, 0, Feature::arm_cortex_a75},
{"cortex-a76", CPU::arm_cortex_a76, CPU::generic, 0, Feature::arm_cortex_a76},
{"cortex-a76ae", CPU::arm_cortex_a76ae, CPU::generic, 0, Feature::arm_cortex_a76},
{"cortex-a77", CPU::arm_cortex_a77, CPU::arm_cortex_a76, 110000, Feature::arm_cortex_a77},
{"cortex-a78", CPU::arm_cortex_a78, CPU::arm_cortex_a77, 110000, Feature::arm_cortex_a78},
{"cortex-x1", CPU::arm_cortex_x1, CPU::arm_cortex_a78, 110000, Feature::arm_cortex_x1},
{"neoverse-n1", CPU::arm_neoverse_n1, CPU::arm_cortex_a76, 100000, Feature::arm_neoverse_n1},
{"neoverse-v1", CPU::arm_neoverse_v1, CPU::arm_neoverse_n1, UINT32_MAX, Feature::arm_neoverse_v1},
{"neoverse-n2", CPU::arm_neoverse_n2, CPU::arm_neoverse_n1, UINT32_MAX, Feature::arm_neoverse_n2},
{"denver1", CPU::nvidia_denver1, CPU::arm_cortex_a53, UINT32_MAX, Feature::nvidia_denver1},
{"denver2", CPU::nvidia_denver2, CPU::arm_cortex_a57, UINT32_MAX, Feature::nvidia_denver2},
{"xgene1", CPU::apm_xgene1, CPU::armv8_a, UINT32_MAX, Feature::apm_xgene1},
{"xgene2", CPU::apm_xgene2, CPU::armv8_a, UINT32_MAX, Feature::apm_xgene2},
{"xgene3", CPU::apm_xgene3, CPU::armv8_a, UINT32_MAX, Feature::apm_xgene3},
{"kyro", CPU::qualcomm_kyro, CPU::armv8_a, UINT32_MAX, Feature::qualcomm_kyro},
{"falkor", CPU::qualcomm_falkor, CPU::armv8_a, UINT32_MAX, Feature::qualcomm_falkor},
{"saphira", CPU::qualcomm_saphira, CPU::armv8_a, UINT32_MAX, Feature::qualcomm_saphira},
{"exynos-m1", CPU::samsung_exynos_m1, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m1},
{"exynos-m2", CPU::samsung_exynos_m2, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m2},
{"exynos-m3", CPU::samsung_exynos_m3, CPU::generic, 0, Feature::samsung_exynos_m3},
{"exynos-m4", CPU::samsung_exynos_m4, CPU::generic, 0, Feature::samsung_exynos_m4},
{"exynos-m5", CPU::samsung_exynos_m5, CPU::samsung_exynos_m4, 110000,
Feature::samsung_exynos_m5},
{"apple-a7", CPU::apple_a7, CPU::generic, 0, Feature::apple_a7},
};
#endif
static constexpr size_t ncpu_names = sizeof(cpus) / sizeof(cpus[0]);
// auxval reader
#ifndef AT_HWCAP
# define AT_HWCAP 16
#endif
#ifndef AT_HWCAP2
# define AT_HWCAP2 26
#endif
#if defined(USE_DYN_GETAUXVAL)
static unsigned long getauxval_procfs(unsigned long type)
{
int fd = open("/proc/self/auxv", O_RDONLY);
if (fd == -1)
return 0;
unsigned long val = 0;
unsigned long buff[2];
while (read(fd, buff, sizeof(buff)) == sizeof(buff)) {
if (buff[0] == 0)
break;
if (buff[0] == type) {
val = buff[1];
break;
}
}
close(fd);
return val;
}
static inline unsigned long jl_getauxval(unsigned long type)
{
// First, try resolving getauxval in libc
auto libc = jl_dlopen(nullptr, JL_RTLD_LOCAL);
static unsigned long (*getauxval_p)(unsigned long) = NULL;
if (getauxval_p == NULL && jl_dlsym(libc, "getauxval", (void **)&getauxval_p, 0)) {
return getauxval_p(type);
}
// If we couldn't resolve it, use procfs.
return getauxval_procfs(type);
}
#else
static inline unsigned long jl_getauxval(unsigned long type)
{
return getauxval(type);
}
#endif
struct CPUID {
uint8_t implementer;
uint8_t variant;
uint16_t part;
bool operator<(const CPUID &right) const
{
if (implementer < right.implementer)
return true;
if (implementer > right.implementer)
return false;
if (part < right.part)
return true;
if (part > right.part)
return false;
return variant < right.variant;
}
};
// /sys/devices/system/cpu/cpu<n>/regs/identification/midr_el1 reader
static inline void get_cpuinfo_sysfs(std::set<CPUID> &res)
{
// This only works on a 64bit 4.7+ kernel
auto dir = opendir("/sys/devices/system/cpu");
if (!dir)
return;
while (auto entry = readdir(dir)) {
if (entry->d_type != DT_DIR)
continue;
if (strncmp(entry->d_name, "cpu", 3) != 0)
continue;
std::string stm;
llvm::raw_string_ostream(stm) << "/sys/devices/system/cpu/" << entry->d_name << "/regs/identification/midr_el1";
std::ifstream file(stm);
if (!file)
continue;
uint64_t val = 0;
file >> std::hex >> val;
if (!file)
continue;
CPUID cpuid = {
uint8_t(val >> 24),
uint8_t((val >> 20) & 0xf),
uint16_t((val >> 4) & 0xfff)
};
res.insert(cpuid);
}
closedir(dir);
}
// Use an external template since lambda's can't be templated in C++11
template<typename T, typename F>
static inline bool try_read_procfs_line(llvm::StringRef line, const char *prefix, T &out,
bool &flag, F &&reset)
{
if (!line.startswith(prefix))
return false;
if (flag)
reset();
flag = line.substr(strlen(prefix)).ltrim("\t :").getAsInteger(0, out);
return true;
}
// /proc/cpuinfo reader
static inline void get_cpuinfo_procfs(std::set<CPUID> &res)
{
std::ifstream file("/proc/cpuinfo");
CPUID cpuid = {0, 0, 0};
bool impl = false;
bool part = false;
bool var = false;
auto reset = [&] () {
if (impl && part)
res.insert(cpuid);
impl = false;
part = false;
var = false;
memset(&cpuid, 0, sizeof(cpuid));
};
for (std::string line; std::getline(file, line);) {
if (line.empty()) {
reset();
continue;
}
try_read_procfs_line(line, "CPU implementer", cpuid.implementer, impl, reset) ||
try_read_procfs_line(line, "CPU variant", cpuid.variant, var, reset) ||
try_read_procfs_line(line, "CPU part", cpuid.part, part, reset);
}
reset();
}
static std::set<CPUID> get_cpuinfo(void)
{
std::set<CPUID> res;
get_cpuinfo_sysfs(res);
if (res.empty())
get_cpuinfo_procfs(res);
return res;
}
static CPU get_cpu_name(CPUID cpuid)
{
switch (cpuid.implementer) {
case 0x41: // 'A': ARM
switch (cpuid.part) {
case 0xb02: return CPU::arm_mpcore;
case 0xb36: return CPU::arm_1136jf_s;
case 0xb56: return CPU::arm_1156t2f_s;
case 0xb76: return CPU::arm_1176jzf_s;
case 0xc05: return CPU::arm_cortex_a5;
case 0xc07: return CPU::arm_cortex_a7;
case 0xc08: return CPU::arm_cortex_a8;
case 0xc09: return CPU::arm_cortex_a9;
case 0xc0d: return CPU::arm_cortex_a12;
case 0xc0f: return CPU::arm_cortex_a15;
case 0xc0e: return CPU::arm_cortex_a17;
case 0xc14: return CPU::arm_cortex_r4;
case 0xc15: return CPU::arm_cortex_r5;
case 0xc17: return CPU::arm_cortex_r7;
case 0xc18: return CPU::arm_cortex_r8;
case 0xc20: return CPU::arm_cortex_m0;
case 0xc21: return CPU::arm_cortex_m1;
case 0xc23: return CPU::arm_cortex_m3;
case 0xc24: return CPU::arm_cortex_m4;
case 0xc27: return CPU::arm_cortex_m7;
case 0xd01: return CPU::arm_cortex_a32;
case 0xd02: return CPU::arm_cortex_a34;
case 0xd03: return CPU::arm_cortex_a53;
case 0xd04: return CPU::arm_cortex_a35;
case 0xd05: return CPU::arm_cortex_a55;
case 0xd06: return CPU::arm_cortex_a65;
case 0xd07: return CPU::arm_cortex_a57;
case 0xd08: return CPU::arm_cortex_a72;
case 0xd09: return CPU::arm_cortex_a73;
case 0xd0a: return CPU::arm_cortex_a75;
case 0xd0b: return CPU::arm_cortex_a76;
case 0xd0c: return CPU::arm_neoverse_n1;
case 0xd0d: return CPU::arm_cortex_a77;
case 0xd0e: return CPU::arm_cortex_a76ae;
case 0xd13: return CPU::arm_cortex_r52;
case 0xd20: return CPU::arm_cortex_m23;
case 0xd21: return CPU::arm_cortex_m33;
// case 0xd22: return CPU::arm_cortex_m55;
case 0xd40: return CPU::arm_neoverse_v1;
case 0xd41: return CPU::arm_cortex_a78;
case 0xd43: return CPU::arm_cortex_a65ae;
case 0xd44: return CPU::arm_cortex_x1;
case 0xd49: return CPU::arm_neoverse_n2;
case 0xd4a: return CPU::arm_neoverse_e1;
default: return CPU::generic;
}
case 0x42: // 'B': Broadcom (Cavium)
switch (cpuid.part) {
// case 0x00f: return CPU::broadcom_brahma_b15;
// case 0x100: return CPU::broadcom_brahma_b53;
case 0x516: return CPU::cavium_thunderx2t99p1;
default: return CPU::generic;
}
case 0x43: // 'C': Cavium
switch (cpuid.part) {
case 0xa0: return CPU::cavium_thunderx;
case 0xa1:
if (cpuid.variant == 0)
return CPU::cavium_thunderx88p1;
return CPU::cavium_thunderx88;
case 0xa2: return CPU::cavium_thunderx81;
case 0xa3: return CPU::cavium_thunderx83;
case 0xaf: return CPU::cavium_thunderx2t99;
case 0xb0: return CPU::cavium_octeontx2;
case 0xb1: return CPU::cavium_octeontx2t98;
case 0xb2: return CPU::cavium_octeontx2t96;
case 0xb3: return CPU::cavium_octeontx2f95;
case 0xb4: return CPU::cavium_octeontx2f95n;
case 0xb5: return CPU::cavium_octeontx2f95mm;
case 0xb8: return CPU::marvell_thunderx3t110;
default: return CPU::generic;
}
case 0x46: // 'F': Fujitsu
switch (cpuid.part) {
case 0x1: return CPU::fujitsu_a64fx;
default: return CPU::generic;
}
case 0x48: // 'H': HiSilicon
switch (cpuid.part) {
case 0xd01: return CPU::hisilicon_tsv110;
case 0xd40: return CPU::arm_cortex_a76; // Kirin 980
default: return CPU::generic;
}
case 0x4e: // 'N': NVIDIA
switch (cpuid.part) {
case 0x000: return CPU::nvidia_denver1;
case 0x003: return CPU::nvidia_denver2;
case 0x004: return CPU::nvidia_carmel;
default: return CPU::generic;
}
case 0x50: // 'P': AppliedMicro
// x-gene 2
// x-gene 3
switch (cpuid.part) {
case 0x000: return CPU::apm_xgene1;
default: return CPU::generic;
}
case 0x51: // 'Q': Qualcomm
switch (cpuid.part) {
case 0x00f:
case 0x02d:
return CPU::qualcomm_scorpion;
case 0x04d:
case 0x06f:
return CPU::qualcomm_krait;
case 0x201: // silver
case 0x205: // gold
case 0x211: // silver
return CPU::qualcomm_kyro;
// kryo 2xx
case 0x800: // gold
return CPU::arm_cortex_a73;
case 0x801: // silver
return CPU::arm_cortex_a53;
// kryo 3xx
case 0x802: // gold
return CPU::arm_cortex_a75;
case 0x803: // silver
return CPU::arm_cortex_a55;
// kryo 4xx
case 0x804: // gold
return CPU::arm_cortex_a76;
case 0x805: // silver
return CPU::arm_cortex_a55;
// kryo 5xx seems to be using ID for cortex-a77 directly
case 0xc00:
return CPU::qualcomm_falkor;
case 0xc01:
return CPU::qualcomm_saphira;
default: return CPU::generic;
}
case 0x53: // 'S': Samsung
if (cpuid.part == 1) {
if (cpuid.variant == 4)
return CPU::samsung_exynos_m2;
return CPU::samsung_exynos_m1;
}
if (cpuid.variant != 1)
return CPU::generic;
switch (cpuid.part) {
case 0x2: return CPU::samsung_exynos_m3;
case 0x3: return CPU::samsung_exynos_m4;
case 0x4: return CPU::samsung_exynos_m5;
default: return CPU::generic;
}
case 0x56: // 'V': Marvell
switch (cpuid.part) {
case 0x581:
case 0x584:
return CPU::marvell_pj4;
default: return CPU::generic;
}
case 0x61: // 'a': Apple
// https://opensource.apple.com/source/xnu/xnu-6153.81.5/osfmk/arm/cpuid.h.auto.html
switch (cpuid.part) {
case 0x0: // Swift
return CPU::apple_swift;
case 0x1: // Cyclone
return CPU::apple_a7;
case 0x2: // Typhoon
case 0x3: // Typhoo/Capri
return CPU::apple_a8;
case 0x4: // Twister
case 0x5: // Twister/Elba/Malta
return CPU::apple_a9;
case 0x6: // Hurricane
case 0x7: // Hurricane/Myst
return CPU::apple_a10;
case 0x8: // Monsoon
case 0x9: // Mistral
return CPU::apple_a11;
case 0xB: // Vortex
case 0xC: // Tempest
case 0x10: // A12X, Vortex Aruba
case 0x11: // A12X, Tempest Aruba
return CPU::apple_a12;
case 0xF: // Tempest M9