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versal-memmap.dtsh
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versal-memmap.dtsh
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/*
* ZynqMP memory region definitions
*
* Copyright (c) 2016, Xilinx Inc
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define MEM_REGION(name, addrH, addrL, addr64, s, c) \
name: name@addr64 { \
compatible = "qemu:memory-region"; \
container = <c>; \
qemu,ram = <QEMU_RAM_PROPERTY>; \
reg = <addrH addrL 0x0 s 0x0 >; \
};
/* The MEM_SPEC macro tells QEMU that memory can be created here, but does
* NOT create memory regions.
* Do not change this macro without changing the QEMU code.
*/
#define MEM_SPEC(name, addrH, addrL, addr64, sizeH, sizeL, c) \
name: name@addr64 { \
compatible = "qemu:memory-region-spec"; \
container = <c>; \
qemu,ram = <QEMU_RAM_PROPERTY>; \
reg = <addrH addrL sizeH sizeL 0x0>; \
};
/* Manual entries. */
#define ACPU_GIC_STRIDE 0x10000
#define ACPU_GIC_DIST 0xF9000000
#define ACPU_GIC_CPUIF 0xF9040000
#define ACPU_GIC_REDIST 0xF9080000
#define R5_GIC_DIST 0xF9000000
#define R5_GIC 0xF9001000
#define MM_PMC_QSPI_DMA 0xf1030800
#define MM_PMC_LQSPI 0xC0000000
#define MM_PMC_LQSPI_SIZE 0x08000000
#define MM_PMC_PPU0_IOM(a) 0xf00800 ## a
#define MM_PMC_PPU1_IOM(a) 0xf02800 ## a
#define MM_PSM_IOM(a) 0xffc800 ## a
/* Split the PMC DMA into a SRC and a DST. */
#define MM_PMC_PMC_DMA0_SRC MM_PMC_PMC_DMA0
#define MM_PMC_PMC_DMA0_DST 0xf11c0800
#define MM_PMC_PMC_DMA1_SRC MM_PMC_PMC_DMA1
#define MM_PMC_PMC_DMA1_DST 0xf11d0800
#define MM_PMC_OSPI_DMA_SRC 0xf1011000
#define MM_PMC_OSPI_DMA_DST 0xf1011800
#define MM_PMC_OSPI_DAC 0xc0000000
/* FIXME: Randomly chosen location for SSS (MM_PMC_PMC_GLOBAL + 0x500). */
#define MM_PMC_PMC_SSS 0xf1110500
#define MM_PRAM_ZEROIZE 0xf1110518
#define MM_PRAM_ZEROIZE_SIZE 4
/* Split PMC_GLOBAL into areas matching separate ods */
#define MM_PMC_PMC_GLOBAL_SYS_SIZE 0x10000
#define MM_PMC_PPU1_PRIVATE 0xf1120000
#define MM_PMC_PPU1_PRIVATE_SIZE 0x10000
#define MM_PMC_PMC_ERR_MANAGEMENT 0xf1130000
#define MM_PMC_PMC_ERR_MANAGEMENT_SIZE 0x10000
#define MM_PMC_PUF_CTRL 0xf1150000
#define MM_PMC_PUF_CTRL_SIZE 0x10000
/* PMC GIC Proxy at MM_PMC_PMC_GLOBAL + 0x30000 offset. */
#define MM_PMC_GIC_PROXY 0xf1140000
#define MM_PMC_GIC_PROXY_SIZE 0x100
#define MM_PSM_GIC_PROXY 0xffc92000
#define MM_PSM_GIC_PROXY_SIZE 0x100
/* IPI Message buffers. */
#define MM_IPI_MSGBUF 0xFF3F0000
#define MM_IPI_MSGBUF_SIZE 0x1000
/* DDRMC as seen from the UBs, not from PMC nor PS. */
#define MM_DDRMC_IOM(a) 0x0001b0 ## a
#define MM_DDRMC_RAM_DATA 0x1c000
#define MM_DDRMC_RAM_DATA_SIZE 0x04000
#define MM_DDRMC_RAM_INSTR 0x20000
#define MM_DDRMC_RAM_INSTR_SIZE 0x20000
#define MM_DDRMC_RAM_EXCHANGE 0x08000
#define MM_DDRMC_RAM_EXCHANGE_SIZE 0x08000
/* Everything before RAM exchange gets mapped to main regs. */
#define MM_DDRMC_NPI_MAIN 0x0
#define MM_DDRMC_NPI_MAIN_SIZE MM_DDRMC_RAM_EXCHANGE
/* Based off MM_TOP_Reserved. */
#define MM_TOP_VIRTIO_MMIO_0 0xa0000000
#define MM_TOP_VIRTIO_MMIO_1 0xa0000200
#define MM_TOP_VIRTIO_MMIO_2 0xa0000400
#define MM_TOP_VIRTIO_MMIO_3 0xa0000600
#define MM_TOP_VIRTIO_MMIO_4 0xa0000800
#define MM_TOP_VIRTIO_MMIO_5 0xa0000A00
#define MM_TOP_VIRTIO_MMIO_6 0xa0000C00
#define MM_TOP_VIRTIO_MMIO_7 0xa0000E00
#define MM_TOP_VIRTIO_MMIO_8 0xa0001000
#define MM_TOP_VIRTIO_MMIO_9 0xa0001200
#define MM_TOP_VIRTIO_MMIO_10 0xa0001400
#define MM_TOP_VIRTIO_MMIO_11 0xa0001600
#define MM_TOP_VIRTIO_MMIO_12 0xa0001800
#define MM_TOP_VIRTIO_MMIO_13 0xa0001A00
#define MM_TOP_VIRTIO_MMIO_14 0xa0001C00
#define MM_TOP_VIRTIO_MMIO_15 0xa0001E00
/* USB dwc3 base */
#define MM_USB_DWC3_0 0xFE20C100 // (MM_USB_XHCI + 0xC100)
#define MM_USB_DWC3_0_SIZE 0x600
/* Include auto-generated files. */
#include "versal-top-memmap.dtsh"
#include "versal-fpd-memmap.dtsh"
#include "versal-pmc-memmap.dtsh"
#include "versal-psm-memmap.dtsh"
#include "versal-iou-memmap.dtsh"
#include "versal-lpd-memmap.dtsh"
#include "versal-npi-memmap.dtsh"
#include "versal-cpm-memmap.dtsh"